AT87C51RD2-3CSUM

TS80C51RA2_08 ATMEL | Alldatasheet

Document overview

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Technical content

1. Features

• 80C52 Compatible – 8051 pin and instruction compatible – Four 8-bit I/O ports – Three 16-bit timer/counters – 256 bytes scratchpad RAM
• High-Speed Architecture – 40 MHz @ 5V, 30MHz @ 3V – X2 Speed Improvement capability (6 clocks/machine cycle) – 30 MHz @ 5V, 20 MHz @ 3V (Equivalent to – 60 MHz @ 5V, 40 MHz @ 3V)
• Dual Data Pointer
• On-chip ROM/EPROM (16K-bytes, 32K-bytes, 64K-bytes)
• On-chip eXpanded RAM (XRAM) (256 or 768 bytes)
• Programmable Clock Out and Up/Down Timer/Counter 2
• Programmable Counter Array with – High Speed Output, – Compare / Capture, – Pulse Width Modulator, – Watchdog Timer Capabilities
• Hardware Watchdog Timer (One-time enabled with Reset-Out)
• 2 extra 8-bit I/O ports available on RD2 with high pin count packages
• Asynchronous port reset
• Interrupt Structure with – 7 Interrupt sources, – 4 level priority interrupt system
• Full duplex Enhanced UART – Framing error detection – Automatic address recognition
• Low EMI (inhibit ALE)
• Power Control modes – Idle mode – Power-down mode – Power-off Flag
• Once mode (On-chip Emulation)
• Power supply: 4.5-5V, 2.7-5.5V
• Temperature ranges: Commercial (0 to 70 oC) and Industrial (-40 to 85 oC)
• Packages: PDIL40, PLCC44, VQFP44 1.4, PLCC68, VQFP64 1.4 2. Description Atmel TS8xC51Rx2 is a high performance CMOS ROM, OT P, EPROM and ROMless versions of the 80C51 CMOS single chip 8-bit microcontroller. The TS8xC51Rx2 retains all features of the 80C51 wi th extended ROM/EPROM capacity (16/32/64 Kbytes), 256 bytes of internal R AM, a 7-source , 4-level interrupt system, an on-chip oscilator and three timer/counters. In addition, the TS80C51Rx2 has a Programmable Counter Array, an XRAM of 256 or 768 bytes, a Hardware Watchdog Timer, a more versatile serial channel that High Performance 8-bit Microcontroller TS80C51RA2 TS83C51RB2 TS83C51RC2 TS83C51RD2 TS87C51RB2 TS87C51RC2 TS87C51RD2 AT80C51RA2 AT83C51RB2 AT83C51RC2 AT83C51RD2 AT87C51RB2 AT87C51RC2 Rev. 4188F–8051–01/08

4188F–8051–01/08 AT/TS8xC51Rx2 facilitates multiprocessor communication (EUART) and an X2 speed improvement mechanism. The fully static design of the TS80C51Rx2 allows to reduce system power consumption by bringing the clock frequency down to any value, even DC, without loss of data. The TS80C51Rx2 has 2 software-selectable modes of r educed activity for further reduction in power consumption. In the idle mode the CPU is froz en while the timers, the serial port and the interrupt system are still operating. In the power- down mode the RAM is saved and all other functions are inoperative. PDIL40 PLCC44 VQFP44 1.4 ROM (bytes) EPROM (bytes) XRAM (bytes) TOTAL RAM (bytes) I/O TS80C51RA2 TS80C51RD2 256 768 512 1024 TS83C51RB2 TS83C51RC2 TS83C51RD2 16k 32k 64k 256 256 768 512 512 1024 TS87C51RB2 TS87C51RC2 TS87C51RD2 16k 32k 64k 256 256 768 512 512 1024 PLCC68 VQFP64 1.4 ROM (bytes) EPROM (bytes) XRAM (bytes) TOTAL RAM (bytes) I/O TS80C51RD2 0 0 768 1024 48 TS83C51RD2 64k 0 768 1024 48 TS87C51RD2 0 64k 768 1024 48

4188F–8051–01/08 AT/TS8xC51Rx2 3. Block Diagram Timer 0 INT RAM 256x8 RxD TxD WR RD EA/VPP PSEN ALE/ XTAL2 XTAL1 EUART CPU Timer 1 INT1 Ctrl INT0 (3) (3) C51 CORE (3) (3) (3) (3) Port 0 Port 1 Port 2 Port 3 Parallel I/O Ports & Ext. Bus XRAM 256/768x8 IB-bus PCA RESET PROG Watch Dog PCA ECI Vss Vcc (3) (3) (1) (1): Alternate function of Port 1 (3): Alternate function of Port 3 (1) Timer2 T2EX (1) (1) Port 5 Port 4 (2): Only available on high pin count packages (2) (2) ROM /EPROM 0/16/32/64Kx8

4188F–8051–01/08 AT/TS8xC51Rx2 4. SFR Mapping The Special Function Registers (SFRs) of the TS80C51Rx2 fall into the following categories:

• C51 core registers: ACC, B, DPH, DPL, PSW, SP, AUXR1
• I/O port registers: P0, P1, P2, P3, P4, P5
• Timer registers: T2CON, T2MOD, TCON, TH0, TH1, TH2 , TMOD, TL0, TL1, TL2, RCAP2L, RCAP2H
• Serial I/O port registers: SADDR, SADEN, SBUF, SCO N
• Power and clock control registers: PCON
• HDW Watchdog Timer Reset: WDTRST, WDTPRG
• PCA registers: CL, CH, CCAPiL, CCAPiH, CCON, CMOD, CCAPMi
• Interrupt system registers: IE, IP, IPH
• Others: AUXR, CKCON

4188F–8051–01/08 AT/TS8xC51Rx2 Table 4-1. All SFRs with their address and their reset value Bit addressable Non Bit addressable F8h CH 0000 0000 CCAP0H XXXX XXXX CCAP1H XXXX XXXX CCAPL2H XXXX XXXX CCAPL3H XXXX XXXX CCAPL4H XXXX XXXX FFh F0h B 0000 0000 F7h E8h P5 bit addressable 1111 1111 CL 0000 0000 CCAP0L XXXX XXXX CCAP1L XXXX XXXX CCAPL2L XXXX XXXX CCAPL3L XXXX XXXX CCAPL4L XXXX XXXX EFh E0h ACC 0000 0000 E7h D8h CCON 00X0 0000 CMOD 00XX X000 CCAPM0 X000 0000 CCAPM1 X000 0000 CCAPM2 X000 0000 CCAPM3 X000 0000 CCAPM4 X000 0000 DFh D0h PSW 0000 0000 D7h C8h T2CON 0000 0000 T2MOD XXXX XX00 RCAP2L 0000 0000 RCAP2H 0000 0000 TL2 0000 0000 TH2 0000 0000 CFh C0h P4 bit addressable 1111 1111 P5 byte addressable 1111 1111 C7h B8h IP X000 000 SADEN 0000 0000 BFh B0h P3 1111 1111 IPH X000 0000 B7h A8h IE 0000 0000 SADDR 0000 0000 AFh A0h P2 1111 1111 AUXR1 XXXX0XX0 WDTRST XXXX XXXX WDTPRG XXXX X000 A7h 98h SCON 0000 0000 SBUF XXXX XXXX 9Fh 90h P1 1111 1111 97h 88h TCON 0000 0000 TMOD 0000 0000 TL0 0000 0000 TL1 0000 0000 TH0 0000 0000 TH1 0000 0000 AUXR XXXXXX00 CKCON XXXX XXX0 8Fh 80h P0 1111 1111 SP 0000 0111 DPL 0000 0000 DPH 0000 0000 PCON 00X1 0000 87h reserved

4188F–8051–01/08 AT/TS8xC51Rx2 5. Pin Configuration P1.7 P1.4 RST P3.0/RxD P3.1/TxD P1.3 P1.5 P1.6 P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD XTAL2 XTAL1 VSS P2.0 / A8 P2.1 / A9 P2.2 / A10 P2.3 / A11 P2.4 / A12 P0.4 / A4 P0.6 / A6 P0.5 / A5 P0.7 / A7 ALE/PROG PSEN EA/VPP P2.7 / A15 P2.5 / A13 P2.6 / A14 P1.0 / T2 P1.2 P1.1 / T2EX VCC P0.0 / A0 P0.1 / A1 P0.2 / A2 P0.3 / A3 PDIL/ 5 4 3 2 1 6 44 43 42 41 40 P1.4 P1.0/T2 P1.1/T2EX P1.3 P1.2 VSS1/NIC* VCC P0.0/AD0 P0.2/AD2 P0.1/AD1 P0.4/AD4 P0.6/AD6 P0.5/AD5 P0.7/AD7 ALE/PROG PSEN EA/VPP NIC* P2.7/A15 P2.5/A13 P2.6/A14 P3.6/WR P3.7/RD XTAL2 XTAL1 VSS P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 43 42 41 40 39 44 38 37 36 35 34 P1.4 P1.0/T2 P1.1/T2EX P1.3 P1.2 VSS1/NIC* VCC P0.0/AD0 P0.2/AD2 P0.3/AD3 P0.1/AD1 P0.4/AD4 P0.6/AD6 P0.5/AD5 P0.7/AD7 ALE/PROG PSEN EA/VPP NIC* P2.7/A15 P2.5/A13 P2.6/A14 P1.5 P1.6 P1.7 RST P3.0/RxD NIC* P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD XTAL2 XTAL1 VSS P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P1.5 P1.6 P1.7 RST P3.0/RxD NIC* P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P0.3/AD3 NIC* NIC* *NIC: No Internal Connection PLCC/CQPJ 44 VQFP44 1.4 CDIL40 18 19 20 21 22 23 24 25 26 27 28 12 13 14 15 16 17 18 19 20 21 22

4188F–8051–01/08 AT/TS8xC51Rx2 P5.5 P0.3/AD3 P0.2/AD2 P5.6 P0.1/AD1 P0.0/AD0 P5.7 VCC NIC P1.0/T2 P4.0 P1.1/T2EX P1.2 P1.3 P4.1 P1.4 P4.2 23567 4 1 68 67 66 65 64 63 36 37 38 39 40 41 29 30 31 32 33 34 35 27 28 42 43 PSEN P5.3 P0.5/AD5 P0.6/AD6 NIC P0.7/AD7 EA/VPP NIC ALE/PROG NIC P2.7/A15 P2.6/A14 P5.2 P0.4/AD4 P5.4 P5.1 P2.5/A13 NIC P1.7 RST NIC NIC NIC P3.0/RxD NIC NIC NIC P3.1/TxD P3.3/INT1 P5.0 P2.4/A12 P2.3/A11 P4.7 P2.2/A10 P2.1/A9 P2.0/A8 VSS P4.6 P4.5 XTAL1 XTAL2 NIC PLCC 68 89 62 61 P1.5 P1.6 P3.4/T0 P3.5/T1 P4.4 P3.6/WR P4.3 P3.7/RD P3.2/INT0 PSEN P5.4 P5.3 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA/VPP NIC ALE/PROG P2.7/A15 P2.6/A14 P5.2 P5.1 P2.5/A13 P5.0 P0.4/AD4 58 50 51 52 53 54 55 56 57 59 60 61 62 63 64 49 VSS P2.3/A11 P4.7 P2.2/A10 P2.1/A9 P2.0/A8 P4.6 P4.5 NIC XTAL1 XTAL2 P3.7/RD P4.4 P4.3 P2.4/A12 P3.6/WR P1.0/T2 P0.3/AD3 P0.2/AD2 P5.6 P0.1/AD1 P0.0/AD0 P5.7 VCC VSS P4.0 P1.1/T2EX P1.2 P1.3 P4.1 P1.4 P5.5 NIC P3.4/T0 P3.2/INT0 P3.1/TxD NIC NIC P3.0/RxD NIC NIC RST P1.7 P1.6 P1.5 P4.2 P3.5/T1 26 18 19 20 21 22 23 24 25 27 28 29 30 31 32 17 VQFP64 1.4 P3.3/INT1 NIC: No InternalConnection

4188F–8051–01/08 AT/TS8xC51Rx2 Mnemonic Pin Number Type Name And Function DIL LCC VQFP 1.4 VSS 20 22 16 I Ground: 0V reference Vss1 1 39 I Optional Ground: Contact the Sales Office for ground connection. VCC 40 44 38 I Power Supply: This is the power supply voltage for normal, idle and power-down operation P0.0-P0.7 39-32 43-36 37-30 I/O Port 0 : Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high impedance inputs. Port 0 pins must be polarized to Vcc or Vss in order to prevent any parasitic curren t consumption. Port 0 is also the multiplexed low-order address and data bus during a ccess to external program and data memory. In this application, it uses strong internal pull-up when emitting 1s. Port 0 also inputs the code bytes during EPROM programming. External pull-ups are required during program verification during which P0 outputs the code bytes. 1-3 I/O Port 1 : Port 1 is an 8-bit bidirectional I/O port with in ternal pull-ups. Port 1 pins that have 1s written to them are pulled high by the inte rnal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally pulled low will source current because of the internal pull-ups. Port 1 also receives the low-order address byte during memory programming and verification. Alternate functions for Port 1 include: 1 2 40 I/O T2 (P1.0): Timer/Counter 2 external count input/Clockout 2 3 41 I T2EX (P1.1): Timer/Counter 2 Reload/Capture/Direction Control 3 4 42 I ECI (P1.2): External Clock for the PCA 4 5 43 I/O CEX0 (P1.3): Capture/Compare External I/O for PCA module 0 5 6 44 I/O CEX1 (P1.4): Capture/Compare External I/O for PCA module 1 6 7 45 I/O CEX0 (P1.5): Capture/Compare External I/O for PCA module 2 7 8 46 I/O CEX0 (P1.6): Capture/Compare External I/O for PCA module 3 8 9 47 I/O CEX0 (P1.7): Capture/Compare External I/O for PCA module 4 P2.0-P2.7 21-28 24-31 18-25 I/O Port 2 : Port 2 is an 8-bit bidirectional I/O port with in ternal pull-ups. Port 2 pins that have 1s written to them are pulled high by the inte rnal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally pulled low will source current because of the internal pull-ups. Port 2 emits the high-ord er address byte during fetches from external program memory and during accesses to exte rnal data memory that use 16- bit addresses (MOVX @DPTR).In this application, it uses strong internal pull-ups emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @Ri), port 2 emits the contents of the P2 SFR. Some Port 2 pins (P2.0 to P2.5) receive the high order address bits during EPROM programmin g and verification: 13-19 7-13 I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with inte rnal pull-ups. Port 3 pins that have 1s written to them are pulled high by the inte rnal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally pulled low will source current because of the internal pull-ups. Some Port 3 pins (P3.4 to P3.5) receive the high order address bits during EPROM programming and verification. Port 3 also serves the special features of the 80C5 1 family, as listed below. 10 11 5 I RXD (P3.0): Serial input port 11 13 7 O TXD (P3.1): Serial output port

4188F–8051–01/08 AT/TS8xC51Rx2

5.1 Pin Description for 64/68 pin Packages

Port 4 and Port 5 are 8-bit bidirectional I/O ports with internal pull-ups. Pins that have 1s written to them are pulled high by the internal pull ups and can be used as inputs. As inputs, pins that are externally pulled low will source current because of the internal pull-ups. Refer to the previous pin description for other pins. Table 5-1. 64/68 Pin Packages Configuration 12 14 8 I INT0 (P3.2): External interrupt 0 13 15 9 I INT1 (P3.3): External interrupt 1 14 16 10 I T0 (P3.4): Timer 0 external input 15 17 11 I T1 (P3.5): Timer 1 external input 16 18 12 O WR (P3.6): External data memory write strobe 17 19 13 O RD (P3.7): External data memory read strobe Reset 9 10 4 I Reset: A high on this pin for two machine cycles while th e oscillator is running, resets the device. An internal diffused resistor to V SS permits a power-on reset using only an external capacitor to V CC. If the hardware watchdog reaches its time-out, the reset pin becomes an output during the time the internal rese t is activated. ALE/PROG 30 33 27 O (I) Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the address during an access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 (1/3 in X2 mode) the oscillato r frequency, and can be used for external timing or clocking. Note that one ALE puls e is skipped during each access to external data memory. This pin is also the program pulse input (PROG ) during EPROM programming. ALE can be disabled by setting SFR’s AUXR.0 bit. With this bit set, ALE will be inactive during internal fetches. PSEN 29 32 26 O Program Store ENable: The read strobe to external program memory. When executing code from the external program memory, PS EN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal prog ram memory. EA /V PP 31 35 29 I External Access Enable/Programming Supply Voltage: EA must be externally held low to enable the device to fetch code from external program memory locations 0000H and 3FFFH (RB) or 7FFFH (RC), or FFFFH (RD). If EA is held high, the device executes from internal program memory unless the pr ogram counter contains an address greater than 3FFFH (RB) or 7FFFH (RC) EA must be held low for ROMless devices. This pin also receives the 12.75V programm ing supply voltage (V PP ) during EPROM programming. If security level 1 is programme d, EA will be internally latched on Reset. XTAL1 19 21 15 I Crystal 1: Input to the inverting oscillator amplifier and inp ut to the internal clock generator circuits. XTAL2 18 20 14 O Crystal 2: Output from the inverting oscillator amplifier Mnemonic Pin Number Type Name And Function DIL LCC VQFP 1.4 Pin PLCC68 SQUARE VQFP64 1.4 VSS 51 9/40 VCC 17 8

4188F–8051–01/08 AT/TS8xC51Rx2 P0.0 15 6 P0.1 14 5 P0.2 12 3 P0.3 11 2 P0.4 9 64 P0.5 6 61 P0.6 5 60 P0.7 3 59 P1.0 19 10 P1.1 21 12 P1.2 22 13 P1.3 23 14 P1.4 25 16 P1.5 27 18 P1.6 28 19 P1.7 29 20 P2.0 54 43 P2.1 55 44 P2.2 56 45 P2.3 58 47 P2.4 59 48 P2.5 61 50 P2.6 64 53 P2.7 65 54 P3.0 34 25 P3.1 39 28 Pin PLCC68 SQUARE VQFP64 1.4 P3.2 40 29 P3.3 41 30 P3.4 42 31 P3.5 43 32 P3.6 45 34 P3.7 47 36 RESET 30 21 ALE/PROG 68 56

4188F–8051–01/08 AT/TS8xC51Rx2 PSEN 67 55 EA /VPP 2 58 XTAL1 49 38 XTAL2 48 37 P4.0 20 11 P4.1 24 15 P4.2 26 17 P4.3 44 33 P4.4 46 35 P4.5 50 39 P4.6 53 42 P4.7 57 46 P5.0 60 49 P5.1 62 51 P5.2 63 52 P5.3 7 62 P5.4 8 63 P5.5 10 1 P5.6 13 4 P5.7 16 7

4188F–8051–01/08 AT/TS8xC51Rx2

5.2 TS80C51Rx2 Enhanced Features

In comparison to the original 80C52, the TS8xC51Rx2 implements some new features, which are :

• The X2 option.
• The Dual Data Pointer.
• The extended RAM.
• The Programmable Counter Array (PCA).
• The Watchdog.
• The 4 level interrupt priority system.
• The power-off flag.
• The ONCE mode.
• The ALE disabling.
• Some enhanced features are also located in the UAR T and the timer 2.

5.3 X2 Feature

The TS80C51Rx2 core needs only 6 clock periods per machine cycle. This feature called ”X2” provides the following advantages:

• Divides frequency crystals by 2 (cheaper crystals) while keeping same CPU power.
• Saves power consumption while keeping same CPU pow er (oscillator power saving).
• Saves power consumption by dividing dynamically operating frequency by 2 in operating and idle modes.
• Increases CPU power by 2 while keeping same crysta l frequency. In order to keep the original C51 compatibility, a divider by 2 is inserted between the XTAL1 sig- nal and the main clock input of the core (phase gen erator). This divider may be disabled by software.

5.3.1 Description

The clock for the whole circuit and peripheral is f irst divided by two before being used by the CPU core and peripherals. This allows any cyclic ra tio to be accepted on XTAL1 input. In X2 mode, as this divider is bypassed, the signals on X TAL1 must have a cyclic ratio between 40 to 60%. Figure 5-1 shows the clock generation block diagram. X2 bit i s validated on XTAL1 ÷ 2 ris- ing edge to avoid glitches when switching from X2 t o STD mode. Figure 5-2 shows the mode switching waveforms.

4188F–8051–01/08 AT/TS8xC51Rx2 Reset Value = XXXX XXX0b Not bit addressable For further details on the X2 feature, please refer to ANM072 available on the web (http://www.atmel.com) 4 - Reserved The value read from this bit is indeterminate. Do n ot set this bit. 3 - Reserved The value read from this bit is indeterminate. Do n ot set this bit. 2 - Reserved The value read from this bit is indeterminate. Do n ot set this bit. 1 - Reserved The value read from this bit is indeterminate. Do n ot set this bit. 0 X2 CPU and peripheral clock bit Clear to select 12 clock periods per machine cycle (STD mode, F OSC =F XTAL /2). Set to select 6 clock periods per machine cycle (X2 mode, F OSC =F XTAL ). Bit Number Bit Mnemonic Description

4188F–8051–01/08 AT/TS8xC51Rx2

5.4 Dual Data Pointer Register

The additional data pointer can be used to speed up code execution and reduce code size in a number of ways. The dual DPTR structure is a way by which the chip will specify the address of an external data memory location. There are two 16-bit DPTR register s that address the external memory, and a single bit called DPS = AUXR1/bit0 ( Table 5-3 ) that allows the program code to switch between them (Refer to Figure 5-3). Figure 5-3. Use of Dual Pointer Table 5-3. AUXR1: Auxiliary Register 1 External Data Memory AUXR1(A2H) DPS DPH(83H) DPL(82H) DPTR0 DPTR1 AUXR1 Address 0A2H - - - - GF3 - - DPS Reset value X X X X 0 X X 0 Symbol Function - Not implemented, reserved for future use (1) 1. User software should not write 1s to reserved bit s. These bits may be used in future 8051 family products to invoke new feature. In that case, the reset value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate. GF3 will not be available on first version of the RC devices. DPS Data Pointer Selection. DPS Operating Mode

0 DPTR0 Selected

1 DPTR1 Selected

GF3 This bit is a general purpose user flag (2) .

4188F–8051–01/08 AT/TS8xC51Rx2 6. Application Software can take advantage of the additional data pointers to both increase speed and reduce code size, for example, block operations (copy, com pare, search ...) are well served by using one data pointer as a ’source’ pointer and the other one as a "destination" pointer. ASSEMBLY LANGUAGE ; Block move using dual data pointers ; Destroys DPTR0, DPTR1, A and PSW ; note: DPS exits opposite of entry state ; unless an extra INC AUXR1 is added 00A2 AUXR1 EQU 0A2H 0000 909000MOV DPTR,#SOURCE ; address of SOURCE 0003 05A2 INC AUXR1 ; switch data pointers 0005 90A000 MOV DPTR,#DEST ; address of DEST

0008 LOOP:

0008 05A2 INC AUXR1 ; switch data pointers 000A E0 MOVX A,@DPTR ; get a byte from SOURCE 000B A3 INC DPTR ; increment SOURCE address 000C 05A2 INC AUXR1 ; switch data pointers 000E F0 MOVX @DPTR,A ; write the byte to DEST 000F A3 INC DPTR ; increment DEST address 0010 70F6JNZ LOOP ; check for 0 terminator 0012 05A2 INC AUXR1 ; (optional) restore DPS INC is a short (2 bytes) and fast (12 clocks) way t o manipulate the DPS bit in the AUXR1 SFR. However, note that the INC instruction does not dir ectly force the DPS bit to a particular state, but simply toggles it. In simple routines, such as the block move example, only the fact that DPS is toggled in the proper sequence matters, not its actual value. In other words, the block move routine works the same whether DPS is '0' or '1' on entry. Observe that without the last instruc- tion (INC AUXR1), the routine will exit with DPS in the opposite state.

4188F–8051–01/08 AT/TS8xC51Rx2

6.1 Expanded RAM (XRAM)

The TS80C51Rx2 provide additional Bytes of ramdom a ccess memory (RAM) space for increased data parameter handling and high level language usage. RA2, RB2 and RC2 devices have 256 bytes of expanded RAM, from 00H to FFH in external data space; RD2 devices have 768 bytes of expanded RAM, from 00H to 2FFH in external data space. The TS80C51Rx2 has internal data memory that is mapped into four separate segments. The four segments are:

• 1. The Lower 128 bytes of RAM (addresses 00H to 7F H) are directly and indirectly addressable.
• 2. The Upper 128 bytes of RAM (addresses 80H to FF H) are indirectly addressable only.
• 3. The Special Function Registers, SFRs, (addresse s 80H to FFH) are directly addressable only.
• 4. The expanded RAM bytes are indirectly accessed by MOVX instructions, and with the EXTRAM bit cleared in the AUXR register. (See Table 6-1.) The Lower 128 bytes can be accessed by either direc t or indirect addressing. The Upper 128 bytes can be accessed by indirect addressing only. The Upper 128 bytes occupy the same address space as the SFR. That means they have the same address, but are physically sepa- rate from SFR space. When an instruction accesses an internal location a bove address 7FH, the CPU knows whether the access is to the upper 128 bytes of data RAM or to SFR space by the addressing mode used in the instruction.
• Instructions that use direct addressing access SFR space. For example: MOV 0A0H, # data , accesses the SFR at location 0A0H (which is P2).
• Instructions that use indirect addressing access t he Upper 128 bytes of data RAM. For example: MOV @R0, # data where R0 contains 0A0H, accesses the data byte at address 0A0H, rather than P2 (whose address is 0A0H).
• The 256 or 768 XRAM bytes can be accessed by indir ect addressing, with EXTRAM bit cleared and MOVX instructions. This part of memory which is physically located on-chip, logically occupies the first 256 or 768 bytes of external data memory.
• With EXTRAM = 0, the XRAM is indirectly addressed, using the MOVX instruction in combination with any of the registers R0, R1 of the selected bank or DPTR. An access to XRAM will not affect ports P0, P2, P3.6 (WR ) and P3.7 (RD ). For example, with EXTRAM = 0, MOVX @R0, # data where R0 contains 0A0H, accesses the XRAM at address 0A0H rather than external memory. An access to external data memory locations higher than FFH (i.e. 0100H to FFFFH) (higher than 2FFH (i.e. 0300H to FFFFH for RD devices) will be performed with the MOVX DPTR instructions in the same way as in the standard 80C51, so with P0 and P2 as data/address busses, and P3.6 and P3.7 as write and read timing signals. Refer to Figure 6-1. For RD devices, accesses to expanded RAM from 100H to 2FFH can only be done thanks to the use of DPTR.
• With EXTRAM = 1 , MOVX @Ri and MOVX @DPTR will be similar to the standard 80C51. MOVX @ Ri will provide an eight-bit address multiplexed with data on Port0 and any output port pins can be used to output higher order address bits. This is to provide the external paging capability. MOVX @DPTR will generate a sixteen-bit address. Port2 outputs the high- order eight address bits (the contents of DPH) while Port0 multiplexes the low-order eight

4188F–8051–01/08 AT/TS8xC51Rx2 address bits (DPL) with data. MOVX @ Ri and MOVX @DPTR will generate either read or write signals on P3.6 (WR ) and P3.7 (RD ). The stack pointer (SP) may be located anywhere in t he 256 bytes RAM (lower and upper RAM) internal data memory. The stack may not be located in the XRAM. Figure 6-1. Internal and External Data Memory Address Table 6-1. Auxiliary Register AUXR XRAM 256 bytes Upper 128 bytes Internal Ram Lower 128 bytes Internal Ram Special Function Register 80 80 FF(RA, RB, RC)/2FF (RD) FF FF External Data Memory 0000 0100 (RA, RB, RC) or 0300 (RD) FFFF indirect accesses direct accesses direct or indirect accesses AUXR Address 08EH - - - - - - EXTRAM AO Reset value X X X X X X 0 0 Symbol Function - Not implemented, reserved for future use. (1) 1. User software should not write 1s to reserved bit s. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate. AO Disable/Enable ALE AO Operating Mode

0 ALE is emitted at a constant rate of 1/6 the oscill ator frequency (or 1/3 if X2 mode

is used)

1 ALE is active only during a MOVX or MOVC instructi on

EXTRAM Internal/External RAM (00H-FFH) access using MOVX @ Ri/ @ DPTR EXTRAM Operating Mode

0 Internal XRAM access using MOVX @ Ri/ @ DPTR

1 External data memory access

4188F–8051–01/08 AT/TS8xC51Rx2

6.2 Timer 2

The timer 2 in the TS80C51RX2 is compatible with the timer 2 in the 80C52. It is a 16-bit timer/counter: the count is maintained by two eight-bit timer registers, TH2 and TL2, connected in cascade. It is controlled by T2CON reg ister (See Table 6-2) and T2MOD register (See Table 6-3). Timer 2 operation is similar to Timer 0 and Timer 1. C/T2 selects F OSC /12 (timer operation) or external pin T2 (counter operation) as the timer clock input. Setting TR2 allows TL2 to be incremented by the selected input. Timer 2 has 3 operating modes: capture, autoreload and Baud Rate Generator. These modes are selected by the combination of RCLK, TCLK and C P/RL2 (T2CON), as described in the Atmel 8-bit Microcontroller Hardware description. Refer to the Atmel 8-bit Microcontroller Hardware d escription for the description of Capture and Baud Rate Generator Modes. In TS80C51RX2 Timer 2 includes the following enhancements:

• Auto-reload mode with up or down counter
• Programmable clock-output

6.2.1 Auto-reload Mode

The auto-reload mode configures timer 2 as a 16-bit timer or event counter with automatic reload. If DCEN bit in T2MOD is cleared, timer 2 be haves as in 80C52 (refer to the Atmel 8-bit Microcontroller Hardware description). If DCEN bit is set, timer 2 acts as an Up/down timer/counter as shown in Figure 6-2. In this mode the T2EX pin controls the direction of count. When T2EX is high, timer 2 counts up. Timer overflo w occurs at FFFFh which sets the TF2 flag and generates an interrupt request. The overflow al so causes the 16-bit value in RCAP2H and RCAP2L registers to be loaded into the timer registers TH2 and TL2. When T2EX is low, timer 2 counts down. Timer underf low occurs when the count in the timer registers TH2 and TL2 equals the value stored in RC AP2H and RCAP2L registers. The under- flow sets TF2 flag and reloads FFFFh into the timer registers. The EXF2 bit toggles when timer 2 overflows or unde rflows according to the the direction of the count. EXF2 does not generate any interrupt. This bit can be used to provide 17-bit resolution.

4188F–8051–01/08 AT/TS8xC51Rx2 Figure 6-2. Auto-reload Mode Up/Down Counter (DCEN = 1)

6.2.2 Programmable Clock-Output

In the clock-out mode, timer 2 operates as a 50%-du ty-cycle, programmable clock generator (See Figure 6-3) . The input clock increments TL2 at frequency F OSC /2. The timer repeatedly counts to overflow from a loaded value. At overflow , the contents of RCAP2H and RCAP2L reg- isters are loaded into TH2 and TL2. In this mode, t imer 2 overflows do not generate interrupts. The formula gives the clock-out frequency as a func tion of the system oscillator frequency and the value in the RCAP2H and RCAP2L registers: For a 16 MHz system clock, timer 2 has a programmable frequency range of 61 Hz OSC /2 16) to 4 MHz (F OSC /4). The generated clock signal is brought out to T2 pin (P1.0). Timer 2 is programmed for the clock-out mode as follows:

• Set T2OE bit in T2MOD register.
• Clear C/T2 bit in T2CON register.
• Determine the 16-bit reload value from the formula and enter it in RCAP2H/RCAP2L registers.
• Enter a 16-bit initial value in timer registers TH 2/TL2. It can be the same as the reload value or a different one depending on the application.
• To start the timer, set TR2 run control bit in T2CON register. (DOWN COUNTING RELOAD VALUE) C/T2 TF2 TR2 EXF2 TH2 (8-bit) TL2 (8-bit) RCAP2H (8-bit) RCAP2L (8-bit) FFh (8-bit) FFh (8-bit) TOGGLE (UP COUNTING RELOAD VALUE) TIMER 2 INTERRUPT XTAL1 :12 FOSC FXTAL T2CONreg T2CONreg T2CONreg T2CONreg T2EX: if DCEN=1, 1=UP if DCEN=1, 0=DOWN if DCEN = 0, up counting (:6 in X2 mode) Cl o c k O u t F re qu e nc y – Fos c

4188F–8051–01/08 AT/TS8xC51Rx2 It is possible to use timer 2 as a baud rate genera tor and a clock generator simultaneously. For this configuration, the baud rates and clock freque ncies are not independent since both func- tions use the values in the RCAP2H and RCAP2L registers. Figure 6-3. Clock-Out Mode C/T2 = 0 Table 6-2. T2CON Register T2CON - Timer 2 Control Register (C8h) EXF2 TR2 OVERFLOW T2EX TH2 (8-bit) TL2 (8-bit) TIMER 2 RCAP2H (8-bit) RCAP2L (8-bit) T2OE XTAL1 T2CON reg T2CON reg T2CON reg T2MOD reg INTERRUPT Q D Toggle EXEN2 (:1 in X2 mode) 7 6 5 4 3 2 1 0 TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2# CP/RL2#

4188F–8051–01/08 AT/TS8xC51Rx2 Reset Value = 0000 0000b Bit addressable Table 6-3. T2MOD Register T2MOD - Timer 2 Mode Control Register (C9h) Bit Number Bit Mnemonic Description

7 TF2

Must be cleared by software. Set by hardware on timer 2 overflow, if RCLK = 0 an d TCLK = 0.

6 EXF2

Set when a capture or a reload is caused by a negative transition on T2EX pin if EXEN2=1. When set, causes the CPU to vector to timer 2 interrupt routine when timer 2 interrupt is enabled. Must be cleared by software. EXF2 doesn’t cause an interrupt in Up/down counter mode (DCEN = 1)

5 RCLK

Clear to use timer 1 overflow as receive clock for serial port in mode 1 or 3. Set to use timer 2 overflow as receive clock for se rial port in mode 1 or 3.

4 TCLK

Clear to use timer 1 overflow as transmit clock for serial port in mode 1 or 3. Set to use timer 2 overflow as transmit clock for s erial port in mode 1 or 3.

3 EXEN2

Timer 2 External Enable bit Clear to ignore events on T2EX pin for timer 2 oper ation. Set to cause a capture or reload when a negative transition on T2EX pin is detected, if timer 2 is not used to clock the serial port.

2 TR2

Clear to turn off timer 2. Set to turn on timer 2.

1 C/T2#

Timer/Counter 2 select bit Clear for timer operation (input from internal cloc k system: F OSC ). Set for counter operation (input from T2 input pin, falling edge trigger). Must be 0 for clock out mode.

0 CP/RL2#

Timer 2 Capture/Reload bit If RCLK=1 or TCLK=1, CP/RL2# is ignored and timer is forced to auto-reload on timer 2 overflow. Clear to auto-reload on timer 2 overflows or negati ve transitions on T2EX pin if EXEN2=1. Set to capture on negative transitions on T2EX pin if EXEN2=1. 7 6 5 4 3 2 1 0 - - - - - - T2OE DCEN

4188F–8051–01/08 AT/TS8xC51Rx2 Reset Value = XXXX XX00b Not bit addressable Bit Number Bit Mnemonic Description 7 - Reserved The value read from this bit is indeterminate. Do n ot set this bit. 6 - Reserved The value read from this bit is indeterminate. Do n ot set this bit. 5 - Reserved The value read from this bit is indeterminate. Do n ot set this bit. 4 - Reserved The value read from this bit is indeterminate. Do n ot set this bit. 3 - Reserved The value read from this bit is indeterminate. Do n ot set this bit. 2 - Reserved The value read from this bit is indeterminate. Do n ot set this bit.

1 T2OE

Clear to program P1.0/T2 as clock input or I/O port . Set to program P1.0/T2 as clock output.

0 DCEN

Clear to disable timer 2 as up/down counter. Set to enable timer 2 as up/down counter.

4188F–8051–01/08 AT/TS8xC51Rx2

6.3 Programmable Counter Array PCA

The PCA provides more timing capabilities with less CPU intervention than the standard timer/counters. Its advantages include reduced soft ware overhead and improved accuracy. The PCA consists of a dedicated timer/counter which ser ves as the time base for an array of five compare/capture modules. Its clock input can be pro grammed to count any one of the following signals:

• Oscillator frequency ÷ 12 ( ÷ 6 in X2 mode)
• Oscillator frequency ÷ 4 ( ÷ 2 in X2 mode)
• Timer 0 overflow
• External input on ECI (P1.2) Each compare/capture modules can be programmed in a ny one of the following modes:
• rising and/or falling edge capture,
• software timer,
• high-speed output, or
• pulse width modulator. Module 4 can also be programmed as a watchdog timer (See Section "PCA Watchdog Timer", page 33). When the compare/capture modules are programmed in the capture mode, software timer, or high speed output mode, an interrupt can be generat ed when the module executes its function. All five modules plus the PCA timer overflow share one interrupt vector. The PCA timer/counter and compare/capture modules s hare Port 1 for external I/O. These pins are listed below. If the port is not used for the PCA, it can still be used for standard I/O. The PCA timer is a common time base for all five modules (See Fi gure 6-4). The timer count source is determined from the CPS1 and CPS0 bits in the CMOD SFR (See Table 6-4) and can be programmed to run at:
• 1/12 the oscillator frequency. (Or 1/6 in X2 Mode)
• 1/4 the oscillator frequency. (Or 1/2 in X2 Mode)
• The Timer 0 overflow
• The input on the ECI pin (P1.2) PCA component External I/O Pin 16-bit Counter P1.2 / ECI 16-bit Module 0 P1.3 / CEX0 16-bit Module 1 P1.4 / CEX1 16-bit Module 2 P1.5 / CEX2 16-bit Module 3 P1.6 / CEX3 16-bit Module 4 P1.7 / CEX4

4188F–8051–01/08 AT/TS8xC51Rx2 Figure 6-4. PCA Timer/Counter Table 6-4. CMOD: PCA Counter Mode Register The CMOD SFR includes three additional bits associated with the PCA (See Figure 6-4 and Table 6-4). CIDL CPS1 CPS0 ECF It CH CL 16 bit up/down counter To PCA modules Fosc /12 Fosc / 4 T0 OVF P1.2 Idle CMOD 0xD9 WDTE CF CR CCON 0xD8 CCF4 CCF3 CCF2 CCF1 CCF0 overflow CMOD Address 0D9H CIDL WDTE - - - CPS1 CPS0 ECF Reset value 0 0 X X X 0 0 0 Symbol Function CIDL Counter Idle control: CIDL = 0 programs the PCA Cou nter to continue functioning during idle Mode. CIDL = 1 programs it to be gated off during idle. WDTE Watchdog Timer Enable: WDTE = 0 disables Watchdog Timer function on PCA Module 4. WDTE = 1 enables it. - Not implemented, reserved for future use. (1) 1. User software should not write 1s to reserved bit s. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate. CPS1 PCA Count Pulse Select bit 1. CPS0 PCA Count Pulse Select bit 0. CPS1 CPS0 Selected PCA input. (2) 2. f osc = oscillator frequency 0 0 Internal clock f osc /12 ( Or f osc /6 in X2 Mode). 0 1 Internal clock f osc /4 ( Or f osc /2 in X2 Mode). 1 0 Timer 0 Overflow 1 1 External clock at ECI/P1.2 pin (max rate = f osc / 8) ECF PCA Enable Counter Overflow interrupt: ECF = 1 enab les CF bit in CCON to generate an interrupt. ECF = 0 disables that function of CF.

4188F–8051–01/08 AT/TS8xC51Rx2

• The CIDL bit which allows the PCA to stop during i dle mode.
• The WDTE bit which enables or disables the watchdo g function on module 4.
• The ECF bit which when set causes an interrupt and the PCA overflow flag CF (in the CCON SFR) to be set when the PCA timer overflows. The CCON SFR contains the run control bit for the PCA and the f lags for the PCA timer (CF) and each module (Refer to Table 6-5).
• Bit CR (CCON.6) must be set by software to run the PCA. The PCA is shut off by clearing this bit.
• Bit CF: The CF bit (CCON.7) is set when the PCA co unter overflows and an interrupt will be generated if the ECF bit in the CMOD register is set. The CF bit can only be cleared by software.
• Bits 0 through 4 are the flags for the modules (bit 0 for module 0, bit 1 for module 1, etc.) and are set by hardware when either a match or a capture occurs. These flags also can only be cleared by software. Table 6-5. CCON: PCA Counter Control Register The watchdog timer function is implemented in module 4 (See Figure 6-7). The PCA interrupt system is shown in Figure 6-5. CCON Address 0D8H CF CR - CCF4 CCF3 CCF2 CCF1 CCF0 Reset value 0 0 X 0 0 0 0 0 Symbol Function CF PCA Counter Overflow flag. Set by hardware when the counter rolls over. CF flags an interrupt if bit ECF in CMOD is set. CF may be set by either hardware or software but can only be cleared by software. CR PCA Counter Run control bit. Set by software to tur n the PCA counter on. Must be cleared by software to turn the PCA counter off. - Not implemented, reserved for future use. (1) 1. User software should not write 1s to reserved bit s. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate. CCF4 PCA Module 4 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. CCF3 PCA Module 3 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. CCF2 PCA Module 2 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. CCF1 PCA Module 1 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. CCF0 PCA Module 0 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.

4188F–8051–01/08 AT/TS8xC51Rx2 Figure 6-5. PCA Interrupt System PCA Modules: each one of the five compare/capture modules has si x possible functions. It can perform:

• 16-bit Capture, positive-edge triggered,
• 16-bit Capture, negative-edge triggered,
• 16-bit Capture, both positive and negative-edge tr iggered,
• 16-bit Software Timer,
• 16-bit High Speed Output,
• 8-bit Pulse Width Modulator. In addition, module 4 can be used as a Watchdog Timer. Each module in the PCA has a special function regis ter associated with it. These registers are: CCAPM0 for module 0, CCAPM1 for module 1, etc. (See Table 6-6). The registers contain the bits that control the mode that each module will operate in.
• The ECCF bit (CCAPMn.0 where n=0, 1, 2, 3, or 4 de pending on the module) enables the CCF flag in the CCON SFR to generate an interrupt when a match or compare occurs in the associated module.
• PWM (CCAPMn.1) enables the pulse width modulation mode.
• The TOG bit (CCAPMn.2) when set causes the CEX out put associated with the module to toggle when there is a match between the PCA counter and the module's capture/compare register.
• The match bit MAT (CCAPMn.3) when set will cause the CCFn bit in the CCON register to be set when there is a match between the PCA counter and the module's capture/compare register.
• The next two bits CAPN (CCAPMn.4) and CAPP (CCAPMn .5) determine the edge that a capture input will be active on. The CAPN bit enables the negative edge, and the CAPP bit enables the positive edge. If both bits are set both edges will be enabled and a capture will occur for either transition. CF CR CCON 0xD8 CCF4 CCF3 CCF2 CCF1 CCF0 Module 4 Module 3 Module 2 Module 1 Module 0 ECF PCA Timer/Counter ECCFn CCAPMn.0 CMOD.0 IE.6 IE.7 To Interrupt priority decoder EC EA

4188F–8051–01/08 AT/TS8xC51Rx2

• The last bit in the register ECOM (CCAPMn.6) when set enables the comparator function. Table 6-7 shows the CCAPMn settings for the various PCA functions. Table 6-6. CCAPMn: PCA Modules Compare/Capture Control Registe rs Table 6-7. PCA Module Modes (CCAPMn Registers) CCAPMn Address n = 0 - 4 CCAPM0=0DAH CCAPM1=0DBH CCAPM2=0DCH CCAPM3=0DDH CCAPM4=0DEH - ECOMn CAPPn CAPNn MATn TOGn PWMm ECCFn Reset value X 0 0 0 0 0 0 0 Symbol Function - Not implemented, reserved for future use. (1) 1. User software should not write 1s to reserved bit s. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate. ECOMn Enable Comparator. ECOMn = 1 enables the compa rator function. CAPPn Capture Positive, CAPPn = 1 enables positive e dge capture. CAPNn Capture Negative, CAPNn = 1 enables negative e dge capture. MATn Match. When MATn = 1, a match of the PCA counter wi th this module's compare/capture register causes the CCFn bit in CCON to be set, flagging an interrupt. TOGn Toggle. When TOGn = 1, a match of the PCA counter w ith this module's compare/capture register causes the CEXn pin to toggle. PWMn Pulse Width Modulation Mode. PWMn = 1 enables the C EXn pin to be used as a pulse width modulated output. ECCFn Enable CCF interrupt. Enables compare/capture flag CCFn in the CCON register to generate an interrupt. ECOMn CAPPn CAPNn MATn TOGn PWMm ECCFn Module Function 0 0 0 0 0 0 0 No Operation X 1 0 0 0 0 X 16-bit capture by a positive-edge trigger on CEXn X 0 1 0 0 0 X 16-bit capture by a negative trigger on CEXn X 1 1 0 0 0 X 16-bit capture by a transition on CEXn 1 0 0 1 0 0 X 16-bit Software Timer / Compare mode. 1 0 0 1 1 0 X 16-bit High Speed Output 1 0 0 0 0 1 0 8-bit PWM 1 0 0 1 X 0 X Watchdog Timer (module 4 only)

4188F–8051–01/08 AT/TS8xC51Rx2 There are two additional registers associated with each of the PCA modules. They are CCAPnH and CCAPnL and these are the registers that store t he 16-bit count when a capture occurs or a compare should occur. When a module is used in the PWM mode these registers are used to control the duty cycle of the output (See Table 6-8 & Table 6-9) Table 6-8. CCAPnH: PCA Modules Capture/Compare Registers High Table 6-9. CCAPnL: PCA Modules Capture/Compare Registers Low Table 6-10. CH: PCA Counter High Table 6-11. CL: PCA Counter Low

6.3.1 PCA Capture Mode

To use one of the PCA modules in the capture mode e ither one or both of the CCAPM bits CAPN and CAPP for that module must be set. The external CEX input for the module (on port 1) is sampled for a transition. When a valid transitio n occurs the PCA hardware loads the value of the PCA counter registers (CH and CL) into the modu le's capture registers (CCAPnL and CCAPnH). If the CCFn bit for the module in the CCON SFR and the ECCFn bit in the CCAPMn SFR are set then an interrupt will be generated (Refer to Figure 6-6). CCAPnH Address n = 0 - 4 CCAP0H=0FAH CCAP1H=0FBH CCAP2H=0FCH CCAP3H=0FDH CCAP4H=0FEH 7 6 5 4 3 2 1 0 Reset value 0 0 0 0 0 0 0 0 CCAPnL Address n = 0 - 4 CCAP0L=0EAH CCAP1L=0EBH CCAP2L=0ECH CCAP3L=0EDH CCAP4L=0EEH 7 6 5 4 3 2 1 0 Reset value 0 0 0 0 0 0 0 0 CH Address 0F9H 7 6 5 4 3 2 1 0 Reset value 0 0 0 0 0 0 0 0 CL Address 0E9H 7 6 5 4 3 2 1 0 Reset value 0 0 0 0 0 0 0 0

4188F–8051–01/08 AT/TS8xC51Rx2 Figure 6-6. PCA Capture Mode 6.3.2 16-bit Software Timer/ Compare Mode The PCA modules can be used as software timers by s etting both the ECOM and MAT bits in the modules CCAPMn register. The PCA timer will be compared to the module's capture regis- ters and when a match occurs an interrupt will occu r if the CCFn (CCON SFR) and the ECCFn (CCAPMn SFR) bits for the module are both set (See Figure 6-7). CF CR CCON 0xD8 CH CL CCAPnH CCAPnL CCF4 CCF3 CCF2 CCF1 CCF0 PCA IT PCA Counter/Timer ECOMn CCAPMn, n= 0 to 4 0xDA to 0xDE CAPNn MATn TOGn PWMn ECCFn CAPPn Cex.n Capture

4188F–8051–01/08 AT/TS8xC51Rx2 Figure 6-7. PCA Compare Mode and PCA Watchdog Timer Before enabling ECOM bit, CCAPnL and CCAPnH should be set with a non zero value, other- wise an unwanted match could happen. Writing to CCAPnH will set the ECOM bit. Once ECOM set, writing CCAPnL will clear ECOM so th at an unwanted match doesn’t occur while modifying the compare value. Writing to CCAPn H will set ECOM. For this reason, user software should write CCAPnL first, and then CCAPnH . Of course, the ECOM bit can still be controlled by accessing to CCAPMn register.

6.3.3 High Speed Output Mode

In this mode the CEX output (on port 1) associated with the PCA module will toggle each time a match occurs between the PCA counter and the module 's capture registers. To activate this mode the TOG, MAT, and ECOM bits in the module's CCAPMn SFR must be set (See Figure 6- 8). A prior write must be done to CCAPnL and CCAPnH before writing the ECOMn bit. CH CL CCAPnH CCAPnL ECOMn CCAPMn, n = 0 to 4 0xDA to 0xDE CAPNn MATn TOGn PWMn ECCFn CAPPn 16 bit comparator Match CCON 0xD8 PCA IT Enable PCA counter/timer RESET * CIDL CPS1 CPS0 ECF CMOD 0xD9 WDTE * Only for Module 4 Reset Write to CCAPnL Write to CCAPnH CF CCF2 CCF1 CCF0 CR CCF3 CCF4 1 0

4188F–8051–01/08 AT/TS8xC51Rx2 Figure 6-8. PCA High Speed Output Mode Before enabling ECOM bit, CCAPnL and CCAPnH should be set with a non zero value, other- wise an unwanted match could happen. Once ECOM set, writing CCAPnL will clear ECOM so th at an unwanted match doesn’t occur while modifying the compare value. Writing to CCAPn H will set ECOM. For this reason, user software should write CCAPnL first, and then CCAPnH . Of course, the ECOM bit can still be controlled by accessing to CCAPMn register.

6.3.4 Pulse Width Modulator Mode

All of the PCA modules can be used as PWM outputs. Figure 6-9 shows the PWM function. The frequency of the output depends on the source for t he PCA timer. All of the modules will have the same frequency of output because they all share the PCA timer. The duty cycle of each module is independently variable using the module's capture register CCAPLn. When the value of the PCA CL SFR is less than the value in the mod ule's CCAPLn SFR the output will be low, when it is equal to or greater than the output will be high. When CL overflows from FF to 00, CCAPLn is reloaded with the value in CCAPHn. This a llows updating the PWM without glitches. The PWM and ECOM bits in the module's CCAPMn regist er must be set to enable the PWM mode. CH CL CCAPnH CCAPnL ECOMn CCAPMn, n = 0 to 4 0xDA to 0xDE CAPNn MATn TOGn PWMn ECCFn CAPPn 16 bit comparator Match CF CR CCON 0xD8 CCF4 CCF3 CCF2 CCF1 CCF0 PCA IT Enable CEXn PCA counter/timer Write to CCAPnH Reset Write to CCAPnL 1 0

4188F–8051–01/08 AT/TS8xC51Rx2 Figure 6-9. PCA PWM Mode

6.3.5 PCA Watchdog Timer

An on-board watchdog timer is available with the PC A to improve the reliability of the system without increasing chip count. Watchdog timers are useful for systems that are susceptible to noise, power glitches, or electrostatic discharge. Module 4 is the only PCA module that can be programmed as a watchdog. However, this module can still be used for other modes if the watchdog is not needed. Figure 6-7 shows a diagram of how the watchdog works. The user pre- loads a 16-bit value in the compare registers. Just like the other compare modes, this 16-bit value is compared to the PCA timer value. If a match is allowed to occur, an internal reset will be generated. This will not cause the RST pin to be driven high. In order to hold off the reset, the user has three options:

• 1. Periodically change the compare value so it wil l never match the PCA timer,
• 2. periodically change the PCA timer value so it w ill never match the compare values, or
• 3. Disable the watchdog by clearing the WDTE bit b efore a match occurs and then re-enable it. The first two options are more reliable because the watchdog timer is never disabled as in option #3. If the program counter ever goes astray, a matc h will eventually occur and cause an internal reset. The second option is also not recommended if other PCA modules are being used. Remember, the PCA timer is the time base for all mo dules; changing the time base for other modules would not be a good idea. Thus, in most applications the first solution is the best option. This watchdog timer won’t generate a reset out on the reset pin. CL CCAPnH CCAPnL ECOMn CCAPMn, n= 0 to 4 0xDA to 0xDE CAPNn MATn TOGn PWMn ECCFn CAPPn 8 bit comparator CEXn “0” “1” Š <Enable PCA counter/timer Overflow

4188F–8051–01/08 AT/TS8xC51Rx2

6.4 TS80C51Rx2 Serial I/O Port

The serial I/O port in the TS80C51Rx2 is compatible with the serial I/O port in the 80C52. It provides both synchronous and asynchronous commu nication modes. It operates as an Uni- versal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes (Modes 1, 2 and 3). Asynchronous transmission and reception can occur simultaneously and at different baud rates Serial I/O port includes the following enhancements:

• Framing error detection
• Automatic address recognition

6.4.1 Framing Error Detection

Framing bit error detection is provided for the three asynchronous modes (modes 1, 2 and 3). To enable the framing bit error detection feature, set SMOD0 bit in PCON register (See Figure 6- 10). Figure 6-10. Framing Error Block Diagram When this feature is enabled, the receiver checks each incoming data frame for a valid stop bit. An invalid stop bit may result from noise on the serial lines or from simultaneous transmission by two CPUs. If a valid stop bit is not found, the Framing Error bit (FE) in SCON register (See Table 6-14.) bit is set. Software may examine FE bit after each reception to check for data errors. Once set, only soft- ware or a reset can clear FE bit. Subsequently rece ived frames with valid stop bits cannot clear FE bit. When FE feature is enabled, RI rises on stop bit instead of the last data bit (See Figure 6- 11 and Figure 6-12 ). Figure 6-11. UART Timings in Mode 1 RI TI RB8 TB8 REN SM2 SM1 SM0/FE IDL PD GF0 GF1 POF -SMOD0 SMOD1 To UART framing error control SM0 to UART mode control (SMOD = 0) Set FE bit if stop bit is 0 (framing error) (SMOD0 = 1) SCON (98h) PCON (87h) Data byte RI SMOD0=X Stop bit Start bit RXD D7 D6 D5 D4 D3 D2 D1 D0 FE SMOD0=1

4188F–8051–01/08 AT/TS8xC51Rx2 Figure 6-12. UART Timings in Modes 2 and 3

6.4.2 Automatic Address Recognition

The automatic address recognition feature is enable d when the multiprocessor communication feature is enabled (SM2 bit in SCON register is set). Implemented in hardware, automatic address recognit ion enhances the multiprocessor commu- nication feature by allowing the serial port to exa mine the address of each incoming command frame. Only when the serial port recognizes its own address, the receiver sets RI bit in SCON register to generate an interrupt. This ensures tha t the CPU is not interrupted by command frames addressed to other devices. If desired, you may enable the automatic address re cognition feature in mode 1. In this configu- ration, the stop bit takes the place of the ninth d ata bit. Bit RI is set only when the received command frame address matches the device’s address and is terminated by a valid stop bit. To support automatic address recognition, a device is identified by a given address and a broad- cast address. Note: The multiprocessor communication and automatic address recognition features cannot be enabled in mode 0 (i.e. setting SM2 bit in SCON register in mode 0 has no effect).

6.4.3 Given Address

Each device has an individual address that is speci fied in SADDR register; the SADEN register is a mask byte that contains don’t-care bits (defin ed by zeros) to form the device’s given address. The don’t-care bits provide the flexibilit y to address one or more slaves at a time. The following example illustrates how a given address is formed. To address a device by its individual address, the SADEN mask byte must be 1111 1111b . For example: SADDR0101 0110b SADEN 1111 1100b Given0101 01XXb The following is an example of how to use given addresses to address different slaves: Slave A:SADDR1111 0001b SADEN 1111 1010b Given1111 0X0Xb Slave B:SADDR1111 0011b SADEN 1111 1001b Given1111 0XX1b RI SMOD0=0 Data byte Ninth bit Stop bit Start bit RXD D8 D7 D6 D5 D4 D3 D2 D1 D0 RI SMOD0=1 FE SMOD0=1

4188F–8051–01/08 AT/TS8xC51Rx2 Slave C:SADDR1111 0010b SADEN 1111 1101b Given1111 00X1b The SADEN byte is selected so that each slave may be addressed separately. For slave A, bit 0 (the LSB) is a don’t-care bit; f or slaves B and C, bit 0 is a 1. To communicate with slave A only, the master must send an address where bit 0 is clear (e.g. 1111 0000b ). For slave A, bit 1 is a 1; for slaves B and C, bit 1 is a don’t care bit. To communicate with slaves B and C, but not slave A, the master must send an address with bits 0 and 1 both set (e.g. 1111 0011b ). To communicate with slaves A, B and C, the master must send an address with bit 0 set, bit 1 clear, and bit 2 clear (e.g. 1111 0001b ).

6.4.4 Broadcast Address

A broadcast address is formed from the logical OR o f the SADDR and SADEN registers with zeros defined as don’t-care bits, e.g.: SADDR0101 0110b SADEN1111 1100b Broadcast =SADDR OR SADEN1111 111Xb The use of don’t-care bits provides flexibility in defining the broadcast address, however in most applications, a broadcast address is FFh. The follo wing is an example of using broadcast addresses: Slave A:SADDR1111 0001b SADEN 1111 1010b Broadcast1111 1X11b, Slave B:SADDR1111 0011b SADEN 1111 1001b Broadcast1111 1X11B, Slave C:SADDR=1111 0010b SADEN 1111 1101b Broadcast1111 1111b For slaves A and B, bit 2 is a don’t care bit; for slave C, bit 2 is set. To communicate with all of the slaves, the master must send an address FFh. To communicate with slaves A and B, but not slave C, the master can send and address FBh.

6.4.5 Reset Addresses

On reset, the SADDR and SADEN registers are initial ized to 00h, i.e. the given and broadcast addresses are XXXX XXXXb (all don’t-care bits). This ensures that the serial port will reply to any address, and so, that it is backwards compatible wi th the 80C51 microcontrollers that do not support automatic address recognition.

4188F–8051–01/08 AT/TS8xC51Rx2 Table 6-12. SADEN - Slave Address Mask Register (B9h) Reset Value = 0000 0000b Not bit addressable Table 6-13. SADDR - Slave Address Register (A9h) Reset Value = 0000 0000b Not bit addressable Table 6-14. SCON Register SCON - Serial Control Register (98h) 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 FE/SM0 SM1 SM2 REN TB8 RB8 TI RI

4188F–8051–01/08 AT/TS8xC51Rx2 Reset Value = 0000 0000b Bit addressable Table 6-15. PCON Register PCON - Power Control Register (87h) Bit Number Bit Mnemonic Description 7 FE Framing Error bit (SMOD0=1 ) Clear to reset the error state, not cleared by a va lid stop bit. Set by hardware when an invalid stop bit is detecte d. SMOD0 must be set to enable access to the FE bit SM0 Serial port Mode bit 0 Refer to SM1 for serial port mode selection. SMOD0 must be cleared to enable access to the SM0 b it

6 SM1

SM1 Mode DescriptionBaud Rate 0 0 0Shift RegisterF XTAL /12 (/6 in X2 mode) 0 1 18-bit UARTVariable 1 0 29-bit UARTF XTAL /64 or F XTAL /32 (/32, /16 in X2 mode) 1 1 39-bit UARTVariable

5 SM2

Serial port Mode 2 bit / Multiprocessor Communicati on Enable bit Clear to disable multiprocessor communication featu re. Set to enable multiprocessor communication feature in mode 2 and 3, and eventually mode 1. This bit should be cleared in mode 0.

4 REN

Clear to disable serial reception. Set to enable serial reception.

3 TB8

Transmitter Bit 8 / Ninth bit to transmit in modes 2 and 3 Clear to transmit a logic 0 in the 9th bit. Set to transmit a logic 1 in the 9th bit.

2 RB8

Receiver Bit 8 / Ninth bit received in modes 2 and 3 Cleared by hardware if 9th bit received is a logic 0. Set by hardware if 9th bit received is a logic 1. In mode 1, if SM2 = 0, RB8 is the received stop bit . In mode 0 RB8 is not used. 1 TI Transmit Interrupt flag Clear to acknowledge interrupt. Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the stop bit in the other modes. 0 RI Receive Interrupt flag Clear to acknowledge interrupt. Set by hardware at the end of the 8th bit time in mode 0, see Figure 6-11. and Figure 6- 12. in the other modes. 7 6 5 4 3 2 1 0 SMOD1 SMOD0 - POF GF1 GF0 PD IDL

4188F–8051–01/08 AT/TS8xC51Rx2 Reset Value = 00X1 0000b Not bit addressable Power-off flag reset value will be 1 only after a power on (cold reset). A warm reset doesn’t affect the value of this bit. Bit Number Bit Mnemonic Description

7 SMOD1 Serial port Mode bit 1

Set to select double baud rate in mode 1, 2 or 3.

6 SMOD0

Clear to select SM0 bit in SCON register. Set to to select FE bit in SCON register. 5 - Reserved The value read from this bit is indeterminate. Do n ot set this bit.

4 POF

Clear to recognize next reset type. Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set by software.

3 GF1

Cleared by user for general purpose usage. Set by user for general purpose usage.

2 GF0

Cleared by user for general purpose usage. Set by user for general purpose usage. 1 PD Power-Down mode bit Cleared by hardware when reset occurs. Set to enter power-down mode.

0 IDL

Clear by hardware when interrupt or reset occurs. Set to enter idle mode.

4188F–8051–01/08 AT/TS8xC51Rx2

6.5 Interrupt System

The TS80C51Rx2 has a total of 7 interrupt vectors: two external interrupts (INT0 and INT1 ), three timer interrupts (timers 0, 1 and 2), the ser ial port interrupt and the PCA global interrupt. These interrupts are shown in Figure 6-13. WARNING: Note that in the first version of RC devices, the PCA interrupt is in the lowest priority. Thus the order in INT0 , TF0, INT1 , TF1, RI or TI, TF2 or EXF2, PCA. Figure 6-13. Interrupt Control System Each of the interrupt sources can be individually e nabled or disabled by setting or clearing a bit in the Interrupt Enable register (See Table 6-17.Table 6-18.). This register also contains a global disable bit, which must be cleared to disable all interrupts at once. Each interrupt source can also be individually prog rammed to one out of four priority levels by setting or clearing a bit in the Interrupt Priority register (See Table 6-18.) and in the Interrupt Pri- ority High register (See Table 6-19.). shows the b it values and priority levels associated with each combination. The PCA interrupt vector is located at address 0033 H. All other vector addresses are the same as standard C52 devices. IE1 High priority interrupt Interrupt polling sequence, decreasing from high to low priority Low priority interrupt Global Disable Individual Enable EXF2 TF2 TI RI TF0 INT0 INT1 TF1 IPH, IP IE0 PCA IT

4188F–8051–01/08 AT/TS8xC51Rx2 Table 6-16. Priority Level Bit Values A low-priority interrupt can be interrupted by a high priority interrupt, but not by another low-prior- ity interrupt. A high-priority interrupt can’t be interrupted by any other interrupt source. If two interrupt requests of different priority lev els are received simultaneously, the request of higher priority level is serviced. If interrupt requests of the same priority level are received simul- taneously, an internal polling sequence determines which request is serviced. Thus within each priority level there is a second priority structure determined by the polling sequence. Table 6-17. IE Register IE - Interrupt Enable Register (A8h) Reset Value = 0000 0000b Bit addressable IPH.x IP.x Interrupt Level Priority 0 0 0 (Lowest) 0 1 1 1 0 2 1 1 3 (Highest) 7 6 5 4 3 2 1 0 EA EC ET2 ES ET1 EX1 ET0 EX0 Bit Number Bit Mnemonic Description 7 EA Enable All interrupt bit Clear to disable all interrupts. Set to enable all interrupts. If EA=1, each interrupt source is individually enabled or disabled by setting or clearing its own interrupt enable bit.

6 EC PCA interrupt enable bit

Clear to disable . Set to enable.

5 ET2

Timer 2 overflow interrupt Enable bit Clear to disable timer 2 overflow interrupt. Set to enable timer 2 overflow interrupt. 4 ES Serial port Enable bit Clear to disable serial port interrupt. Set to enable serial port interrupt.

3 ET1

Timer 1 overflow interrupt Enable bit Clear to disable timer 1 overflow interrupt. Set to enable timer 1 overflow interrupt.

2 EX1

External interrupt 1 Enable bit Clear to disable external interrupt 1. Set to enable external interrupt 1.

1 ET0

Timer 0 overflow interrupt Enable bit Clear to disable timer 0 overflow interrupt. Set to enable timer 0 overflow interrupt.

0 EX0

External interrupt 0 Enable bit Clear to disable external interrupt 0. Set to enable external interrupt 0.

4188F–8051–01/08 AT/TS8xC51Rx2 Table 6-18. IP Register IP - Interrupt Priority Register (B8h) Reset Value = X000 0000b Bit addressable 7 6 5 4 3 2 1 0 - PPC PT2 PS PT1 PX1 PT0 PX0 Bit Number Bit Mnemonic Description 7 - Reserved The value read from this bit is indeterminate. Do n ot set this bit.

6 PPC PCA interrupt priority bit

Refer to PPCH for priority level.

5 PT2 Timer 2 overflow interrupt Priority bit

Refer to PT2H for priority level.

4 PS Serial port Priority bit

Refer to PSH for priority level.

3 PT1 Timer 1 overflow interrupt Priority bit

Refer to PT1H for priority level.

2 PX1 External interrupt 1 Priority bit

Refer to PX1H for priority level.

1 PT0 Timer 0 overflow interrupt Priority bit

Refer to PT0H for priority level.

0 PX0 External interrupt 0 Priority bit

Refer to PX0H for priority level.

4188F–8051–01/08 AT/TS8xC51Rx2 Table 6-19. IPH Register IPH - Interrupt Priority High Register (B7h) Reset Value = X000 0000b Not bit addressable 7 6 5 4 3 2 1 0 - PPCH PT2H PSH PT1H PX1H PT0H PX0H Bit Number Bit Mnemonic Description 7 - Reserved The value read from this bit is indeterminate. Do n ot set this bit.

6 PPCH

PCA interrupt priority bit high. PPCH PPC Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest

5 PT2H

Timer 2 overflow interrupt Priority High bit PT2H PT2 Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest

4 PSH

Serial port Priority High bit PSH PS Priority Level 0 0Lowest 0 1 1 0 1 1Highest

3 PT1H

Timer 1 overflow interrupt Priority High bit PT1H PT1 Priority Level 0 0Lowest 0 1 1 0 1 1Highest

2 PX1H

External interrupt 1 Priority High bit PX1H PX1 Priority Level 0 0Lowest 0 1 1 0 1 1Highest

1 PT0H

Timer 0 overflow interrupt Priority High bit PT0H PT0 Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest

0 PX0H

External interrupt 0 Priority High bit PX0H PX0 Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest

4188F–8051–01/08 AT/TS8xC51Rx2

6.6 Idle Mode

An instruction that sets PCON.0 causes that to be the last instruction executed before going into the Idle mode. In the Idle mode, the internal clock signal is gated off to the CPU, but not to the interrupt, Timer, and Serial Port functions. The CP U status is preserved in its entirety: the Stack Pointer, Program Counter, Program Status Word, Accu mulator and all other registers maintain their data during Idle. The port pins hold the logi cal states they had at the time Idle was acti- vated. ALE and PSEN hold at logic high levels. There are two ways to terminate the Idle. Activatio n of any enabled interrupt will cause PCON.0 to be cleared by hardware, terminating the Idle mod e. The interrupt will be serviced, and follow- ing RETI the next instruction to be executed will b e the one following the instruction that put the device into idle. The flag bits GF0 and GF1 can be used to give an in dication if an interrupt occured during nor- mal operation or during an Idle. For example, an in struction that activates Idle can also set one or both flag bits. When Idle is terminated by an in terrupt, the interrupt service routine can exam- ine the flag bits. The other way of terminating the Idle mode is with a hardware reset. Since the clock oscillator is still running, the hardware reset needs to be held active for only two machine cycles (24 oscilla- tor periods) to complete the reset.

6.7 Power-down Mode

To save maximum power, a power-down mode can be invoked by software (Refer to Table 6-15 , PCON register). In power-down mode, the oscillator is stopped and t he instruction that invoked power-down mode is the last instruction executed. The internal RAM and SFRs retain their value until the power-down mode is terminated. V CC can be lowered to save further power. Either a har dware reset or an external interrupt can cause an exit fr om power-down. To properly terminate power- down, the reset or external interrupt should not be executed before V CC is restored to its normal operating level and must be held active long enough for the oscillator to restart and stabilize. Only external interrupts INT0 and INT1 are useful to exit from power-down. For that, inte rrupt must be enabled and configured as level or edge sensitive interrupt input. Holding the pin low restarts the oscillator but bringing the pin high completes the exit as detailed in Figure 6-14. When both interrupts are enabled, t he oscillator restarts as soon as one of the two inputs is held low and power down exit will be completed when the first input will be released. In this case the higher priority interrupt service routine is executed. Once the interrupt is serviced, the next instructio n to be executed after RETI will be the one fol- lowing the instruction that put TS80C51Rx2 into power-down mode.

4188F–8051–01/08 AT/TS8xC51Rx2 Figure 6-14. Power-Down Exit Waveform Exit from power-down by reset redefines all the SFR s, exit from power-down by external inter- rupt does no affect the SFRs. Exit from power-down by either reset or external in terrupt does not affect the internal RAM content. Note: If idle mode is activated with power-down mode (IDL and PD bits set), the exit sequence is unchanged, when execution is vectored to interrupt, PD and IDL bits are cleared and idle mode is not entered. Table 6-20. The state of ports during idle and power-down mode * Port 0 can force a "zero" level. A "one" will leave port floating. INT1 INT0 XTAL1 Power-down phase Oscillator restart phase Active phase Active phase Mode Program Memory ALE PSEN PORT0 PORT1 PORT2 PORT3 Idle Internal 1 1 Port Data* Port Data Port Data Port Data Idle External 1 1 Floating Port Data Address Port Data Power-down Internal 0 0 Port Data* Port Data Port Data Por t Data Power-down External 0 0 Floating Port Data Port Data Port Data

4188F–8051–01/08 AT/TS8xC51Rx2

6.8 Hardware Watchdog Timer

The WDT is intended as a recovery method in situati ons where the CPU may be subjected to software upset. The WDT consists of a 14-bit counte r and the WatchDog Timer ReSeT (WDTRST) SFR. The WDT is by default disabled from e xiting reset. To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR location 0A6H. When WDT is enabled, it will increment every machine cycle while the oscillator is running and there is no way to disable the WDT except through reset (either har dware reset or WDT overflow reset). When WDT overflows, it will drive an output RESET HIGH pulse at the RST-pin.

6.8.1 Using the WDT

To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR loca- tion 0A6H. When WDT is enabled, the user needs to s ervice it by writing to 01EH and 0E1H to WDTRST to avoid WDT overflow. The 14-bit counter ov erflows when it reaches 16383 (3FFFH) and this will reset the device. When WDT is enabled, it will increment every machine cycle while the oscillator is running. This means the user must reset the WDT at least every 16383 machine cycle. To reset the WDT the user must write 01EH an d 0E1H to WDTRST. WDTRST is a write only register. The WDT counter cannot be read or written. When WDT overflows, it will generate an output RESET pulse at the RST-pin. The RESET pul se duration is 96 x T OSC , where T OSC = 1/F OSC . To make the best use of the WDT, it should be se rviced in those sections of code that will periodically be executed within the time required to prevent a WDT reset. To have a more powerful WDT, a 2 7 counter has been added to extend the Time-out capa bility, ranking from 16ms to 2s @ F OSC = 12MHz. To manage this feature, refer to WDTPRG r egister description, Table 6-22 (SFR0A7h). Table 6-21. WDTRST Register WDTRST Address (0A6h) Write only, this SFR is used to reset/enable the WDT by writing 01EH then 0E1H in sequence. Table 6-22. WDTPRG Register WDTPRG Address (0A7h) 7 6 5 4 3 2 1 Reset value X X X X X X X 7 6 5 4 3 2 1 0 T4 T3 T2 T1 T0 S2 S1 S0

4188F–8051–01/08 AT/TS8xC51Rx2 Reset value XXXX X000

6.8.2 WDT during Power-down and Idle

In Power-down mode the oscillator stops, which mean s the WDT also stops. While in Power- down mode the user does not need to service the WDT . There are 2 methods of exiting Power- down mode: by a hardware reset or via a level activated external interrupt which is enabled prior to entering Power-down mode. When Power-down is exi ted with hardware reset, servicing the WDT should occur as it normally should whenever the TS80C51Rx2 is reset. Exiting Power- down with an interrupt is significantly different. The interrupt is held low long enough for the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent the WDT from resetting the device while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high. It is suggested that the WDT be reset during the interrupt service routine. To ensure that the WDT does not overflow within a f ew states of exiting of powerdown, it is best to reset the WDT just before entering powerdown. In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting the TS80C51Rx2 while in Idle mode, the user should alwa ys set up a timer that will periodically exit Idle, service the WDT, and re-enter Idle mode. Bit Number Bit Mnemonic Description 7 T4 Reserved Do not try to set or clear this bit. 6 T3 5 T2 4 T1 3 T0

2 S2 WDT Time-out select bit 2

1 S1 WDT Time-out select bit 1

0 S0 WDT Time-out select bit 0

0 0 0(2 14 - 1) machine cycles, 16.3 ms @ 12 MHz 0 0 1(2 15 - 1) machine cycles, 32.7 ms @ 12 MHz 0 1 0(2 16 - 1) machine cycles, 65.5 ms @ 12 MHz 0 1 1(2 17 - 1) machine cycles, 131 ms @ 12 MHz 1 0 0(2 18 - 1) machine cycles, 262 ms @ 12 MHz 1 0 1(2 19 - 1) machine cycles, 542 ms @ 12 MHz 1 1 0(2 20 - 1) machine cycles, 1.05 s @ 12 MHz 1 1 1(2 21 - 1) machine cycles, 2.09 s @ 12 MHz

4188F–8051–01/08 AT/TS8xC51Rx2

6.9 ONCE TM Mode (ON Chip Emulation)

The ONCE mode facilitates testing and debugging of systems using TS8xC51Rx2 without removing the circuit from the board. The ONCE mode is invoked by driving certain pins of the TS80C51Rx2; the following sequence must be exercised:

• Pull ALE low while the device is in reset (RST hig h) and PSEN is high.
• Hold ALE low as RST is deactivated. While the TS80C51Rx2 is in ONCE mode, an emulator or test CPU can be used to drive the cir- cuit Table 26. shows the status of the port pins during ONCE mode. Normal operation is restored when normal reset is applied. Table 6-23. External Pin Status during ONCE Mode ALE PSEN Port 0 Port 1 Port 2 Port 3 XTAL1/2 Weak pull-up Weak pull-up Float Weak pull-up Weak pull- up Weak pull-up Active

4188F–8051–01/08 AT/TS8xC51Rx2 7. Power-Off Flag The power-off flag allows the user to distinguish b etween a “cold start” reset and a “warm start” reset. A cold start reset is the one induced by V CC switch-on. A warm start reset occurs while V CC is still applied to the device and could be generated for example by an exit from power-down. The power-off flag (POF) is located in PCON registe r (See Table 7-1 ). POF is set by hardware when V CC rises from 0 to its nominal voltage. The POF can b e set or cleared by software allow- ing the user to determine the type of reset. The POF value is only relevant with a Vcc range from 4.5V to 5.5V. For lower Vcc value, reading POF bit will return indeterminate value. Table 7-1. PCON Register PCON - Power Control Register (87h) Reset Value = 00X1 0000b Not bit addressable 7 6 5 4 3 2 1 0 SMOD1 SMOD0 - POF GF1 GF0 PD IDL Bit Number Bit Mnemonic Description Set to select double baud rate in mode 1, 2 or 3. Clear to select SM0 bit in SCON register. Set to to select FE bit in SCON register. 5 - Reserved The value read from this bit is indeterminate. Do n ot set this bit. Clear to recognize next reset type. Set by hardware when V CC rises from 0 to its nominal voltage. Can also be set by software. Cleared by user for general purpose usage. Set by user for general purpose usage. Cleared by user for general purpose usage. Set by user for general purpose usage. 1 PD Power-Down mode bit Cleared by hardware when reset occurs. Set to enter power-down mode. Clear by hardware when interrupt or reset occurs. Set to enter idle mode.

4188F–8051–01/08 AT/TS8xC51Rx2

7.1 Reduced EMI Mode

The ALE signal is used to demultiplex address and d ata buses on port 0 when used with exter- nal program or data memory. Nevertheless, during in ternal code execution, ALE signal is still generated. In order to reduce EMI, ALE signal can be disabled by setting AO bit. The AO bit is located in AUXR register at bit locat ion 0. As soon as AO is set, ALE is no longer output but remains active during MOVX and MOVC inst ructions and external fetches. During ALE disabling, ALE pin is weakly pulled high. Table 7-2. AUXR Register AUXR - Auxiliary Register (8Eh) Reset Value = XXXX XX00b Not bit addressable 7 6 5 4 3 2 1 0 - - - - - - EXTRAM AO Bit Number Bit Mnemonic Description 7 - Reserved The value read from this bit is indeterminate. Do n ot set this bit. 6 - Reserved The value read from this bit is indeterminate. Do n ot set this bit. 5 - Reserved The value read from this bit is indeterminate. Do n ot set this bit. 4 - Reserved The value read from this bit is indeterminate. Do n ot set this bit. 3 - Reserved The value read from this bit is indeterminate. Do n ot set this bit. 2 - Reserved The value read from this bit is indeterminate. Do n ot set this bit.

1 EXTRAM EXTRAM bit

See Table 6-1. 0 AO ALE Output bit Clear to restore ALE operation during internal fetc hes. Set to disable ALE operation during internal fetche s.

4188F–8051–01/08 AT/TS8xC51Rx2 8. TS83C51RB2/RC2/RD2 ROM

8.1 ROM Structure

The TS83C51RB2/RC2/RD2 ROM memory is divided in thr ee different arrays:

• the code array:16/32/64 Kbytes.
• the encryption array:64 bytes.
• the signature array:4 bytes.

8.2 ROM Lock System

The program Lock system, when programmed, protects the on-chip program against software piracy. 8.2.1 8.2.1 Encryption Array Within the ROM array are 64 bytes of encryption array that are initially unprogrammed (all FF’s). Every time a byte is addressed during program verif y, 6 address lines are used to select a byte of the encryption array. This byte is then exclusive-NOR’ed (XNOR) with the code byte, creating an encrypted verify byte. The algorithm, with the e ncryption array in the unprogrammed state, will return the code in its original, unmodified form. When using the encryption array, one important fact or needs to be considered. If a byte has the value FFh, verifying the byte will produce the encr yption byte value. If a large block (>64 bytes) of code is left unprogrammed, a verification routin e will display the content of the encryption array. For this reason all the unused code bytes sh ould be programmed with random values. This will ensure program protection.

8.2.2 Program Lock Bits

The lock bits when programmed according to Table 8- 1. will provide different level of protection for the on-chip code and data. U: unprogrammed P: programmed

8.2.3 Signature bytes

The TS83C51RB2/RC2/RD2 contains 4 factory programme d signatures bytes. To read these bytes, perform the process described in section 8.3. Table 8-1. Program Lock bits Program Lock Bits Protection Description Security level LB1 LB2 LB3

1 U U U

No program lock features enabled. Code verify will still be encrypted by the encryption array if programmed. MOVC instruc tion executed from external program memory returns non encrypted data.

2 P U U

MOVC instruction executed from external program mem ory are disabled from fetching code bytes from internal mem ory, EA is sampled and latched on reset. 3 U P U Same as level 1+ Verify disable. This security level is only available for 51RDX2 de vices.

4188F–8051–01/08 AT/TS8xC51Rx2

8.2.4 Verify Algorithm

Refer to Section “Verify algorithm”.

4188F–8051–01/08 AT/TS8xC51Rx2 9. TS87C51RB2/RC2/RD2 EPROM

9.1 EPROM Structure

The TS87C51RB2/RC2/RD2 EPROM is divided in two diff erent arrays:

• the code array:16/32/64 Kbytes.
• the encryption array:64 bytes. In addition a third non programmable array is implemented:
• the signature array: 4 bytes.

9.2 EPROM Lock System

The program Lock system, when programmed, protects the on-chip program against software piracy.

9.2.1 Encryption Array

Within the EPROM array are 64 bytes of encryption a rray that are initially unprogrammed (all FF’s). Every time a byte is addressed during program verify, 6 address lines are used to select a byte of the encryption array. This byte is then exclusive-NOR’ed (XNOR) with the code byte, cre- ating an encrypted verify byte. The algorithm, with the encryption array in the unprogrammed state, will return the code in its original, unmodified form. When using the encryption array, one important fact or needs to be considered. If a byte has the value FFh, verifying the byte will produce the encr yption byte value. If a large block (>64 bytes) of code is left unprogrammed, a verification routin e will display the content of the encryption array. For this reason all the unused code bytes sh ould be programmed with random values. This will ensure program protection.

9.2.2 Program Lock Bits

The three lock bits, when programmed according to Table 9-1.9.2.3, will provide different level of protection for the on-chip code and data. U: unprogrammed, P: programmed Table 9-1. Program Lock bits Program Lock Bits Protection Description Security level LB1 LB2 LB3 No program lock features enabled. Code verify will still be encrypted by the encryption array if programmed. MO VC instruction executed from external program memory returns non encrypted data. MOVC instruction executed from external program mem ory are disabled from fetching code bytes from internal mem ory, EA is sampled and latched on reset, and further programmi ng of the EPROM is disabled. 3 U P U Same as 2, also verify is disabled. 4 U U P Same as 3, also external execution is disabled.

4188F–8051–01/08 AT/TS8xC51Rx2 WARNING: Security level 2 and 3 should only be prog rammed after EPROM and Core verification.

9.2.3 Signature bytes

The TS87C51RB2/RC2/RD2 contains 4 factory programme d signatures bytes. To read these bytes, perform the process described in Section “Sig nature bytes”.

9.3 EPROM Programming

9.3.1 Set-up Modes

In order to program and verify the EPROM or to read the signature bytes, the TS87C51RB2/RC2/RD2 is placed in specific set-up mod es (See Figure 9-1.). Control and program signals must be held at the levels indicated in Table 9-2.

9.3.2 Definition of Terms

P3.4 (A14) for RC, P3.5 (A15) for RD) Data Lines: P0.0-P0.7 for D0-D7 Control Signals: RST, PSEN Program Signals: ALE/PROG , EA /VPP. Table 9-2. EPROM Set-Up Modes Mode RST PSEN ALE/P ROG EA /VP Program Code data 1 0 12.75V 0 1 1 1 1 Verify Code data 1 0 1 1 0 0 1 1 Program Encryption Array Address 0-3Fh 1 0 12.75V 0 1 1 0 1 Read Signature Bytes 1 0 1 1 0 0 0 0 Program Lock bit 1 1 0 12.75V 1 1 1 1 1 Program Lock bit 2 1 0 12.75V 1 1 1 0 0 Program Lock bit 3 1 0 12.75V 1 0 1 1 0

4188F–8051–01/08 AT/TS8xC51Rx2 Figure 9-1. Set-Up Modes Configuration

9.3.3 Programming Algorithm

The Improved Quick Pulse algorithm is based on the Quick Pulse algorithm and decreases the number of pulses applied during byte programming from 25 to 1. To program the TS87C51RB2/RC2/RD2 the following sequence must be exercised:

• Step 1: Activate the combination of control signal s.
• Step 2: Input the valid address on the address lin es.
• Step 3: Input the appropriate data on the data lin es.
• Step 4: Raise EA /VPP from VCC to VPP (typical 12.75V).
• Step 5: Pulse ALE/PROG once.
• Step 6: Lower EA /VPP from VPP to VCC Repeat step 2 through 6 changing the address and da ta for the entire array or until the end of the object file is reached (See Figure 9-2 ).

9.3.4 Verify algorithm

Code array verify must be done after each byte or b lock of bytes is programmed. In either case, a complete verify of the programmed array will ensu re reliable programming of the TS87C51RB2/RC2/RD2. P 2.7 is used to enable data output. To verify the TS87C51RB2/RC2/RD2 code the following sequence must be exercised:

• Step 1: Activate the combination of program and co ntrol signals.
• Step 2: Input the valid address on the address lin es.
• Step 3: Read data on the data lines. Repeat step 2 through 3 changing the address for the entire array verification (See Figure 9-2.) +5V VCC P0.0-P0.7 P1.0-P1.7 P2.0-P2.5 P3.4-P3.5 VSS GND D0-D7 A0-A7 A8-A15 RST EA /VPP ALE/PROG PSEN P2.6 P2.7 P3.3 P3.7 P3.6 XTAL1 4 to 6 MHz CONTROL SIGNALS* PROGRAM SIGNALS* * See Table 31. for proper value on these inputs

observing that the code array is well encrypted.

9.4 EPROM Erasure (Windowed Packages Only)

parts to full functionality. Erasure leaves all the EPROM cells in a 1’s state (FF).

9.4.1 Erasure Characteristics

1. Exposing the EPROM to an ultraviolet lamp of 12,0 00 µ W/cm 2 rat-

recommended with most of standard erasers. Table 31. for Read Signature Bytes. Table 10-1. sho ws the content of the signature byte for the

4188F–8051–01/08 AT/TS8xC51Rx2 60h FCh Product name: TS87C51RD2 60h 37h Product name: TS83C51RC2 60h B7h Product name: TS87C51RC2 60h 3Bh Product name: TS83C51RB2 60h BBh Product name: TS87C51RB2 61h FFh Product revision number

4188F–8051–01/08 AT/TS8xC51Rx2 11. Electrical Characteristics

11.1 Absolute Maximum Ratings

11.2 Power Consumption Measurement

Since the introduction of the first C51 devices, every manufacturer made operating Icc measure- ments under reset, which made sense for the designs were the CPU was running under reset. In Atmel new devices, the CPU is no more active during reset, so the power consumption is very low but is not really representative of what will happen in the customer system. That’s why, while keeping measurements under Reset, Atmel presents a new way to measure the operating Icc: Using an internal test ROM, the following code is executed: Label: SJMP Label (80 FE) Ports 1, 2, 3 are disconnected, Port 0 is tied to F Fh, EA = Vcc, RST = Vss, XTAL2 is not con- nected and XTAL1 is driven by the clock. This is much more representative of the real operating Icc.

11.3 DC Parameters for Standard Voltage

TA = 0 °C to +70 °C; V SS = 0 V; V CC = 5 V ± 10%; F = 0 to 40 MHz. TA = -40 °C to +85 °C; V SS = 0 V; V CC = 5 V ± 10%; F = 0 to 40 MHz. Ambiant Temperature Under Bias: Voltage on V *NOTICE: Stresses at or above those listed under “ Abso- lute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Power dissipation is based on the maximum allowable die temperature and the thermal resis- tance of the package. Table 11-1. DC Parameters in Standard Voltage Symbol Parameter Min Typ Max Unit Test Conditions VIL Input Low Voltage -0.5 0.2 V CC - 0.1 V VIH Input High Voltage except XTAL1, RST 0.2 V CC + 0.9 V CC + 0.5 V VIH1 Input High Voltage, XTAL1, RST 0.7 V CC VCC + 0.5 V VOL Output Low Voltage, ports 1, 2, 3, 4, 5 (6) 0.3 0.45 1.0 V V V I OL = 100 µ A(4) IOL = 1.6 mA (4) IOL = 3.5 mA (4) VOL1 Output Low Voltage, port 0 (6) 0.3 0.45 1.0 V V V I OL = 200 µ A(4) IOL = 3.2 mA (4) IOL = 7.0 mA (4) VOL2 Output Low Voltage, ALE, PSEN 0.3 0.45 1.0 V V V I OL = 100 µ A(4) IOL = 1.6 mA (4) IOL = 3.5 mA (4)

4188F–8051–01/08 AT/TS8xC51Rx2 VOH Output High Voltage, ports 1, 2, 3, 4, 5 VCC - 0.3 VCC - 0.7 VCC - 1.5 V V V I OH = -10 µ A IOH = -30 µ A IOH = -60 µ A VCC = 5 V ± 10% VOH1 Output High Voltage, port 0 VCC - 0.3 VCC - 0.7 VCC - 1.5 V V V I OH = -200 µ A IOH = -3.2 mA IOH = -7.0 mA VCC = 5 V ± 10% VOH2 Output High Voltage,ALE, PSEN VCC - 0.3 VCC - 0.7 VCC - 1.5 V V V I OH = -100 µ A IOH = -1.6 mA IOH = -3.5 mA VCC = 5 V ± 10% RRST RST Pulldown Resistor 50 90 (5) 200 k Ω IIL Logical 0 Input Current ports 1, 2, 3, 4, 5 -50 µ A Vin = 0.45 V ILI Input Leakage Current ±10 µ A 0.45 V < Vin < V CC ITL Logical 1 to 0 Transition Current, ports 1, 2, 3, 4 , 5 -650 µ A Vin = 2.0 V CIO Capacitance of I/O Buffer 10 pF Fc = 1 MHz T A = 25 °C IPD Power-down Current 20 (5) 50 µ A 2.0 V < V CC < 5.5 V (3) ICC under RESET Power Supply Current Maximum values, X1 mode: (7) 1 + 0.4 Freq (MHz) @12MHz 5.8 @16MHz 7.4 mA V CC = 5.5 V (1) ICC operating Power Supply Current Maximum values, X1 mode: (7) 3 + 0.6 Freq (MHz) @12MHz 10.2 @16MHz 12.6 mA V CC = 5.5 V (8) ICC idle Power Supply Current Maximum values, X1 mode: (7) 0.25+0.3 Freq (MHz) @12MHz 3.9 @16MHz 5.1 mA V CC = 5.5 V (2) Table 11-1. DC Parameters in Standard Voltage Symbol Parameter Min Typ Max Unit Test Conditions

4188F–8051–01/08 AT/TS8xC51Rx2

11.4 DC Parameters for Low Voltage

TA = 0 °C to +70 °C; V SS = 0 V; V CC = 2.7 V to 5.5 V ± 10%; F = 0 to 30 MHz. TA = -40 °C to +85 °C; V SS = 0 V; V CC = 2.7 V to 5.5 V ± 10%; F = 0 to 30 MHz. Notes: 1. I CC under reset is measured with all output pins disconnected; XTAL1 driven with T CLCH , T CHCL = 5 ns (see Figure 11-5.), V IL = V SS + 0.5 V, 2. Idle I CC is measured with all output pins disconnected; XTAL1 driven with T CLCH , T CHCL = 5 ns, V IL = V SS + 0.5 V, V IH = V CC - 0.5 V; XTAL2 N.C; Port 0 = V CC ; EA = RST = V SS (see Figure 11-3.). 3. Power-down I CC is measured with all output pins disconnected; EA = V SS , PORT 0 = V CC ; XTAL2 NC.; RST = V SS (see Fig- ure 11-4.). Table 11-2. DC Parameters for Low Voltage Symbol Parameter Min Typ Max Unit Test Conditions VIL Input Low Voltage -0.5 0.2 V CC - 0.1 V VIH Input High Voltage except XTAL1, RST 0.2 V CC + 0.9 V CC + 0.5 V VIH1 Input High Voltage, XTAL1, RST 0.7 V CC VCC + 0.5 V VOL Output Low Voltage, ports 1, 2, 3, 4, 5 (6) 0.45 V I OL = 0.8 mA (4) VOL1 Output Low Voltage, port 0, ALE, PSEN (6) 0.45 V I OL = 1.6 mA (4) VOH Output High Voltage, ports 1, 2, 3, 4, 5 0.9 V CC V I OH = -10 µ A VOH1 Output High Voltage, port 0, ALE, PSEN 0.9 V CC V I OH = -40 µ A IIL Logical 0 Input Current ports 1, 2, 3, 4, 5 -50 µ A Vin = 0.45 V ILI Input Leakage Current ±10 µ A 0.45 V < Vin < V CC ITL Logical 1 to 0 Transition Current, ports 1, 2, 3, 4 , 5 -650 µ A Vin = 2.0 V RRST RST Pulldown Resistor 50 90 (5) 200 k Ω CIO Capacitance of I/O Buffer 10 pF Fc = 1 MHz T A = 25 °C IPD Power-down Current 20 (5) 10 (5) 30 µ A V CC = 2.0 V to 5.5 V (3) VCC = 2.0 V to 3.3 V (3) IPD Power-down Current (Only for TS87C51RD2 S287-xxx Very Low power) 2 (5) 15 µ A 2.0 V < V CC < 3.6 V (3) ICC under RESET Power Supply Current Maximum values, X1 mode: (7) 1 + 0.2 Freq (MHz) @12MHz 3.4 @16MHz 4.2 mA V CC = 3.3 V (1) ICC operating Power Supply Current Maximum values, X1 mode: (7) 1 + 0.3 Freq (MHz) @12MHz 4.6 @16MHz 5.8 mA V CC = 3.3 V (8) ICC idle Power Supply Current Maximum values, X1 mode: (7)

0.15 Freq

(MHz) + 0.2 @12MHz 2 @16MHz 2.6 mA V CC = 3.3 V (2)

4188F–8051–01/08 AT/TS8xC51Rx2 Figure 11-3. ICC Test Condition, Idle Mode Figure 11-4. ICC Test Condition, Power-Down Mode Figure 11-5. Clock Signal Waveform for I CC Tests in Active and Idle Modes

11.5 AC Parameters

11.5.1 Explanation of the AC Symbols

Each timing symbol has 5 characters. The first char acter is always a “T” (stands for time). The other characters, depending on their positions, sta nd for the name of a signal or the logical sta- tus of that signal. The following is a list of all the characters and what they stand for. Example:TAVLL = Time for Address Valid to ALE Low. TLLPL = Time for ALE Low to PSEN Low. TA = 0 to +70 °C (commercial temperature range); V SS = 0 V; V CC = 5 V ± 10%; -M and -V ranges. TA = -40 °C to +85 °C (industrial temperature range); V SS = 0 V; V CC = 5 V ± 10%; -M and -V ranges. RST EA XTAL2 XTAL1 V SS VCC VCC ICC (NC) VCC All other pins are disconnected. CLOCK SIGNAL Reset = Vss after a high pulse during at least 24 clock cycles RST EA XTAL2 XTAL1 V SS VCC VCC ICC (NC) VCC All other pins are disconnected. Reset = Vss after a high pulse during at least 24 clock cycles VCC -0.5V 0.45V 0.7V CC 0.2V CC -0.1 TCLCH TCHCL TCLCH = T CHCL = 5ns.

4188F–8051–01/08 AT/TS8xC51Rx2 TA = 0 to +70 °C (commercial temperature range); V SS = 0 V; 2.7 V < V CC < 5.5 V; -L range. TA = -40 °C to +85 °C (industrial temperature range); V SS = 0 V; 2.7 V < V CC < 5.5 V; -L range. Table 11-3. gives the maximum applicable load capacitance for Port 0, Port 1, 2 and 3, and ALE and PSEN signals. Timings will be guaranteed if these capac itances are respected. Higher capacitance values can be used, but timings will then be degraded. Table 11-3. Load Capacitance versus speed range, in pF Table 11-5., Table 39. and Table 42. give the description of each AC symbols. Table 11-6., Table 11-8. and Table 11-10. give for each range the AC parameter. Table 11-7., Table 11-9. and Table 11-11. give the frequency derating formula of the AC param- eter. To calculate each AC symbols, take the x valu e corresponding to the speed grade you need (-M, -V or -L) and replace this value in the formula. Values of the frequency must be limited to the corresponding speed grade: Table 11-4. Max frequency for derating formula regarding the speed grade Example: T LLIV in X2 mode for a -V part at 20 MHz (T = 1/20 E6 = 50 ns): x= 22 (Table 11-7.) T= 50ns T LLIV = 2T - x = 2 x 50 - 22 = 78ns -M -V -L Port 0 100 50 100 Port 1, 2, 3 80 50 80 ALE / PSEN 100 30 100 -M X1 mode -M X2 mode -V X1 mode -V X2 mode -L X1 mode - L X2 mode Freq (MHz) 40 20 40 30 30 20 T (ns) 25 50 25 33.3 33.3 50

4188F–8051–01/08 AT/TS8xC51Rx2

11.5.2 External Program Memory Characteristics

Table 11-5. Symbol Description Table 11-6. AC Parameters for Fix Clock Symbol Parameter T Oscillator clock period TLHLL ALE pulse width TAVLL Address Valid to ALE TLLAX Address Hold After ALE TLLIV ALE to Valid Instruction In TLLPL ALE to PSEN TPLPH PSEN Pulse Width TPLIV PSEN to Valid Instruction In TPXIX Input Instruction Hold After PSEN TPXIZ Input Instruction FloatAfter PSEN TPXAV PSEN to Address Valid TAVIV Address to Valid Instruction In TPLAZ PSEN Low to Address Float Speed

40 MHz

30 MHz

60 MHz equiv. standard mode

20 MHz

40 MHz equiv. standard mode Symbol Min Max Min Max Min Max Min Max Min Max T 25 33 25 50 33 ns TLHLL 40 25 42 35 52 ns TAVLL 10 4 12 5 13 ns TLLAX 10 4 12 5 13 ns TLLIV 70 45 78 65 98 ns TLLPL 15 9 17 10 18 ns TPLPH 55 35 60 50 75 ns TPLIV 35 25 50 30 55 ns TPXIX 0 0 0 0 0 ns TPXIZ 18 12 20 10 18 ns TAVIV 85 53 95 80 122 ns TPLAZ 10 10 10 10 10 ns

4188F–8051–01/08 AT/TS8xC51Rx2 Table 11-7. AC Parameters for a Variable Clock: derating formula

11.5.3 External Program Memory Read Cycle

Figure 11-6. External Program Memory Read Cycle Symbol Type Standard Clock X2 Clock -M -V -L Units TLHLL Min 2 T - x T - x 10 8 15 ns TAVLL Min T - x 0.5 T - x 15 13 20 ns TLLAX Min T - x 0.5 T - x 15 13 20 ns TLLIV Max 4 T - x 2 T - x 30 22 35 ns TLLPL Min T - x 0.5 T - x 10 8 15 ns TPLPH Min 3 T - x 1.5 T - x 20 15 25 ns TPLIV Max 3 T - x 1.5 T - x 40 25 45 ns TPXIX Min x x 0 0 0 ns TPXIZ Max T - x 0.5 T - x 7 5 15 ns TAVIV Max 5 T - x 2.5 T - x 40 30 45 ns TPLAZ Max x x 10 10 10 ns TPLIV TPLAZ ALE PSEN PORT 0 PORT 2 A0-A7 A0-A7 INSTR IN INSTR IN INSTR IN ADDRESS OR SFR-P2 ADDRESS A8-A15 ADDRESS A8-A15

12 T CLCL

4188F–8051–01/08 AT/TS8xC51Rx2

11.5.4 External Data Memory Characteristics

Table 11-8. AC Parameters for a Fix Clock Symbol Parameter TRLRH RD Pulse Width TWLWH WR Pulse Width TRLDV RD to Valid Data In TRHDX Data Hold After RD TRHDZ Data Float After RD TLLDV ALE to Valid Data In TAVDV Address to Valid Data In TLLWL ALE to WR or RD TAVWL Address to WR or RD TQVWX Data Valid to WR Transition TQVWH Data set-up to WR High TWHQX Data Hold After WR TRLAZ RD Low to Address Float TWHLH RD or WR High to ALE high Speed -M 60 MHz equiv. standard mode 40 MHz X2 mode 40 MHz equiv. standard mode Symbol Min Max Min Max Min Max Min Max Min Max TRLRH 130 85 135 125 175 ns TWLWH 130 85 135 125 175 ns TRLDV 100 60 102 95 137 ns TRHDX 0 0 0 0 0 ns TRHDZ 30 18 35 25 42 ns TLLDV 160 98 165 155 222 ns TAVDV 165 100 175 160 235 ns TLLWL 50 100 30 70 55 95 45 105 70 130 ns TAVWL 75 47 80 70 103 ns TQVWX 10 7 15 5 13 ns TQVWH 160 107 165 155 213 ns TWHQX 15 9 17 10 18 ns TRLAZ 0 0 0 0 0 ns TWHLH 10 40 7 27 15 35 5 45 13 53 ns

4188F–8051–01/08 AT/TS8xC51Rx2 Table 11-9. AC Parameters for a Variable Clock: derating formula

11.5.5 External Data Memory Write Cycle

Figure 11-7. External Data Memory Write Cycle

11.5.6 External Data Memory Read Cycle

Clock X2 Clock -M -V -L Units TRLRH Min 6 T - x 3 T - x 20 15 25 ns TWLWH Min 6 T - x 3 T - x 20 15 25 ns TRLDV Max 5 T - x 2.5 T - x 25 23 30 ns TRHDX Min x x 0 0 0 ns TRHDZ Max 2 T - x T - x 20 15 25 ns TLLDV Max 8 T - x 4T -x 40 35 45 ns TAVDV Max 9 T - x 4.5 T - x 60 50 65 ns TLLWL Min 3 T - x 1.5 T - x 25 20 30 ns TLLWL Max 3 T + x 1.5 T + x 25 20 30 ns TAVWL Min 4 T - x 2 T - x 25 20 30 ns TQVWX Min T - x 0.5 T - x 15 10 20 ns TQVWH Min 7 T - x 3.5 T - x 15 10 20 ns TWHQX Min T - x 0.5 T - x 10 8 15 ns TRLAZ Max x x 0 0 0 ns TWHLH Min T - x 0.5 T - x 15 10 20 ns TWHLH Max T + x 0.5 T + x 15 10 20 ns TQVWH TLLAX ALE PSEN WR PORT 0 PORT 2 A0-A7 DATA OUT ADDRESS OR SFR-P2 TAVWL TLLWL TQVWX ADDRESS A8-A15 OR SFR P2 TWHQX TWHLH TWLWH

4188F–8051–01/08 AT/TS8xC51Rx2 Figure 11-8. External Data Memory Read Cycle

11.5.7 Serial Port Timing - Shift Register Mode

Table 11-10. AC Parameters for a Fix Clock Symbol Parameter TXLXL Serial port clock cycle time TQVHX Output data set-up to clock rising edge TXHQX Output data hold after clock rising edge TXHDX Input data hold after clock rising edge TXHDV Clock rising edge to input data valid ALE PSEN RD PORT 0 PORT 2 A0-A7 DATA IN ADDRESS OR SFR-P2 TAVWL TLLWL TRLAZ ADDRESS A8-A15 OR SFR P2 TRHDZ TWHLH TRLRH TLLDV TRHDX TAVDV TLLAX TRLDV Speed 60 MHz equiv. standard mode 40 MHz X2 mode 40 MHz equiv. standard mode Symbol Min Max Min Max Min Max Min Max Min Max TXLXL 300 200 300 300 400 ns TQVHX 200 117 200 200 283 ns TXHQX 30 13 30 30 47 ns TXHDX 0 0 0 0 0 ns TXHDV 117 34 117 117 200 ns

4188F–8051–01/08 AT/TS8xC51Rx2 Table 11-11. AC Parameters for a Variable Clock: derating formula

11.5.8 Shift Register Timing Waveforms

Figure 11-9. Shift Register Timing Waveforms Symbol Type Standard Clock X2 Clock -M -V -L Units TXLXL Min 12 T 6 T ns TQVHX Min 10 T - x 5 T - x 50 50 50 ns TXHQX Min 2 T - x T - x 20 20 20 ns TXHDX Min x x 0 0 0 ns TXHDV Max 10 T - x 5 T- x 133 133 133 ns V ALID VALID INPUT DATA VALID VALID 0 1 2 3 4 5 6 8 7 ALE CLOCK OUTPUT DATA WRITE to SBUF CLEAR RI TXLXL TQVXH TXHQX TXHDV TXHDX SET TI SET RI INSTRUCTION 0 1 2 3 4 5 6 7 VALID V ALID VALID VALID

4188F–8051–01/08 AT/TS8xC51Rx2

11.5.9 EPROM Programming and Verification Characteri stics

TA = 21 °C to 27 °C; V SS = 0V; V CC = 5V ± 10% while programming. V CC = operating range while verifying

11.5.10 EPROM Programming and Verification Waveforms

Figure 11-10. EPROM Programming and Verification Waveforms Symbol Parameter Min Max Units VPP Programming Supply Voltage 12.5 13 V IPP Programming Supply Current 75 mA 1/T CLCL Oscillator Frquency 4 6 MHz TAVGL Address Setup to PROG Low 48 T CLCL TGHAX Adress Hold after PROG 48 T CLCL TDVGL Data Setup to PROG Low 48 T CLCL TGHDX Data Hold after PROG 48 T CLCL TEHSH (Enable) High to V PP 48 T CLCL TSHGL VPP Setup to PROG Low 10 µ s TGHSL VPP Hold after PROG 10 µ s TGLGH PROG Width 90 110 µ s TAVQV Address to Valid Data 48 T CLCL TELQV ENABLE Low to Data Valid 48 T CLCL TEHQZ Data Float after ENABLE 0 48 T CLCL TGHSL TEHSH ALE/PROG TAVGL TDVGL P1.0-P1.7 P2.0-P2.5 P3.4-P3.5* EA/V PP CONTROL SIGNALS (ENABLE) ADDRESS DATA IN VCC VPP VCC TGHAX TGHDX TGLGH TSHGL ADDRESS DATA OUT TAVQV TELQV TEHQZ PROGRAMMING VERIFICATION * 8KB: up to P2.4, 16KB: up to P2.5, 32KB: up to P3 .4, 64KB: up to P3.5

4188F–8051–01/08 AT/TS8xC51Rx2

11.5.11 External Clock Drive Characteristics (XTAL1)

11.5.12 External Clock Drive Waveforms

Figure 11-11. External Clock Drive Waveforms

11.5.13 AC Testing Input/Output Waveforms

Figure 11-12. AC Testing Input/Output Waveforms AC inputs during testing are driven at V CC - 0.5 for a logic “1” and 0.45V for a logic “0”. T iming measurement are made at V IH min for a logic “1” and V IL max for a logic “0”.

11.5.14 Float Waveforms

Figure 11-13. Float Waveforms For timing purposes a port pin is no longer floatin g when a 100 mV change from load voltage occurs and begins to float when a 100 mV change fro m the loaded V OH /V OL level occurs. I OL /I OH ≥ ± 20mA. Symbol Parameter Min Max Units TCLCL Oscillator Period 25 ns TCHCX High Time 5 ns TCLCX Low Time 5 ns TCLCH Rise Time 5 ns TCHCL Fall Time 5 ns TCHCX /T CLCX Cyclic ratio in X2 mode 40 60 % VCC -0.5 V 0.45 V 0.7V CC 0.2V CC -0.1 V TCHCL TCLCX TCLCL TCLCH TCHCX 0.45 V VCC -0.5 V 0.2V CC +0.9 0.2V CC -0.1 INPUT/OUTPUT VOL +0.1 V VOH -0.1 V FLOAT VLOAD VLOAD +0.1 V VLOAD -0.1 V

4188F–8051–01/08 AT/TS8xC51Rx2

11.5.15 Clock Waveforms

Valid in normal clock mode. In X2 mode XTAL2 signal must be changed to XTAL2 divided by two. Figure 11-14. Clock Waveforms This diagram indicates when signals are clocked internally. The time it takes the signals to prop- agate to the pins, however, ranges from 25 to 125 n s. This propagation delay is dependent on variables such as temperature and pin loading. Prop agation also varies from output to output and component. Typically though (T A=25 °C fully loaded) RD and WR propagation delays are approximately 50ns. The other signals are typically 85 ns. Propagation delays are incorporated in the AC specifications. CLOCK XTAL2 ALE INTERNAL STATE4 STATE5 STATE6 STATE1 STATE2 STATE3 STATE4 STATE5 EXTERNAL PROGRAM MEMORY FETCH READ CYCLE WRITE CYCLE SERIAL PORT SHIFT CLOCK PORT OPERATION PSEN P2 (EXT) RD WR TXD (MODE 0) RXD SAMPLED RXD SAMPLED P0 PINS SAMPLED P1, P2, P3 PINS SAMPLED P1, P2, P3 PINS SAMPLED P0 PINS SAMPLED MOV DEST PORT (P1, P2, P3) (INCLUDES INT0, INT1, TO, T1) MOV DEST P0 OLD DATA NEW DATA DPL OR Rt OUT DATA OUT PCL OUT (EVEN IF PROGRAM MEMORY IS INTERNAL) PCL OUT (IF PROGRAM MEMORY IS EXTERNAL) INDICATES DPH OR P2 SFR TO PCH TRANSITION DPL OR Rt OUT FLOAT PCL OUT (IF PROGRAM MEMORY IS EXTERNAL) INDICATES DPH OR P2 SFR TO PCH TRANSITION INDICATES ADDRESS TRANSITIONS FLOAT FLOAT FLOAT PCL OUT PCL OUT PCL OUT DATA SAMPLED DATA SAMPLED DATA SAMPLED THESE SIGNALS ARE NOT ACTIVATED DURING THE EXECUTION OF A MOVX INSTRUCTION P1P2 P1P2 P1P2 P1P2 P1P2 P1P2 P1P2 P1P2

4188F–8051–01/08 AT/TS8xC51Rx2 12. Ordering Information Part Number Memory size Supply Voltage Temperature R ange Max Frequency Package Packing TS80C51RA2-MCA OBSOLETE TS80C51RA2-MCB TS80C51RA2-MCE TS80C51RA2-MIA TS80C51RA2-MIB TS80C51RA2-MIE TS80C51RA2-LCA TS80C51RA2-LCB TS80C51RA2-LCE TS80C51RA2-LIA TS80C51RA2-LIB TS80C51RA2-LIE TS80C51RA2-VCA TS80C51RA2-VCB TS80C51RA2-VCE TS80C51RA2-VIA TS80C51RA2-VIB TS80C51RA2-VIE AT80C51RA2-3CSUM Romless 5V Industrial & Green 40 MHz ( 20 MHz X2) PDIL40 Stick AT80C51RA2-SLSUM Romless 5V Industrial & Green 40 MHz ( 20 MHz X2) PLCC44 Stick AT80C51RA2-RLTUM Romless 5V Industrial & Green 40 MHz ( 20 MHz X2) VQFP44 Tray AT80C51RA2-3CSIM OBSOLETE AT80C51RA2-SLSIM AT80C51RA2-RLTIM AT80C51RA2-3CSCL AT80C51RA2-SLSCL AT80C51RA2-RLTCL AT80C51RA2-3CSUL Romless 3-5V Industrial & Green 30 MHz (20 MHz X2) PDIL40 Stick AT80C51RA2-SLSUL Romless 3-5V Industrial & Green 30 MHz (20 MHz X2) PLCC44 Stick AT80C51RA2-RLTUL Romless 3-5V Industrial & Green 30 MHz (20 MHz X2) VQFP44 Tray

4188F–8051–01/08 AT/TS8xC51Rx2 AT80C51RA2-3CSCV OBSOLETE AT80C51RA2-SLSCV AT80C51RA2-RLTCV AT80C51RA2-3CSIV AT80C51RA2-SLSIV AT80C51RA2-RLSIV TS80C51RD2-MCA Not recommended use AT87C51RD2 TS80C51RD2-MCB Not recommended use AT87C51RD2 TS80C51RD2-MCE Not recommended use AT87C51RD2 TS80C51RD2-MIA Not recommended use AT87C51RD2 TS80C51RD2-MIB Not recommended use AT87C51RD2 TS80C51RD2-MIE Not recommended use AT87C51RD2 TS80C51RD2-LCA Not recommended use AT87C51RD2 TS80C51RD2-LCB Not recommended use AT87C51RD2 TS80C51RD2-LCE Not recommended use AT87C51RD2 TS80C51RD2-LIA Not recommended use AT87C51RD2 TS80C51RD2-LIB Not recommended use AT87C51RD2 TS80C51RD2-LIE Not recommended use AT87C51RD2 TS80C51RD2-VCA Not recommended use AT87C51RD2 TS80C51RD2-VCB Not recommended use AT87C51RD2 TS80C51RD2-VCE Not recommended use AT87C51RD2 TS80C51RD2-VIA Not recommended use AT87C51RD2 TS80C51RD2-VIB Not recommended use AT87C51RD2 TS80C51RD2-VIE Not recommended use AT87C51RD2 AT80C51RD2-3CSUM Not recommended use AT87C51RD2 AT80C51RD2-SLSUM Not recommended use AT87C51RD2 AT80C51RD2-RLTUM Not recommended use AT87C51RD2 AT80C51RD2-3CSUL Not recommended use AT87C51RD2 AT80C51RD2-SLSUL Not recommended use AT87C51RD2 AT80C51RD2-RLTUL Not recommended use AT87C51RD2 Part Number Memory size Supply Voltage Temperature R ange Max Frequency Package Packing

4188F–8051–01/08 AT/TS8xC51Rx2 TS87C51RB2-MCA OBSOLETE TS87C51RB2-MCB TS87C51RB2-MCE TS87C51RB2-MIA TS87C51RB2-MIB TS87C51RB2-MIE TS87C51RB2-LCA TS87C51RB2-LCB TS87C51RB2-LCE TS87C51RB2-LIA TS87C51RB2-LIB TS87C51RB2-LIE TS87C51RB2-VCA TS87C51RB2-VCB TS87C51RB2-VCE TS87C51RB2-VIA TS87C51RB2-VIB TS87C51RB2-VIE AT87C51RB2-3CSUM OTP 16k Bytes 5V Industrial & Green 40 MHz (20 MHz X2) PDIL40 Stick AT87C51RB2-SLSUM OTP 16k Bytes 5V Industrial & Green 40 MHz (20 MHz X2) PLCC44 Stick AT87C51RB2-RLTUM OTP 16k Bytes 5V Industrial & Green 40 MHz (20 MHz X2) VQFP44 Tray AT87C51RB2-3CSUL OTP 16k Bytes 3-5V Industrial & Green 30 MHz (20 MHz X2) PDIL40 Stick AT87C51RB2-SLSUL OTP 16k Bytes 3-5V Industrial & Green 30 MHz (20 MHz X2) PLCC44 Stick AT87C51RB2-RLTUL OTP 16k Bytes 3-5V Industrial & Green 30 MHz (20 MHz X2) VQFP44 Tray Part Number Memory size Supply Voltage Temperature R ange Max Frequency Package Packing

4188F–8051–01/08 AT/TS8xC51Rx2 TS87C51RC2-MCA OBSOLETE TS87C51RC2-MCB TS87C51RC2-MCE TS87C51RC2-MIA TS87C51RC2-MIB TS87C51RC2-MIE TS87C51RC2-LCA TS87C51RC2-LCB TS87C51RC2-LCE TS87C51RC2-LIA TS87C51RC2-LIB TS87C51RC2-LIE TS87C51RC2-VCA TS87C51RC2-VCB TS87C51RC2-VCE TS87C51RC2-VIA TS87C51RC2-VIB TS87C51RC2-VIE AT87C51RC2-3CSUM OTP 32k Bytes 5V Industrial & Green 40 MHz (20 MHz X2) PDIL40 Stick AT87C51RC2-SLSUM OTP 32k Bytes 5V Industrial & Green 40 MHz (20 MHz X2) PLCC44 Stick AT87C51RC2-RLTUM OTP 32k Bytes 5V Industrial & Green 40 MHz (20 MHz X2) VQFP44 Tray AT87C51RC2-3CSUL OTP 32k Bytes 3-5V Industrial & Green 30 MHz (20 MHz X2) PDIL40 Stick AT87C51RC2-SLSUL OTP 32k Bytes 3-5V Industrial & Green 30 MHz (20 MHz X2) PLCC44 Stick AT87C51RC2-RLTUL OTP 32k Bytes 3-5V Industrial & Green 30 MHz (20 MHz X2) VQFP44 Tray Part Number Memory size Supply Voltage Temperature R ange Max Frequency Package Packing

4188F–8051–01/08 AT/TS8xC51Rx2 TS87C51RD2-MCA OBSOLETE TS87C51RD2-MCB TS87C51RD2-MCE TS87C51RD2-MIA TS87C51RD2-MIB TS87C51RD2-MIE TS87C51RD2-LCA TS87C51RD2-LCB TS87C51RD2-LCE TS87C51RD2-LIA TS87C51RD2-LIB TS87C51RD2-LIE TS87C51RD2-VCA TS87C51RD2-VCB TS87C51RD2-VCE TS87C51RD2-VCL TS87C51RD2-VIA TS87C51RD2-VIB TS87C51RD2-VIE AT87C51RD2-3CSUM OTP 64k Bytes 5V Industrial & Green 40 MHz (20 MHz X2) PDIL40 Stick AT87C51RD2-SLSUM OTP 64k Bytes 5V Industrial & Green 40 MHz (20 MHz X2) PLCC44 Stick AT87C51RD2-RLTUM OTP 64k Bytes 5V Industrial & Green 40 MHz (20 MHz X2) VQFP44 Tray AT87C51RD2-3CSUL OTP 64k Bytes 3-5V Industrial & Green 30 MHz (20 MHz X2) PDIL40 Stick AT87C51RD2-SLSUL OTP 64k Bytes 3-5V Industrial & Green 30 MHz (20 MHz X2) PLCC44 Stick AT87C51RD2-RLTUL OTP 64k Bytes 3-5V Industrial & Green 30 MHz (20 MHz X2) VQFP44 Tray Part Number Memory size Supply Voltage Temperature R ange Max Frequency Package Packing

4188F–8051–01/08 AT/TS8xC51Rx2 TS83C51RB2-MCA OBSOLETE TS83C51RB2-MCB TS83C51RB2-MCE TS83C51RB2-MIA TS83C51RB2-MIB TS83C51RB2-MIE TS83C51RB2-LCA TS83C51RB2-LCB TS83C51RB2-LCE TS83C51RB2-LIA TS83C51RB2-LIB TS83C51RB2-LIE TS83C51RB2-VCA TS83C51RB2-VCB TS83C51RB2-VCE TS83C51RB2-VIA TS83C51RB2-VIB TS83C51RB2-VIE AT83C51RB2-3CSUM ROM 32k Bytes 5V Industrial & Green 4 0 MHz (20 MHz X2) PDIL40 Stick AT83C51RB2-SLSUM ROM 32k Bytes 5V Industrial & Green 4 0 MHz (20 MHz X2) PLCC44 Stick AT83C51RB2-RLTUM ROM 32k Bytes 5V Industrial & Green 4 0 MHz (20 MHz X2) VQFP44 Tray AT83C51RB2-3CSUL ROM 32k Bytes 3-5V Industrial & Green 30 MHz (20 MHz X2) PDIL40 Stick AT83C51RB2-SLSUL ROM 32k Bytes 3-5V Industrial & Green 30 MHz (20 MHz X2) PLCC44 Stick AT83C51RB2-RLTUL ROM 32k Bytes 3-5V Industrial & Green 30 MHz (20 MHz X2) VQFP44 Tray Part Number Memory size Supply Voltage Temperature R ange Max Frequency Package Packing

4188F–8051–01/08 AT/TS8xC51Rx2 TS83C51RC2-MCA OBSOLETE TS83C51RC2-MCB TS83C51RC2-MCE TS83C51RC2-MIA TS83C51RC2-MIB TS83C51RC2-MIE TS83C51RC2-LCA TS83C51RC2-LCB TS83C51RC2-LCE TS83C51RC2-LIA TS83C51RC2-LIB TS83C51RC2-LIE TS83C51RC2-VCA TS83C51RC2-VCB TS83C51RC2-VCE TS83C51RC2-VIA TS83C51RC2-VIB TS83C51RC2-VIE AT83C51RC2-3CSUM ROM 32k Bytes 5V Industrial & Green 4 0 MHz (20 MHz X2) PDIL40 Stick AT83C51RC2-SLSUM ROM 32k Bytes 5V Industrial & Green 4 0 MHz (20 MHz X2) PLCC44 Stick AT83C51RC2-RLTUM ROM 32k Bytes 5V Industrial & Green 4 0 MHz (20 MHz X2) VQFP44 Tray AT83C51RC2-3CSUL ROM 32k Bytes 3-5V Industrial & Green 30 MHz (20 MHz X2) PDIL40 Stick AT83C51RC2-SLSUL ROM 32k Bytes 3-5V Industrial & Green 30 MHz (20 MHz X2) PLCC44 Stick AT83C51RC2-RLTUL ROM 32k Bytes 3-5V Industrial & Green 30 MHz (20 MHz X2) VQFP44 Tray Part Number Memory size Supply Voltage Temperature R ange Max Frequency Package Packing

4188F–8051–01/08 AT/TS8xC51Rx2 TS83C51RD2-MCA OBSOLETE TS83C51RD2-MCB TS83C51RD2-MCE TS83C51RD2-MIA TS83C51RD2-MIB TS83C51RD2-MIE TS83C51RD2-LCB TS83C51RD2-LCE TS83C51RD2-LIA TS83C51RD2-LIB TS83C51RD2-LIE TS83C51RD2-VCA TS83C51RD2-VCB TS83C51RD2-VCE TS83C51RD2-VIA TS83C51RD2-VIB TS83C51RD2-VIE AT83C51RD2-3CSUM ROM 64k Bytes 5V Industrial & Green 4 0 MHz (20 MHz X2) PDIL40 Stick AT83C51RD2-SLSUM ROM 64k Bytes 5V Industrial & Green 4 0 MHz (20 MHz X2) PLCC44 Stick AT83C51RD2-RLTUM ROM 64k Bytes 5V Industrial & Green 4 0 MHz (20 MHz X2) VQFP44 Tray AT83C51RD2-3CSUL ROM 64k Bytes 3-5V Industrial & Green 30 MHz (20 MHz X2) PLCC44 Stick AT83C51RD2-SLSUL ROM 64k Bytes 3-5V Industrial & Green 30 MHz (20 MHz X2) VQFP44 Tray AT83C51RD2-RLTUL ROM 64k Bytes 5V Industrial & Green 4 0 MHz (30 MHz X2) PDIL40 Stick Part Number Memory size Supply Voltage Temperature R ange Max Frequency Package Packing

4188F–8051–01/08 AT/TS8xC51Rx2 13. Package Drawings

13.1 PLCC44

4188F–8051–01/08 AT/TS8xC51Rx2

13.2 PDIL40

4188F–8051–01/08 AT/TS8xC51Rx2

13.3 VQFP44

4188F–8051–01/08 AT/TS8xC51Rx2

13.4 VQFP64

4188F–8051–01/08 AT/TS8xC51Rx2

13.5 PLCC68

1. Datasheet Revision History

14.1 Changes from 4188E to 4188F

1. Removed TS80C51RD2 and AT80C51RD2 from “Ordering Information” on page 73 . 2. Removed non-green part numbers from ordering info rmation.

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