AT87C5103_04 ATMEL | Alldatasheet
Document overview
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Technical content
Features
- 80C51 Compatible CPU Core High-speed Architecture
- X2 Speed Improvement Capability (6 Clocks/Machine Cycle)
- 16 MHz in Standard or X2 mode
- 256 Bytes RAM
- 256 Bytes XRAM
- 12K Bytes ROM/OTP Program Memory
- Two 16-bit Timer/Counters T0, T1
- 5 Channels Programmable Counter Array with High-speed Output, Compare/Capture, Pulse Width Modulation and Watchdog Timer Capabilities
- SPI Interface (Master and Slave mode)
- Interrupt Structure with: – 6 Interrupt Sources – 4 Interrupt Priority Levels
- Power Supply: 3 - 5.5V
- Temperature Range: Industrial (-40oC to 85oC), Automotive (-40oC to 125oC)
- Package: SSOP16, SSOP24
Description
The AT8xC5103 is a high-performance ROM/OTP version of the 80C51 8-bit Micro- controller in 16 and 24-pin packages. The AT8xC5103 contains a standard C51 CPU core with 12 Kbytes ROM/OTP pro- gram memory, 256 bytes of internal RAM, 256 bytes of extended internal RAM, a 5- sources 4-level interrupt system, two timer/counters and a SPI serial bus controller. The AT8xC5103 is also dedicated for analog interfacing applications. For this, it has a five channels Programmable Counter Array. In addition, the AT8xC5103 implements the X2 speed improvement mechanism. The X2 feature allows to keep the same CPU power at a divided by two oscillator frequency. The fully static design of the AT8xC5103 allows to reduce system power consumption by bringing the clock frequency down to any value, even DC, without loss of data. Low-pin Count 8-bit Microcontroller AT87C5103 AT83C5103
4134C–8051–09/04 Block Diagram Notes: Alternate function of Port 1. Alternate function of Port 3. Timer 0 INT RAM 256x8 XTAL2 XTAL1 CPU Timer 1 Ctrl INT0 C51 CORE (3) (3) Port 1 IB-bus Vss Vcc ROM
12 K *8
(1) Port 3 PCA MISO (1) MOSI (1) SPSCK (3) SPI SS (1) RST ECI (1) 256x8 Parallel I/O Ports EXRAM Port 4 INT1 (3) (3)
4134C–8051–09/04 Pin Configurations XTAL1 VCC VSS RST/VPP XTAL2 P1.2/ECI/DIG2 P3.2/DIG0/INT0 P3.6/SPICK P3.4/DIG1/T0 P1.7/CEX4/SS P1.6/CEX3 P1.5/CEX2 P1.4/CEX1 P1.3/CEX0 P1.1/MOSI P1.0/MISO SSOP16 P1.1/MOSI P1.0/MISO VCC XTAL2 P1.5/CEX2 VSS XTAL1 P1.2/ECI/DIG2 RST/VPP P3.1 P3.6/SPICK P1.6/CEX3 P3.7 P3.5/T1 P3.4/DIG1/T0 P4.0 P4.1 P4.2 P1.3/CEX0 P1.4/CEX1 P3.0 P1.7/CEX4/SS P3.3/INT1 P3.2/DIG0/INT0 SSOP24
4134C–8051–09/04 Pin Description Mnemonic Type Name and Function VSS I Ground: 0V reference VCC I Power Supply: 3.0V or 5.5V P1.0 - P1.7 I/O Port 1: Port 1 is an 8-bit programmable I/O port with internal pull-up Alternate functions for Port 1 include: I/O MISO (P1.0): Master IN, Slave OUT of the SPI controller I/O MOSI (P1.1): Master OUT, Slave IN of the SPI controller I/O DIG2 (P1.2): Programmable as Output with Push-pull ECI: External Clock for PCA I/O CEX0 (P1.3): Capture/Compare External I/O for PCA module 0 I/O CEX1 (P1.4): Capture/Compare External I/O for PCA module 1 I/O CEX2 (P1.5): Capture/Compare External I/O for PCA module 2 I/O CEX3 (P1.6): Capture/Compare External I/O for PCA module 3 I/O SS (P1.7): Slave select input of the SPI controller CEX4: Capture/Compare External I/O for PCA module 3 XTAL1 I Input to the inverting oscillator amplifier XTAL2 O Output from the inverting oscillator amplifier RST/VPP I RST: Negative Reset input A low on this pin for two machine cycles while the oscillator is running, resets the device. This pin will include a pull-down to reset the circuit if no external reset level is applied. VPP: High voltage input for OTP programming P3.0 - P3.7 I/O Port 3: Port 3 is a 8-bit programmable I/O port with internal pull-up. I/O P3.0: Programmable as Output with Push-pull. I/O P3.1: Programmable as Output with Push-pull. I/O DIG0 (P3.2): Programmable as Output with Push-pull. INT0: External Interrupt 0 I/O P3.3: Programmable as Output with Push-pull. INT1: External Interrupt 1 I/O DIG1 (P3.4): Programmable as Output with Push-pull. T0: Timer 0 external Input I/O P3.5: Programmable as Output with Push-pull. T1: Timer 1 external Input I/O SPICK (P3.6): Clock I/O of the SPI controller I/O P3.7: Programmable as Output with Push-pull. P4.0-P4.2 I/O Port 4: Port 4 is an 3-bit I/O port with internal pull-up
4134C–8051–09/04 Clock The Errata Sheet core needs only 6 clock periods per machine cycle. This feature, called ”X2”, provides the following advantages: Divides frequency crystals by 2 (cheaper crystals) while keeping the same CPU power. Saves power consumption while keeping the same CPU power (oscillator power saving). Saves power consumption by dividing dynamic operating frequency by 2 in operating and idle modes. Increases CPU power by 2 while keeping the same crystal frequency. In order to keep the original C51 compatibility, a divider-by-2 is inserted between the XTAL1 signal and the main clock input of the core (phase generator). This divider may be disabled by the software. The clock for the whole circuit and peripheral is first divided by 2 before being used by the CPU core and peripherals. This allows any cyclic ratio to be accepted on the XTAL1 input. In X2 Mode, as this divider is bypassed, the signals on XTAL1 must have a cyclic ratio between 40 to 60%. Figure 1. shows the clock generation block diagram. The X2 bit is validated on the XTAL1 ÷ 2 rising edge to avoid glitches when switching from the X2 to the STD mode. Figure 2 shows the mode switching waveforms.
Figure 1. Clock CPU Generation Diagram
Figure 2. Mode Switching Waveforms (STD mode). Setting this bit activates the X2 feature (X2 Mode). ating an interrupt every 20 ms will then generate an interrupt every 10 ms.
4134C–8051–09/04 Registers Table 1. CKCON0 Register
- This control bit is validated when the CPU clock bit X2 is set; when X2 is low, this bit
The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. PCAX2 Programmable Counter Array clock (1) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. T1X2 Timer1 Clock (1) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. T0X2 Timer0 Clock (1) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. CPU Clock Clear to select 12 clock periods per machine cycle (STD mode) for CPU and all the peripherals. Set to select 6 clock periods per machine cycle (X2 Mode) and to enable the individual peripherals "X2" bits.
4134C–8051–09/04 Table 2. CKCON1 Register
- This control bit is validated when the CPU clock bit X2 is set; when X2 is low, this bit
The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. SPIX2 SPI clock (1) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle.
4134C–8051–09/04 SFR Mapping The Special Function Registers (SFRs) of the AT8xC5103 belong to the following categories: C51 core registers: ACC, B, DPH, DPL, PSW, SP, AUXR1 I/O port registers: P1, P3, P4, P1M1, P1M2, P3M1, P3M2 Timer registers: TCON, TH0, TH1, TMOD, TL0, TL1 Power and clock control registers: CKCON0, CKCON1, PCON Interrupt system registers: IE, IE1, IPL0, IPL1, IPH0, IPH1 SPI: SPCON, SPSTA, SPDAT PCA: CCAP0L, CCAP1L, CCAP2L, CCAP3L, CCAP4L, CCAP0H, CCAP1H, CCAP2H, CCAP3H, CCAP4H, CCAPM0, CCAPM1, CCAPM2, CCAPM3, CCAPM4, CL, CH, CMOD, CCON
Table 3. SFR Addresses and Reset Values
4134C–8051–09/04 Ports The AT8xC5103 has 3 I/O ports, port 1, port 3 and port 4. Except RST, and port 4, all port 1 and port 3 I/O port pins on the AT8xC5103 may be software configured to one of four types on a bit-by-bit basis, as shown in Table 2 These are: quasi-bi-directional (standard 80C51 port outputs), push-pull, open drain, and input only. Two configuration registers for each port choose the output type for each port pin. Port Types Quasi-Bi-directional Output Configuration The default port output configuration for standard AT8xC5103 I/O ports is the quasi-bi- directional output that is common on the 80C51 and most of its derivatives. This output type can be used as both an input and output without the need to reconfigure the port. This is possible because when the port outputs a logic high, it is weakly driven, allowing an external device to pull the pin low. When the pin is pulled low, it is driven strongly and able to sink a fairly large current. These features are somewhat similar to an open drain output except that there are three pull-up transistors in the quasi-bi-directional output that serve different purposes. One of these pull-ups, called the ‘very weak’ pull-up, is turned on whenever the port latch for the pin contains a logic 1. The very weak pull-up sources a very small current that will pull the pin high if it is left floating. A second pull- up, called the ‘weak’ pull-up, is turned on when the port latch for the pin contains a logic 1 and the pin itself is also at a logic 1 level. This pull-up provides the primary source cur- rent for a quasi-bi-directional pin that is outputting a 1. If a pin that has a logic 1 on it is pulled low by an external device, the weak pull-up turns off, and only the very weak pull- up remains on. In order to pull the pin low under these conditions, the external device has to sink enough current to overpower the weak pull-up and take the voltage on the port pin below its input threshold. The third pull-up is referred to as the ‘strong’ pull-up. This pull-up is used to speed up low-to-high transitions on a quasi-bi-directional port pin when the port latch changes from a logic 0 to a logic 1. When this occurs, the strong pull-up turns on for a brief time, two CPU clocks, in order to pull the port pin high quickly. Then it turns off again. The quasi-bi-directional port configuration is shown in Figure 3. PxM1.y BIt PxM2.y Bit Port Output Mode Quasi bi-directional Push-pull Input Only (High Impedance) Open Drain
Figure 3. Quasi-Bi-directional Output mode. The open drain port configuration is shown in Figure 4. Figure 4. Open Drain Output Figure 5. Push-pull Output
2 CPU
4134C–8051–09/04 Input Only Configuration The input only configuration is a pure input with neither pull-up nor pull-down. The input only configuration is shown in Figure 6. Figure 6. Input Only Table 4. P1M1 Register Table 5. P1M2 Register P1M1.x Port Output configuration Bit See Table 2 for configuration definition P1M2.7 P1M2.6 P1M2.5 P1M2.4 P1M2.3 P1M2.2 P1M2.1 P1M2.0 Bit Number Bit Mnemonic P1M2.x Port Output configuration bit See Table 2 for configuration definition
4134C–8051–09/04 Table 6. P3M1 Register Table 7. P3M2 Register P3M1.x Port Output configuration bit See Table 2 for configuration definition P3M2.7 P3M2.6 P3M2.5 P3M2.4 P3M2.3 P3M2.2 P3M2.1 P3M2.0 Bit Number Bit Mnemonic P3M2.x Port Output configuration bit See Table 2 for configuration definition
4134C–8051–09/04 Dual-data Pointer Register (DPTR) The additional data pointer can be used to speed up code execution and reduce code size in a number of ways. The dual DPTR structure is a way by which the device will specify the address of an external data memory location. There are two 16-bit DPTR registers that address the external memory, and a single bit called DPS = AUXR1/bit0 (see Table 8) that allows the program code to switch between them (Refer to Figure 7). Figure 7. Use of Dual-data Pointer Table 8. AUXR1: Auxiliary Register 1
- User software should not write 1s to reserved bits. These bits may be used in future
Reserved(1) The value read from this bit is indeterminate. Do not set this bit. always stuck at 0 Reserved The value read from this bit is indeterminate. Do not set this bit. DPS Data Pointer Selection Clear to select DPTR0. Set to select DPTR1.
4134C–8051–09/04 Application Software can take advantage of the additional data pointers to both increase speed and reduce code size, for example, block operations (copy, compare, search...) are well served by using one data pointer as a ’source’ pointer and the other one as a "destina- tion" pointer. ASSEMBLY LANGUAGE ; Block move using dual data pointers ; Destroys DPTR0, DPTR1, A and PSW ; note: DPS exits opposite of entry state ; unless an extra INC AUXR1 is added 00A2 AUXR1 EQU 0A2H 0000 909000MOV DPTR,#SOURCE ; address of SOURCE 0003 05A2 INC AUXR1 ; switch data pointers 0005 90A000 MOV DPTR,#DEST ; address of DEST 0008 LOOP: 0008 05A2 INC AUXR1 ; switch data pointers 000A E0 MOVX A,@DPTR ; get a byte from SOURCE 000B A3 INC DPTR ; increment SOURCE address 000C 05A2 INC AUXR1 ; switch data pointers 000E F0 MOVX @DPTR,A ; write the byte to DEST 000F A3 INC DPTR ; increment DEST address 0010 70F6JNZ LOOP ; check for 0 terminator 0012 05A2 INC AUXR1 ; (optional) restore DPS INC is a short (2 bytes) and fast (12 clocks) way to manipulate the DPS bit in the AUXR1 SFR. However, note that the INC instruction does not directly force the DPS bit to a par- ticular state, but simply toggles it. In simple routines, such as the block move example, only the fact that DPS is toggled in the proper sequence matters, not its actual value. In other words, the block move routine works the same whether DPS is “0” or “1” on entry. Observe that without the last instruction (INC AUXR1), the routine will exit with DPS in the opposite state.
selected at a time by the Master for a transmission. A high level on the SS pin puts the MISO line of a Slave SPI in a high-impedance state. The device is configured as a Master and the SSDIS control bit in SPCON is set. the SPSTA will never be set (1). that the Master uses the SS pin to select the communicating Slave device. Clearing SSDIS control bit does not clear MODF. this mode, the SS is used to start the transmission. Table 9. SPI Master Baud Rate Selection
Figure 10. Full-Duplex Master-Slave Interconnection SCK. Simultaneously, another byte shifts in from the Slave on the Master’s MISO pin. the transmission is established again, the data present in the SPDAT is resent. device must be set to “0”. SS must remain low until the transmission is complete. sampled and the edges on which the output data are shifted (Figure 11 and Figure 12). the Master SPI should be configured before the Slave SPI. The SPI module should be configured as a Slave before it is enabled (SPEN set). Before writing to the CPOL and CPHA bits, the SPI should be disabled (SPEN = "0").
The following flags in the SPSTA signal SPI error conditions. An SPI receiver/error CPU interrupt request is generated. The SPEN bit in SPCON is cleared. This disable the SPI. The MSTR bit in SPCON is cleared. when the SS signal becomes “0”. bit in the SPCON register and therefore making the SS pin as a general-purpose I/O pin. inal set state after the MODF bit has been cleared. done during a transmit sequence. WCOL does not cause an interruption, and the transfer continues uninterrupted. last cleared. A read of the SPDAT returns this byte. All others bytes are lost. This condition is not detected by the SPI peripheral. by writing 0 to SPEN bit (reset of the SPI state machine). Table 10. SPI Interrupts has been completed. SPIF bit generates transmitter CPU interrupt requests. Figure 14 gives a logical view of the above statements.
4134C–8051–09/04 Figure 14. SPI Interrupt Requests Generation functions. These registers are describes in the following paragraphs. Table 11 describes this register and explains the use of each bit. Table 11. SPCON Register: Serial Peripheral Control Register - SPCON (S:C3h) Bit with SPR1 and SPR0 define the clock rate SPEN R/W Serial Peripheral Enable Clear to disable the SPI interface (internal reset of the SPI) Set to enable the SPI interface SSDIS R/W SS Disable Clear to enable SS in both Master and Slave Modes Set to disable SS in both Master and Slave Modes. In Slave Mode, this bit has no effect if CPHA = "0" MSTR R/W Serial Peripheral Master Clear to configure the SPI as a Slave Set to configure the SPI as a Master CPOL R/W Clock Polarity Clear to have the SCK set to ‘0’ in idle state Set to have the SCK set to ’1’ in idle low CPHA R/W Clock Phase Clear to have the data sampled when the SPSCK leaves the idle state (see CPOL) Set to have the data sampled when the SPSCK returns to idle state (see CPOL) SPR1 R/W Serial Peripheral Rate (SPR2:SPR1:SPR0) 000: N.A. 001: FCLK PERIPH /4 010: FCLK PERIPH /8 011: FCLK PERIPH /16
4134C–8051–09/04 Reset Value = 00010100b Serial Peripheral Status Register (SPSTA) The Serial Peripheral Status Register contains flags to signal the following conditions: Data transfer complete Write collision Inconsistent logic level on SS pin (mode fault error) Table 12 describes the SPSTA register and explains the use of every bit in the register. Reset Value = 00X0XXXXb SPR0 R/W 100: FCLK PERIPH /32 101: FCLK PERIPH /64 110: FCLK PERIPH /128 111: Don’t Use Bit Number Bit Mnemonic R/W Mode Table 12. SPSTA: Serial Peripheral Status and Control Register - SPSTA (S:C4h) Clear by hardware to indicate data transfer is in progress or has been approved by a clearing sequence. Set by hardware to indicate that the data transfer has been completed. Cleared by hardware to indicate that no collision has occurred or has been approved by a clearing sequence. Set by hardware to indicate that a collision has been detected. Set by hardware when SS is deasserted before the end of a received data. Cleared by disabling the SPI (clearing SPEN bit in SPCON). The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit.
Table 13. SPDAT (S:C5h): Serial Peripheral Data Register
cascade (see Figure 16). The selected input increments TL1 register. Timer 1 when TR1 run control bit is not available i.e. when Timer 0 is in Mode 3. interrupts are globally enabled by setting EA bit in IE0 register. Figure 19. Timer Interrupt System
4134C–8051–09/04 Registers Table 14. TCON Register Cleared by hardware when processor vectors to interrupt routine. Set by hardware on Timer/Counter overflow, when Timer 1 register overflows. TR1 Timer 1 Run Control Bit Clear to turn off Timer/Counter 1. Set to turn on Timer/Counter 1. TF0 Timer 0 Overflow Flag Cleared by hardware when processor vectors to interrupt routine. Set by hardware on Timer/Counter overflow, when Timer 0 register overflows. TR0 Timer 0 Run Control Bit Clear to turn off Timer/Counter 0. Set to turn on Timer/Counter 0. IE1 Interrupt 1 Edge Flag Cleared by hardware when interrupt is processed if edge-triggered (see IT1). Set by hardware when external interrupt is detected on INT1# pin. IT1 Interrupt 1 Type Control Bit Clear to select low level active (level triggered) for external interrupt 1 (INT1#). Set to select falling edge active (edge triggered) for external interrupt 1. IE0 Interrupt 0 Edge Flag Cleared by hardware when interrupt is processed if edge-triggered (see IT0). Set by hardware when external interrupt is detected on INT0# pin. IT0 Interrupt 0 Type Control Bit Clear to select low level active (level triggered) for external interrupt 0 (INT0#). Set to select falling edge active (edge triggered) for external interrupt 0.
4134C–8051–09/04 Reset Value = 0000 0000b Table 16. TH0 Register Table 15. TMOD Register Timer 1 Gating Control Bit Clear to enable Timer 1 whenever TR1 bit is set. Set to enable Timer 1 only while INT1# pin is high and TR1 bit is set. C/T1# Timer 1 Counter/Timer Select Bit Clear for Timer operation: Timer 1 counts the divided-down system clock. Set for Counter operation: Timer 1 counts negative transitions on external pin T1. M11 Timer 1 Mode Select Bits M11 M01 Operating Mode Mode 0: 8-bit Timer/Counter (TH1) with 5-bit prescaler (TL1). Mode 1: 16-bit Timer/Counter. Mode 2: 8-bit auto-reload Timer/Counter (TL1). Reloaded from TH1 at overflow. Mode 3: Timer 1 halted. Retains count. M01 GATE0 Timer 0 Gating Control Bit Clear to enable Timer 0 whenever TR0 bit is set. Set to enable Timer/Counter 0 only while INT0# pin is high and TR0 bit is set. C/T0# Timer 0 Counter/Timer Select Bit Clear for Timer operation: Timer 0 counts the divided-down system clock. Set for Counter operation: Timer 0 counts negative transitions on external pin T0. M10 Timer 0 Mode Select Bit M10 M00 Operating Mode Mode 0: 8-bit Timer/Counter (TH0) with 5-bit prescaler (TL0). Mode 1: 16-bit Timer/Counter. Mode 2: 8-bit auto-reload Timer/Counter (TL0). Reloaded from TH0 at overflow. Mode 3: TL0 is an 8-bit Timer/Counter. TH0 is an 8-bit Timer using Timer 1’s TR0 and TF0 bits. M00 Bit Number Bit Mnemonic 7:0 High Byte of Timer 0
4134C–8051–09/04 Table 17. TL0 Register Table 18. TH1 Register Table 19. TL1 Register 7:0 Low Byte of Timer 0 Bit Number Bit Mnemonic 7:0 High Byte of Timer 1 Bit Number Bit Mnemonic 7:0 Low Byte of Timer 1
4134C–8051–09/04 Power Management Table 20. PCON Register the logical states they had at the time Idle was activated. lowing the instruction that put the device into idle. service routine can examine the flag bits. machine cycles (24 oscillator periods) to complete the reset. The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. GF1 General-purpose Flag Cleared by user for general purpose usage. Set by user for general purpose usage. GF0 General-purpose Flag Cleared by user for general purpose usage. Set by user for general purpose usage. PD Power-Down Mode Bit Cleared by hardware when reset occurs. Set to enter Power-down Mode. IDL Idle Mode Bit Cleared by hardware when interrupt or reset occurs. Set to enter Idle Mode.
active long enough for the oscillator to restart and stabilize. interrupt must be enabled and configured as level or edge sensitive interrupt input. input is released. In this case the higher priority interrupt service routine is executed. one following the instruction that put AT8xC5103 into power-down mode. Figure 20. Power-Down Exit Waveform external interrupt does no affect the SFRs. Table 21 shows the state of ports during idle and power-down modes.
- Port 0 can force a 0 level. A ‘one’ will leave port floating.
Table 21. State of Ports(1)
4134C–8051–09/04 Programmable Counter Array (PCA) The PCA provides more timing capabilities with less CPU intervention than the standard timer/counters. Its advantages include reduced software overhead and improved accu- racy. The PCA consists of a dedicated timer/counter which serves as the time base for an array of five compare/capture modules. Its clock input can be programmed to count any one of the following signals: Oscillator frequency ÷ 12 (÷ 6 in X2 Mode) Oscillator frequency ÷ 4 (÷ 2 in X2 Mode) Timer 0 overflow External input on ECI (P1.2) Each compare/capture modules can be programmed in any one of the following modes: Rising and/or falling edge capture, Software timer High-speed output Pulse width modulator Module 4 can also be programmed as a watchdog timer. When the compare/capture modules are programmed in the capture mode, software timer, or high speed output mode, an interrupt can be generated when the module exe- cutes its function. All five modules and the PCA timer overflow share one interrupt vector. The PCA timer/counter and compare/capture modules share Port 1 for external I/O. These pins are listed below. If the port is not used for the PCA, it can still be used for standard I/O. The PCA timer is a common time base for all five modules (See Figure 21). The timer count source is determined from the CPS1 and CPS0 bits in the CMOD SFR (see Table 21) and can be programmed to run at: 1/12 the oscillator frequency (or 1/6 in X2 Mode) 1/4 the oscillator frequency (or 1/2 in X2 Mode) The Timer 0 overflow The input on the ECI pin (P1.2) PCA Component External I/O Pin 16-bit Counter P1.2/ECI 16-bit Module 0 P1.3/CEX0 16-bit Module 1 P1.4/CEX1 16-bit Module 2 P1.5/CEX2 16-bit Module 3 P1.6/CEX3 16-bit Module 4 P1.7/CEX4
Figure 21. PCA Timer/Counter Table 22. CMOD: PCA Counter Mode Register Watchdog Timer Enable: WDTE = 0 disables Watchdog Timer function on PCA Module 4. WDTE = 1 enables it. reserved bit is indeterminate. PCA Count Pulse Select bit 1. PCA Count Pulse Select bit 0. Internal clock fosc/12 (Or fosc/6 in X2 Mode). Internal clock fosc/4 (Or fosc/2 in X2 Mode).
The CIDL bit which allows the PCA to stop during idle mode. The WDTE bit which enables or disables the watchdog function on module 4. the CCON SFR) to be set when the PCA timer overflows. (CF) and each module (Refer to Table 23). only be cleared by software. also can only be cleared by software. Table 23. CCON: PCA Counter Control Register The watchdog timer function is implemented in module 4 (See Figure 24). The PCA interrupt system is shown in Figure 22. can only be cleared by software. by software to turn the PCA counter off.
Figure 22. PCA Interrupt System In addition, module 4 can be used as a Watchdog Timer. registers contain the bits that control the mode that each module will operate in. compare occurs in the associated module. PWM (CCAPMn.1) enables the pulse width modulation mode. enabled and a capture will occur for either transition.
Table 24 shows the CCAPMn settings for the various PCA functions. Table 24. CCAPMn: PCA Modules Compare/Capture Control Registers Table 25. PCA Module Modes (CCAPMn Registers) Enable Comparator. ECOMn = 1 enables the comparator function. Capture Positive, CAPPn = 1 enables positive edge capture. Capture Negative, CAPNn = 1 enables negative edge capture. register causes the CCFn bit in CCON to be set, flagging an interrupt. register causes the CEXn pin to toggle.
Table 26. CCAPnH: PCA Modules Capture/Compare Registers High Table 27. CCAPnL: PCA Modules Capture/Compare Registers Low Table 28. CH: PCA Counter High Table 29. CL: PCA Counter Low
Figure 23. PCA Capture Mode
SFR) and the ECCFn (CCAPMn SFR) bits for the module are both set (see Figure 24). Figure 24. PCA Compare Mode and PCA Watchdog Timer other/wise an unwanted match could happen. Writing to CCAPnH will set the ECOM bit. ECOM bit can still be controlled by accessing to CCAPMn register.
each time a match occurs between the PCA counter and the module's capture registers. must be set (see Figure 25). A prior write must be done to CCAPnL and CCAPnH before writing the ECOMn bit. Figure 25. PCA High Speed Output Mode other/wise an unwanted match could happen. ECOM bit can still be controlled by accessing to CCAPMn register. modules will have the same frequency of output because they all share the PCA timer. the module's CCAPMn register must be set to enable the PWM mode.
Figure 26. PCA PWM Mode Periodically change the compare value so it will never match the PCA timer. cations the first solution is the best option. This watchdog timer won’t generate a reset out on the reset pin.
interrupts (timers 0, 1), PCA and SPI. These interrupts are shown in Figure 27.. Figure 27. Interrupt Control System global disable bit, which must be cleared to disable all interrupts at once. levels associated with each combination.
Table 30. Priority Level Bit Values
4134C–8051–09/04 Table 31. IE0 Register Clear to disable all interrupts. Set to enable all interrupts. If EA=1, each interrupt source is individually enabled or disabled by setting or clearing its interrupt enable bit. EC PCA Interrupt Enable Clear to disable the PCA interrupt. Set to enable the PCA interrupt. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. ET1 Timer 1 overflow interrupt Enable bit Clear to disable timer 1 overflow interrupt. Set to enable timer 1 overflow interrupt. EX1 External Interrupt 1 Enable bit Clear to disable external interrupt 0. Set to enable external interrupt 0. ET0 Timer 0 Overflow Interrupt Enable bit Clear to disable timer 0 overflow interrupt. Set to enable timer 0 overflow interrupt. EX0 External Interrupt 0 Enable bit Clear to disable external interrupt 0. Set to enable external interrupt 0.
4134C–8051–09/04 Table 32. IE1 Register The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. ESPI SPI Interrupt Enable bit Clear to disable the SPI interrupt. Set to enable the SPI interrupt. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit.
4134C–8051–09/04 Table 33. IPL0 Register The value read from this bit is indeterminate. Do not set this bit. PPCL PCA Counter Interrupt Priority bit Refer to PPCH for priority level Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. PT1L Timer 1 Overflow Interrupt Priority bit Refer to PT1H for priority level. PX1L External Interrupt 1Priority bit Refer to PX1H for priority level. PT0L Timer 0 Overflow Interrupt Priority bit Refer to PT0H for priority level. PX0L External Interrupt 0 Priority bit Refer to PX0H for priority level.
4134C–8051–09/04 Table 34. IPL1 Register The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. PSPIL SPI Interrupt Priority Level Less Significant bit. Refer to PSPIH for priority level. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit.
4134C–8051–09/04 Table 35. IPH0 Register The value read from this bit is indeterminate. Do not set this bit. PPCH PCA Counter Interrupt Priority Level Most Significant bit PPCH PPCL Priority level Lowest Highest priority Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. PT1H Timer 1 overflow interrupt Priority High bit PT1H PT1L Priority Level Lowest Highest PX1H External interrupt 1Priority High bit PX1H PX1L Priority Level Lowest Highest PT0H Timer 0 overflow interrupt Priority High bit PT0H PT0L Priority Level Lowest Highest PX0H External interrupt 0 Priority High bit PX0H PX0L Priority Level Lowest Highest
4134C–8051–09/04 Table 36. IPH1 Register The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. PSPIH SPI Interrupt Priority Level Most Significant bit PSPIH PSPIL Priority level Lowest Highest Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit.
4134C–8051–09/04 Hardware Byte: Lock bit Table 37. Hardware Byte (HSB) provided. If lock bit program, no read operation can be done, only CRC check. This security bit is accessible only with hardware programmer. User Program EPROM Lock Bit Programmed (0) to protect memory from external read Unprogrammed (1), read or write is allowed 5:0 Reserved Do not write these bits
4134C–8051–09/04
Electrical Characteristics
Absolute Maximum Ratings(1) Power Consumption Measurement Since the introduction of the first C51 device, every manufacturer made operating ICC measurements under reset, which made sense for the designs were the CPU was run- ning under reset. In our new devices, the CPU is no more active during reset, so the power consumption is very low but is not really representative of what will happen in the customer system. That’s why, while keeping measurements under Reset, we present a new way to measure the operating ICC: Using an internal test ROM, the following code is executed: Label: SJMP Label (80 FE) Ports 1 and 4 are disconnected, RST = VCC, XTAL2 is not connected and XTAL1 is driven by the clock. This is much more representative of the real operating ICC. Ambiant Temperature Under Bias: *NOTICE: Stresses at or above those listed under “Abso- lute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability.
Table 38. DC Parameters
0.7 VCC
4134C–8051–09/04
Ordering Information
(Bytes) Supply Voltage Temperature Range Max Frequency Packing Package AT87C5103-IBSIL 12K OTP 3.0 - 5.5V Industrial
16 MHz
3.0 - 5.5V Industrial 3.0 - 5.5V Industrial 3.0 - 5.5V Industrial 3.0 - 5.5V Industrial 3.0 - 5.5V Industrial 3.0 - 5.5V Industrial 3.0 - 5.5V Industrial 3.0 - 5.5V Automotive 3.0 - 5.5V Automotive 3.0 - 5.5V Automotive 3.0 - 5.5V Automotive 3.0 - 5.5V Automotive 3.0 - 5.5V Automotive 3.0 - 5.5V Automotive 3.0 - 5.5V Automotive
4134C–8051–09/04 Package Drawings SSOP 16 Leads
4134C–8051–09/04 SSOP 24 Leads
4134C–8051–09/04 Datasheet Revision History for AT8C5103 Changes from 4134A- 05/02 to 4134B-04/03 Changed the Reset Pulldown resistor for ROM version (See AC/DC parameters). Changes from 4134B- 04/03 to 4134C-09/04 Changed the Section “Hardware Byte: Lock bit”, page 54.
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