T83C5121_06 ATMEL | Alldatasheet
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Features
80C51 Core – 12 or 6 Clocks per Instruction (X1 and X2 Modes) – 256 Bytes Scratchpad RAM – Dual Data Pointer – Two 16-bit Timer/Counters: T0 and T1 T83C5121 with 16 Kbytes Mask ROM T85C5121 with 16 Kbytes Code RAM T89C5121 with 16 Kbytes Code RAM and 16 Kbytes EEPROM On-chip Expanded RAM (XRAM): 256 Bytes Versatile Host Serial Interface – Full-duplex Enhanced UART (EUART) with Dedicated Baud Rate Generator (BRG): Most Standard Speeds up to 230K bits/s at 7.36 MHz – Output Enable Input – Multiple Logic Level Shifters Options (1.8V to V CC) – Automatic Level Shifter Option Multi-protocol Smart Card Interface – Certified with Dedicated Firmware According to ISO 7816, EMV2000, GIE-CB, GSM 11.12V and WHQL Standards – Asynchronous Protocols T = 0 and T = 1 with Direct and Inverse Modes – Baud Rate Generator Supporting All ISO7816 Speeds up to D = 32/F = 372 – Parity Error Detection and Indication – Automatic Character Repetition on Parity Errors – Programmable Timeout Detection – Card Clock Stop High or Low for Card Power-down Mode – Support Synchronous Card with C4 and C8 Programmable Outputs – Card Detection and Automatic De-activation Sequence – Step-up/down Converter with Programmable Voltage Output: 5V, 3V (± 8% at 60 mA) and 1.8V (±8% at 20 mA) – Direct Connection to Smart Card Terminals: Short Circuit Current Limitation Logic Level Shifters 4 kV ESD Protection (MIL/STD 833 Class 3) Alternate Card Support with CLK, I/O and RST According to GSM 11.12V Standard 2x I/O Ports: 6 I/O Port1 and 8 I/O Port3 2x LED Outputs with Programmable Current Sources: 2, 4, or 10 mA Hardware Watchdog Reset Output Includes – Hardware Watchdog Reset – Power-on Reset (POR) – Power-fail Detector (PFD) 4-level Priority Interrupt System with 7 Sources 7.36 to 16 MHz On-chip Oscillator with Clock Prescaler Absolute CPU Maximal Frequency: 16 MHz in X1 mode, 8MHz in X2 mode Idle and Power-down Modes Voltage Operation: 2.85V to 5.4V Low Power Consumption – 8 mA Operating Current (at 5.4V and 3.68 MHz) – 150 mA Maximum Current with Smart Card Power-on (at 16 MHz X1 Mode) –3 0 μA Maximum Power-down Current at 3.0V (without Smart Card) –1 0 0 μA Maximum Power-down Current at 5.4V (without Smart Card) Temperature Range – Commercial: 0 to +70 °C Operating Temperature – Industrial: -40 to +85 °C Operating Temperature Packages – SSOP24 –Q F N 3 2 – PLCC52 8-bit Microcontroller with Multi- protocol Smart Card Interface T83C5121 T85C5121 T89C5121 AT83C5121 AT85C5121 AT89C5121
single chip 8-bit microcontrollers. pointer, 2 programmable LED current sources (2-4-10 mA) and a hardware Watchdog. nal serial EEPROM or from R232 interface. Figure 1. Block Diagram
- Alternate function of Port 3
- Only for the Code RAM version
6 I/Os
8 I/Os
Figure 3. QFN32 Pinout
Figure 4. PLCC52 Pinout
Signals All the T8xC5121 signals are detailed in Table 1. The port structure is described in Section “Port Structure Description”. Table 1. Ports Description P1.0 is a bi-directional I/O port . configuration can be selected).
P3.0 is a bi-directional I/O port with internal pull-ups. OE active at low or high level depending of PMSOEN bits in SIOCON Reg. P3.1 is a bi-directional I/O port with internal pull-ups. P3.2 is a bi-directional I/O port with internal pull-ups. INT1 input set OEIT in ISEL Register, IE1 in the TCON register. P3.3 is a bi-directional I/O port with internal pull-ups. Table 1. Ports Description (Continued)
P3.4 is a bi-directional I/O port with internal pull-ups. P3.5 is a bi-directional I/O port with internal pull-ups.
not the oscillator is running. returns the chip to normal operation. If an external oscillator is used, its output is connected to this pin. If an external oscillator is used, XTAL2 may be left unconnected. VCC is used to power the internal voltage regulators and internal I/O’s. the current for the pump charge of the DC/DC converter. CVCC is the programmable voltage output for the Card interface. It must be connected to an external decoupling capacitor. an external decoupling capacitor. pins. It must be connected to an external decoupling capacitor. or it can be connected to an external voltage reference. CVSS is used to sink high shunt currents from the external coil.
during reset and cannot be dynamically changed during operation.
4164G–SCR–07/06 Port Structure
Description
The different ports structures are described as follows. Quasi Bi-directional Output Configuration The default port output configuration for standard I/O ports is the quasi bi-directional out- put that is common on the 80C51 and most of its derivatives. This output type can be used as both an input and output without the need to reconfigure the port. This is possi- ble because when the port outputs a logic high, it is weakly driven, allowing an external device to pull the pin low. When the port outputs a logic low state, it is driven strongly and able to sink a fairly large current. These features are somewhat similar to an open drain output except that there are three pull-up transistors in the quasi bi-directional out- put that serve different purposes. One of these pull-ups, called the weak pull-up, is turned on whenever the port latch for the pin contains a logic 1. The weak pull-up sources a very small current that will pull the pin high if it is left floating. A second pull- up, called the medium pull-up, is turned on when the port latch for the pin contains a logic 1 and the pin itself is also at a logic 1 level. This pull-up provides the primary source current for a quasi bi-directional pin that is outputting a 1. If a pin that has a logic 1 on it is pulled low by an external device, the medium pull-up turns off, and only the weak pull-up remains on. In order to pull the pin low under these conditions, the external device has to sink enough current to overpower the medium pull-up and take the voltage on the port pin below its input threshold. Figure 5. Quasi Bi-directional Output Configuration needed from a port output. The Push-pull port configuration is shown in Figure 5.
2 CPU
Figure 6. Push-pull Output Configuration LED Output Configuration The input only configuration is shown in Figure 7. Figure 7. LED Source Current Configuration and LEDCON1 registers before switching the led on by writing a logical 0 in Port latch.
4164G–SCR–07/06 SFR Mapping The Special Function Registers (SFR) of the T8xC5121 belongs to the following categories: C51 core registers: ACC, B, DPH, DPL, PSW, SP I/O port registers: P0, P1, P2, P3 Timer 0 registers: TCON, TH0, TH1, TMOD, TL0, TL1 Serial I/O port registers: SADDR, SADEN, SBUF, SCON, BRL, BDRCON Power and clock control registers: PCON, CKRL, CKCON0, CKCON1, DCCKPS Interrupt system registers: IE0, IPL0, IPH0, IE1,IPL1, IPH1, ISEL Watchdog Timer 0: WDTRST, WDTPRG Others: AUXR, AUXR1, RCON Smart Card Interface: SCSR, SCCON/SCETU0, SCISR/SCETU1, SCIER/SCIIR, SCTBUF/SCRBUF , SCGT0/SCWT0, SCGT1/SCWT1, SCICR/SCWT2 Port configuration: SIOCON, LEDCON
Table 2. SFR Addresses and Reset Values
1 SCICR *
0 SCCON *
0 S C I S R *
0 S C I I R *
20 PCON
Figure 9. Power-Up and Steady-state Conditions Monitored when VDD reaches a voltage condition which is out of the specification. at the power-up. The circuit leaves the RESET mode. value for the microcontroller. An internal RESET is set.
4164G–SCR–07/06 Power Monitoring and Clock Management For applications where power consumption is a critical factor, three power modes are provided: Idle mode Power-down mode Clock Management (X2 feature and Clock Prescaler) 3V Regulator Modes (pulsed or not pulsed) Idle Mode An instruction that sets PCON.0 causes the last instruction to be executed before going into the Idle mode. In the Idle mode, the internal clock signal is gated off to the CPU, but not to the interrupt, Timer 0, and Serial Port functions. The CPU status is preserved in its entirety: the Stack Pointer, Program Counter, Program Status Word, Accumulator and all other registers maintain their data during Idle. The port pins hold the logical states they had at the time Idle was activated. ALE and PSEN hold at logic high levels. There are two ways to terminate the Idle. Activation of any enabled interrupt will cause PCON.0 to be cleared by hardware, terminat ing the Idle mode. The interrupt will be ser- viced, and following RETI the next instruction to be executed will be the one following the instruction that put the device into idle. The flag bit GF0 can be used to give an indication if an interrupt occurred during normal operation or during an Idle. For example, an instruction that activates Idle can also set one or both flag bits. When Idle is terminated by an interrupt, the interrupt service rou- tine can examine the flag bits. The other way of terminating the Idle mode is with a hardware reset. Since the clock oscillator is still running, the hardware reset needs to be held active for only two machine cycles (24 oscillator periods) to complete the reset. Power-down Mode Entering Power-down Mode To save maximum power, a Power-down mode can be invoked by software (refer to Table 3, PCON register). In Power-down mode, the oscillator is stopped and the instruction that invoked Power- down mode is the last instruction executed. The internal RAM and SFRs retain their value until the Power-down mode is terminated. VCC can be lowered to save further power. Either a hardware reset or an external interrupt can cause an exit from Power- down. To properly terminate Power-down, the reset or external interrupt should not be executed before VCC is restored to its normal operating level and must be held active long enough for the oscillator to restart and stabilize. Only external interrupts INT0 and INT1 are useful to exit from Power-down. For that, interrupt must be enabled and configured as level or edge sensitive interrupt input. Holding the pin low restarts the oscillator but bringing the pin high completes the exit as detailed in Figure 10. When both interrupts are enabled, the oscillator restarts as soon as one of the two inputs is held low and Power-Down exit will be completed when the first input will be released. In this case t he higher priority interrupt service routine is executed. Once the interrupt is serviced, the next instruction to be executed after RETI will be the one following the instruction that put it into Power-down mode. Exit from Power-down Mode Exiting from Power-down by external interrupt does not affect the SFRs and the internal RAM content.
and PRESIT Bit (ISEL.5) must be reset. Figure 10. Power-down Exit Waveform external interrupt does no affect the SFRs. must be disconnected by setting the LEDPD bit in the PCON Register (PCON 3). choose to select this low-power mode. The activation reference is the following. First select the Low-power mode by setting the LP bit in the AUXR Register (AUXR. The activation of Power-down can then be done.
and external fetches. During ALE disabling, ALE pin is weakly pulled high. Table 3. PCON Register accesses to SCON.6 are to SM1 bit. SCON.6 are to OVR bit. SCON is Serial Port Control register.
5 Reserved
4 Reserved
3 LEDPD
medium pull-up is disconnected. Cleared by hardware when an interrupt or reset occurs. Set to activate the Power-down mode. If IDL and PD are both set, PD takes precedence. Cleared by hardware when an interrupt or reset occurs. Set to activate the Idle mode. If IDL and PD are both set, PD takes precedence.
Table 4. AUXR Register The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. Clear to map XRAM datas in internal XRAM memory. Set to map XRAM datas in external XRAM memory. Clear to restore ALE operation during internal fetches. Set to disable ALE operation during internal fetches.
Table 5. IE0 Register Clear to disable all interrupts. Set to enable all interrupts. clearing its interrupt enable bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. Clear to disable serial port interrupt. Set to enable serial port interrupt. Clear to disable Timer 1 overflow interrupt. Set to enable Timer 1 overflow interrupt. Clear to disable external interrupt 1. Set to enable external interrupt 1. Clear to disable Timer 0 overflow interrupt. Set to enable Timer 0 overflow interrupt. Clear to disable external interrupt 0. Set to enable external interrupt 0.
Table 6. ISEL Register
7 CPLEV
The value read from this bit is indeterminate. Do not set this bit.
5 PRESIT
3 OELEV
Set this bit to indicate that high level is active. Clear this bit to indicate that low level is active.
1 PRESEN
Clear to disable the card presence detection interrupt coming from SCIB. Set to enable the card presence detection interrupt coming from SCIB. Clear to disable the RxD interrupt.
Figure 11. Clock Generation Diagram
Divides frequency crystals by 2 (cheaper crystals) while keeping same CPU power. Increases CPU power by 2 while keeping same crystal frequency. by the CPU core and the peripherals. bypassed, the signals on XTAL1 must have a cyclic ratio from 40 to 60%. Figure 12. Mode Switching Waveforms clock periods per instruction to 6 clock periods and vice versa. periods per peripheral clock cycle). These bits are active only in X2 mode. Advantage of the X2 Features in TS80C51 Microcontroller?".
Table 7. Examples of Factors Clock Prescaler Register This register is used to reload the clock prescaler of the CPU and peripheral clock. Table 8. CKRL Register The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit.
Table 9. CKCON0 Register Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. Clear to select 6 clock periods per peripheral clock cycle. Clear to select 6 clock periods per peripheral clock cycle. individual peripherals "X2" bits.
Table 10. CKCON1 Register Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle.
clock path and the second constraint is solved with the use of a prescaler. Figure 13. Functional Block Diagram Clock Control Register This register is used to reload the clock prescaler of the DC/DC converter clock. Table 11. DCCKPS Register The prescaler factor must be chosen to match the requirement range which is 4MHz. Table 12. Examples of Factors
4164G–SCR–07/06
4164G–SCR–07/06 Smart Card Interface Block (SCIB) Introduction The SCIB provides all signals to directly interface a smart card. Compliance with the ISO7816, EMV’2000, GSM and WHQL standards has been certified. Both synchronous (e.g. memory card) and asynchronous smart cards (e.g. micropro- cessor card) are supported. The component supplies the different voltages requested by the smart card. The power-off sequence is directly managed by the SCIB. The card presence switch of the smart card connector is used to detect card insertion or card removal. In case of card removal, the SCIB de-activates the smart card using the de-activation sequence. An interrupt can be generated when a card is inserted or removed. Any malfunction is reported to the microcontroller (interrupt + control register). The different operating modes are configured by internal registers. Main Features Support of ISO/IEC7816 Character mode 1 transmit buffer + 1 receive buffer 11 bits ETU counter 9 bits guard time counter 24 bits waiting time counter Auto-character repetition on error signal detection in transmit mode Auto-error signal generation on parity error detection in receive mode Power-on and power-off sequence generation Manual mode to directly drive the card I/O
Block Diagram The Smart Card Interface Block diagram is shown in Figure 14. Figure 14. SCIB Block Diagram Functional Description The architecture of the Smart Card Interface Block is detailed below. Barrel Shifter It allows the translation between 1 bit serial data and 8 bits parallel data. the shifter at the end of the character transmission. value in order to manage both direct and inverse ISO7816-3 convention. Coupled with the barrel shifter there is a parity checker and generator. They act as buffers to relieve the CPU of timing constraints.
gives time slots corresponding to the character frame. It is enabled only in UART mode. is given to the transmission. shifter, in fact, it generates the enable signal of the barrel shifter. also equal to 10*(n+1/2) clock cycles. the ETU duration to 12 clock cycles. The result will be a full character duration (10 bits) equal to 11.5 clock cycles. It is 9 bits wide and is incremented at the ETU rate. Figure 15. Guard Time Counter
Figure 16. Waiting Time Counter The counter is loaded, if WTEN = 0, during the write of SCWT2 register. SCWT1 and SCWT2 registers to the WT counter. character. The reload of SCWT[2-0] with the new value occurs with WTEN = 1. After a time out of the counter in UART mode, the restart is done as in manual mode. ing edge of the next character is loaded in the SCWT2, SCWT1, SCWT0 registers. loaded in the same registers. The maximum time between two consecutive start bit is WT[23:0] * ETU.
Figure 17. T = 0 Mode Figure 18. T = 1 Mode To be able to power-on the SCIB, the card presence is mandatory. Figure 19. SCI Deactivation Sequence after a Card Extraction
8 Clock Cycles
Figure 20. SCIB Interrupt Sources will be delayed after the read access. the Section “DC/DC Converter”. The Lowest significant byte register is implemented at the higher address.
Clock The Ck-ISO input must be in the range 1 - 5 MHz according to ISO7816. The ISO Clock diagram and the configuration examples are shown in Figure 20. Figure 21. Clock Diagram of the SCIB Block Table 13. Examples of Settings for Clocks Alternate Card A second card named "Alternate card" can be controlled. ALTKPS1 in SCSR Register are used to set this factor.
Figure 22. Alternate Card consumption (CPRESRES, bit 3 in PMOD0). In this case, an external resistor (typically 1 M Ω) must be externally tied to VCC. CPRES input can generate an interrupt (see Interrupt system section). The detection level can be selected. its registers. Table 15 shows the SCIB registers that are reseted and their reset values. Table 14. Reset Values for SCI Registers
4164G–SCR–07/06 DC/DC Converter The Smart Card supply voltage (C VCC) is generated by the integrated DC/DC converter. It is controlled by several registers: The register described in Section “SCICR Register” controls the CVCC voltage with bits CVcc0, CVcc1 The register described in Section “SCCON Register”, switches ON/OFF the DC/DC converter with bit CARDV CC After the selection of the card voltage (CVcc[1:0]), the CARV CC bit is used to switch on the DC\\DC converter. The CVccOK bit indicates that the card voltage is within the voltage range. It is mandatory to switch off the CV CC before entering in power-down mode.
4164G–SCR–07/06 Registers Description Table 15. SCICR Register SCICR (S:B6h, SCRS = 1) Smart Card Interface Control Register Reset Value = 0000 0000b 76543210 RESET CARDDET CVcc1 CVcc0 UART WTEN CREP CONV Bit Number Bit Mnemonic Description
7 RESET Reset
Set this bit to reset the SCIB and its configuration 6C A R D D E T Card presence detector sense Clear this bit to indicate the card presence detector is opened when no card is inserted (CPRES is high). Set this bit to indicate the card presence detector is closed when no card is inserted (CPRES is low). 5 - 4 CVcc[1:0] Card Voltage Selection: CVcc[1] CVcc[0] CVcc 000 V 0 1 1.8V 10 3 V 11 5 V 3U A R T Card UART selection Clear this bit to use the Card I/O bit to drive the Card I/O pin. Set this bit to use the Smart Card UART to drive the Card I/O pin. Also controls the Wait Time Counter as described in Section “Waiting Time Counter (WT)” 2W T E N Wait time counter enable Clear this bit to stop the counter and enable the load of the Wait Time counter hold registers. The hold registers are loaded with SCWT0, SCWT1 and SCWT2 values when SCWT2 is written. Set this bit to start the Wait Time counter. The counters stop when it reaches the timeout value. If the UART bit is set, the Wait Time counter automatically reloads with the hold registers whenever a start bit is sent or received.
1 CREP
Clear this bit to disable parity error detection and indication on the Card I/O pin in receive mode and to disable character repetition in transmit mode. Set this bit to enable parity error indication on the Card I/O pin in receive mode and to set automatic character repetition when a parity error is indicated in transmit mode. In receive mode, three times error indication is performed and the parity error flag is set after four times parity error detection. In transmit mode, up to three times character repetition is allowed and the parity error flag is set after five times (reset configuration, can be set at 4 using CREPSET bit in SCSR Register) consecutive parity error indication. 0C O N V ISO convention Clear this bit to use the direct convention: b0 bit (LSB) is sent first, the parity bit is added after b7 bit and a low level on the Card I/O pin represents a “0”. Set this bit to use the inverse convention: b7 bit (LSB) is sent first, the parity bit is added after b0 bit and a low level on the Card I/O pin represents a “1”.
Table 16. SCCON Register Clear this bit to use the CardClk bit (CARDCLK) to drive Card CLK pin. Set this bit to use XTAL signal to drive the Card CLK pin. The value read from this bit is indeterminate. Do not change this bit or write 0.
5 CARDC8
Clear this bit to drive a low level on the Card C8 pin. Set this bit to set a high level on the Card C8 pin.
4 CARDC4
Clear this bit to drive a low level on the Card C4 pin. Set this bit to set a high level on the Card C4 pin.
3 CARDIO
Then this pin can be used as a pseudo bi-directional I/O when this bit is set. To be used as an input, this bit must contain a 1.
1 CARDRST
Clear this bit to drive a low level on the Card RST pin. Set this bit to set a high level on the Card RST pin.
0 CARDV CC
bits of SCC register have no effect while this bit is cleared.
Table 17. SCISR Register register of the Smart Card UART. It is cleared by hardware when SCTBUF is written to.
6 CARDIN
It shall be cleared by the hardware . This bit is set by hardware when the Smart card wait time counter times out. It shall be cleared by the reload of the counter or by the reset of the SCIB. It shall be cleared by software after this register has been read. It is cleared by hardware when SCBUF is read. This bit is set at the same time as SCTI or SCRI if a parity error is detected. It shall be cleared by software after this register has been read.
Table 18. SCIIR Register shift register of the Smart Card UART. It is cleared by hardware when this register is read. The value read from this bit is indeterminate. Do not change this bit or write 0. This bit is set when the output current goes out of the current range. It is cleared by hardware when this register is read.
4 CVccERR
It is cleared by hardware when this register is read. This bit is set by hardware when the Smart Card Timer 0 times out. It is cleared by hardware when this register is read. It is cleared by hardware when this register is read. It is cleared by hardware when this register is read. This bit is set at the same time as SCTI or SCRI if a parity error is detected. It is cleared by hardware when this register is read.
Table 19. SCIER Register
7 ESCTBI
Clear this bit to disable the Smart Card UART Transmit Buffer Empty interrupt. Set this bit to enable the Smart Card UART Transmit Buffer Empty interrupt. The value read from this bit is indeterminate. Do not change this bit . Clear this bit to disable the Card Current Error interrupt. Set this bit to enable the Card Current Error interrupt.
4 ECVccER
Clear this bit to disable the Card Voltage Error interrupt. Set this bit to enable the Card Voltage Error interrupt.
3 ESCWTI
Clear this bit to disable the Smart Card Wait timeout interrupt. Set this bit to enable the Smart Card Wait timeout interrupt.
2 ESCTI
Clear this bit to disable the Smart Card UART Transmit interrupt. Set this bit to enable the Smart Card UART Transmit interrupt.
1 ESCRI
Clear this bit to disable the Smart Card UART Receive interrupt. Set this bit to enable the Smart Card UART Receive interrupt.
0 ESCPI
Clear this bit to disable the Smart Card UART Parity Error interrupt. Set this bit to enable the Smart Card UART Parity Error interrupt.
Table 20. SCSR Register Table 21. SCTBUF Register
4 CREPSEL
1 SCCLK1
0 SCRS Smart card register selection
The SCRS bit selects which set of the SCIB registers is accessed. Can store a new byte to be transmitted on the I/O pin when SCTBE is set.
Table 22. SCRBUF Register Table 23. SCETU1 Register –– Provides the byte received from the I/O pin when SCRI is set. Bit ordering on the I/O pin depends on the Convention (see SCICR Register). The value read from these bits is indeterminate. Do not change these bits . Used together with the ETU LSB (see SCETU0 Register).
Table 24. SCETU0 Register Table 25. SCGT1 Register Table 26. SCGT0 Register According to ISO7816, ETU[10:0] can be set between 11 and 2047. The default reset value of ETU[10:0] is 372 (F = 372, D = 1). The value read from these bits is indeterminate. Do not change these bits . Used together with the Transmit Guard Time LSB (see SCGT0 Register). According to ISO 7816, GT can be set between 11 and 266 (11 to 254+12 ETU).
Table 27. SCWT2 Register Table 28. SCWT1 Register Table 29. SCWT0 Register Used together with WT[15:0] (see SCWT0 Register). Used together with WT[23:16] and WT[7:0] (see SCWT0 Register). WT[23:0] is the reload value of the Wait Time counter WTC. controlled by the WTEN bit (see Section “Waiting Time Counter (WT)”).
Card Interface interrupt. These interrupts are shown in Figure 23. Figure 23. Interrupt Control System global disable bit, which must be cleared to disable all interrupts at once. levels associated with each combination. Table 30. Priority Level Bit Values
Table 31. Interrupt Vector Addresses cleared when interrupt is processed. generate an interrupt if enabled with PRESEN (ISEL.1), EX1 (IE0.2) and EA (IE0.7) Bits. This detection is done according to the level selected with Bit CPLEV (ISEL.7). met. This Bit must be cleared by software.
Table 32. IE0 Register Clear to disable all interrupts. Set to enable all interrupts. clearing its interrupt enable bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. Clear to disable serial port interrupt. Set to enable serial port interrupt. Clear to disable Timer 1 overflow interrupt. Set to enable Timer 1 overflow interrupt.
2 EX1
Clear to disable external interrupt 1. Set to enable external interrupt 1. Clear to disable Timer 0 overflow interrupt. Set to enable Timer 0 overflow interrupt.
0 EX0
Clear to disable external interrupt 0. Set to enable external interrupt 0.
Table 33. IE1 Register The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. Clear to disable the SCI interrupt. Set to enable the SCI interrupt. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit.
Table 34. TCON Register Cleared by the hardware when processor vectors to interrupt routine. Clear to turn off Timer 0/Counter 1. Set to turn on Timer 0/Counter 1. Cleared by the hardware when processor vectors to interrupt routine. Clear to turn off Timer 0/Counter 0. Set to turn on Timer 0/Counter 0. Cleared by the hardware when interrupt is processed if edge-triggered (see IT1). Set by the hardware when external interrupt is detected on the INT 1 pin. Clear to select low level active (level triggered) for external interrupt 1 (INT 1). Set to select falling edge active (edge triggered) for external interrupt 1. Cleared by the hardware when interrupt is processed if edge-triggered (see IT0). Set by the hardware when external interrupt is detected on INT 0 pin. Clear to select low level active (level triggered) for external interrupt 0 (INT 0). Set to select falling edge active (edge triggered) for external interrupt 0.
Table 35. ISEL Register The value read from this bit is indeterminate. Do not set this bit. Set this bit to indicate that high level is active. Clear this bit to indicate that low level is active. Clear to disable the card presence detection interrupt coming from SCIB. Set to enable the card presence detection interrupt coming from SCIB. Clear to disable the RxD interrupt.
Table 36. IPL0 Register The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit.
4 PSL Serial port Priority bit
Refer to PSH for priority level. Refer to PT1H for priority level. Refer to PX1H for priority level. Refer to PT0H for priority level. Refer to PX0H for priority level.
Table 37. IPL1 Register The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit.
3 PSCIL Reserved
The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit.
Table 38. IPH0 Register The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit.
00 L o w e s t
Table 39. IPH1 Register The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit.
3 PSCIH
The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit.
4164G–SCR–07/06 LED Ports Configuration The current source of the LED Ports can be adjusted to 3 different values: 2, 4 or 10 mA. The LED output is an alternate function of P3.6 an P3.7 and cannot be used while the alternate card function is used. The control register LEDCON is detailed below. Registers Definition Table 40. LEDCON Register Reset Value = XXXX 0000b 76543210 ---- L E D 1 [ 1 ] L E D 1 [ 0 ] L E D 0 [ 1 ] L E D 0 [ 0 ] Bit Number Bit Mnemonic Description 7 - 4 - Reserved The value read from this bit is indeterminate. Do not set this bit. 3 - 2 LED1[1,0] Port LED1 configuration: LED1[1] LED1[0] Configuration 0 0 Standard C51 port 0 1 2 mA current source when P3.7 is at Low Level 1 0 4 mA current source when P3.7 is at Low Level 1 1 10 mA current source when P3.7 is at Low Level 1 - 0 LED0[1,0] Port LED0 configuration: LED0[1] LED0[0] Configuration 0 0 standard C51 port 0 1 2 mA current source when P3.6 is at Low Level 1 0 4 mA current source when P3.6 is at Low Level 1 1 10 mA current source when P3.6 is at Low Level
moves of blocks need to be accomplished. The second Data Pointer can be used to address the on-chip XRAM. Table 41. DPL Register Table 42. DPH Register
Table 43. AUXR1 Register The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. Clear to select DPTR0 as Data Pointer. Set to select DPTR1 as Data Pointer.
the product and is detailed below. gram is executed (for In System programming). Program ROM Lock Bits The program Lock system protects the on-chip program against software piracy. The T8xC5121 products are delivered with the highest protection level. Table 45. T8xC5121 Products Protection Level
7 Reserved
EA is sampled and latched on reset. But checksum control is still enabled. External execution is possible.
Table 46. RCON Register used for the Bootloader program. or from a host through RS232 serial communication. Bootloader is program masked in ROM space. The Hardware Byte BLJRB value is 0. As described on page 7, after Reset, the Bootloader program is executed. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit.
program download its content in the internal EEPROM and in CRAM. initializes the Program counter at the lower address (0000h) of the executable CRAM. Figure 24. CRAM with ROM and EEPROM Memory Mappings The ROM memory contains the Bootloader program. The CRAM is the Application program memory. CRAM space and the program is executed.
16 Kbytes
Figure 25. CRAM and ROM Mappings In this version, the customer program is masked in 16 Kbytes ROM. The ISP is used to download an Application program in the device and to run it. The communication protocols which are implemented are: UART and TWI.
Figure 26. Hardware in Relation with the Two Communication Protocols The use of these bytes is described in the following paragraphs. Therefore, the User Program must be mapped from 0000h to 3FFCh address.
Figure 27. Bootloader Flowchart
4164G–SCR–07/06 In-System Programming Timings The download from the internal EEPROM to CRAM is executed after 4 seconds when operating at 12 MHz frequency. Protection Mechanisms Transfer Checks In order to verify that the transfers are free of errors, a CRC c heck is implemented dur- ing the download of the program in CRAM. This test is done at the end of the 16K space programming. As detailed in the next algorithms: in ISP mode, if CRC test pass, a character Y is returned before the CRLF characters else a character Z is retuned. in download mode, a serial data AA is sent on P3.7 port and CRAM is not executed. For this purpose, the user program must include in the two last upper bytes (address 3FFEh and 3FFFh) the CRC of the previous bytes (calculated from the address 0000h to 3FFFDh). The following frames are examples incl uding the CRC in the two last upper bytes: FF 03 C0 21 04 00 00 08 07 02 08 02 2D DB (CRC = 2DDBh) FF 03 80 21 02 04 00 0A 03 06 C0 A8 70 01 E3 3D (CRC = E33Dh) FF 03 C0 21 02 01 00 10 02 06 00 00 00 00 05 06 00 00 76 55 49 AC (CRC = 49ACh) The CRC algorithm is the following : Ui n t16 co m pu t e_crc (Ui n t16 W ) Uc h arC ; W & =(Ui n t16)0x00F F ; f o r (C =(Uc h ar)8;C ; C--) i f ((Uch a r) W &(Uc ha r)1 ) W > > = 1 ; W ^= ( U in t16)0x 8 408; e l s e W > > = 1 ; re tu rn W ; Data Bytes
2 Bytes CRC
Address: 3FFE,3FFF
Table 47. Synthesis of Transfer Protection Mechanisms
- If a Bad transfer has occurred in the Internal EEPROM (CRC is bad), as the CRC
be executed after any Reset. This SSB Byte is located at address 3FFDh. on P3.7 and Code execution by LJMP000 is not done.
The only mean to remove the security level 2 is to send a Full Chip Erase command. Table 48. Synthesis of Security Mechanisms TWI external bus and later in the algorithm if characters are received on the UART input. – to avoid any conflict with the target hardware on external TWI bus or UART. The bit 7 is used to bypass (if 0) the External TWI Acknowledge test. The bit 6 is used to bypass (if 0) the UART receipt test.
Table 49. Valid Software Security Byte Values Overview The serial protocol used is described below. values in the last two upper bytes of the 16K bytes space. mands (with 64 data bytes) from address 0000h to address 3FFFh. Frame Description The Serial Protocol is based on the Intel Hex-type records. Table 50. Intel Hex Type Frame – Record Mark is the start of frame. This field must contain’:’. the Record Type field of the record. therefore this field is used only for Program Data Record (see Table 51).
4164G–SCR–07/06 Record Type: – Record Type specifies the command type. This field is used to interpret the remaining information within the frame. The encoding for all the current record types are described in Table 51. Data/Info: – Data/Info is a 64 bytes length field. It consists of 64 bytes encoded as pairs of hexadecimal digits. The meaning of data depends on the Record Type. Checksum: – The two’s complement of the 8-bit bytes that result from converting each pair of ASCII hexadecimal digits to one byte of binary, and including the Reclen field to and including the last byte of the Data/Info field. Therefore, the sum of all the ASCII pairs in a record after converting to binary, from the Reclen field to and including the Checksum field, is zero. Notes: 1. A data byte is represented by two ASCII characters. 2. When the field Load Offset is not used, it should be coded as 2 bytes (00h 00h). Command Description Table 51. Frame Description Command Command Name data[0] data[1] Command Effect 00h Program Data Program 64 Data Bytes 01h End Of File - - End of File 03h Write Function 07h 05h 05h 03h 00h 01h 01h Full Chip Erase Program SSB level1 Program SSB level2 LJMP(data[2],data[3]) (LJMP0000h) 04h Display Function Data[0:1] = start address Data [2:3] = end address Data[4] = 00h -> Display data Data[4] = 01h -> Blank check Data[4] = 03h -> Display CRAM Display Data 05h Read Function 07h 0Fh 00h 00h Read SSB Read Bootloader Version 06h Direct Load of Baud Rate HSB LSB Not implemented
establish the baud rate. Table show the autobaud capability.
- If a bad transfer has occurred in the Internal EEPROM (CRC is bad), as the CRC
be executed after any Reset. Table 52. Autobaud Performances
9600 OK OK OK OK OK OK -
19200 OK - OK OK Ok OK OK
applied on P3.7. Error code’Z’ is returned to ISP.
4164G–SCR–07/06 UART ISP Intern. EEP Programming SSB level 1 must be set (done, if selected, at ISP Programming or Ext EEP Donwload) UART ISP CRAM Program access SSB level 1 IN Int EEP protects as, first, the Int EEP is programmed before CRAM UART ISP SSB in EEP and CRAM level 2 to level 1 Protected by Bootloader UART ISP SSB in EEP and CRAM level 1 to level 0 Protected by Bootloader Source Target Case Protection
4164G–SCR–07/06 Timers/Counters Introduction The T8xC5121 implements two general-purpose, 16-bit Timer 0s/Counters. Although they are identified as Timer 0, Timer 1, you can independently configure each to operate in a variety of modes as a Timer 0 or as an event Counter. When operating as a Timer 0, a Timer 0/Counter runs for a programmed length of time, then issues an interrupt request. When operating as a Counter, a Timer 0/Counter counts negative transitions on an external pin. After a preset number of counts, the Counter issues an interrupt request. The Timer 0 registers and associated control registers are implemented as addressable Special Function Registers (SFRs). Two of the SFRs provide programmable control of the Timer 0s as follows: Timer 0/Counter mode control register (TMOD) and Timer 0/Counter control register (TCON) control respectively Timer 0 and Timer 1. The various operating modes of each Timer 0/Counter are described below. Timer 0/Counter Operations For example, a basic operation is Timer 0 registers THx and TLx (x = 0, 1) connected in cascade to form a 16-bit Timer 0. Setting the run control bit (TRx) in the TCON register (see Figure 55) turns the Timer 0 on by allowing the selected input to increment TLx. When TLx overflows it increments THx and when THx overflows it sets the Timer 0 over- flow flag (TFx) in the TCON register. Setting the TRx does not clear the THx and TLx Timer 0 registers. Timer 0 registers can be accessed to obtain the current count or to enter preset values. They can be read at any time but the TRx bit must be cleared to preset their values, otherwise the behavior of the Timer 0/Counter is unpredictable. The C/Tx# control bit selects Timer 0 operation or Counter operation by selecting the divided-down system clock or the external pin Tx as the source for the counted signal. The TRx bit must be cleared when changing the operating mode, otherwise the behavior of the Timer 0/Counter is unpredictable. For Timer 0 operation (C/Tx# = 0), the Time r 0 register counts the divided-down system clock. The Timer 0 register incremented once every peripheral cycle. Exceptions are the Timer 0 2 Baud Rate and Clock- Out modes in which the Timer 0 reg- ister is incremented by the system clock divided by two. For Counter operation (C/Tx# = 1), the Timer 0 register counts the negative transitions on the Tx external input pin. The external input is sampled during every S5P2 state. The Programmer’s Guide describes the notation for the states in a peripheral cycle. When the sample is high in one cycle and low in the next one, the Counter is incremented. The new count value appears in the register during the next S3P1 state after the transition has been detected. Since it takes 12 states (24 oscillator periods) to recognize a nega- tive transition, the maximum count rate is 1/24 of the oscillator frequency. There are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it should be held for at least one full periph- eral cycle.
Figure 31. Timer 0/Counter 0 in Mode 3: Two 8-bit Counters
4164G–SCR–07/06 Timer 1 Timer 1 is identical to Timer 0 except for Mode 3 which is a hold-count mode. The fol- lowing comments help to understand the differences: Timer 1 functions as either a Timer 0 or an event Counter in the three operating modes. Figure 28 through Figure 30 show the logical configuration for modes 0, 1, and 2. Mode 3 of Timer 1 is a hold-count mode. Timer 1 is controlled by the four high-order bits of the TMOD register (see Figure 56) and bits 2, 3, 6 and 7 of the TCON register (see Figure 55). The TMOD register selects the method of Timer 0 gating (GATE1), Timer 0 or Counter operation (C/T1#) and the operating mode (M11 and M01). The TCON register provides Timer 1 control functions: overflow flag (TF1), run control bit (TR1), interrupt flag (IE1) and the interrupt type control bit (IT1). Timer 1 can serve as the Baud Rate Generator for the Serial Port. Mode 2 is best suited for this purpose. For normal Timer 0 operation (GATE1 = 0), setting TR1 allows TL1 to be incremented by the selected input. Setting GATE1 and TR1 allows external pin INT1 to control Timer 0 operation. Timer 1 overflow (count rolls over from all 1s to all 0s) sets the TF1 flag and generates an interrupt request. When Timer 0 is in mode 3, it uses Timer 1’s overflow flag (TF1) and run control bit (TR1). For this situation, use Timer 1 only for applications that do not require an interrupt (such as a Baud Rate Generator for the Serial Port) and switch Timer 1 in and out of mode 3 to turn it off and on. It is important to stop the Timer 0/Counter before changing modes. Mode 0 (13-bit Timer 0) Mode 0 configures Timer 1 as a 13-bit Timer 0, which is set up as an 8-bit Timer 0 (TH1 register) with a modulo-32 prescaler implemented with the lower 5 bits of the TL1 regis- ter (see Figure 28). The upper 3 bits of TL1 register are ignored. Prescaler overflow increments the TH1 register. Mode 1 (16-bit Timer 0) Mode 1 configures Timer 1 as a 16-bit Timer 0 with TH1 and TL1 registers connected in cascade (see Figure 29). The selected input increments the TL1 register. Mode 2 (8-bit Timer 0 with Auto-Reload) Mode 2 configures Timer 1 as an 8-bit Timer 0 (TL1 register) with automatic reload from the TH1 register on overflow (see Figure 30) . TL1 overflow sets the TF1 flag in the TCON register and reloads TL1 with the contents of TH1, which is preset by the soft- ware. The reload leaves TH1 unchanged. Mode 3 (Halt) Placing Timer 1 in mode 3 causes it to halt and hold its count. This can be used to halt Timer 1 when the TR1 run control bit is not available i.e., when Timer 0 is in mode 3.
4164G–SCR–07/06 Registers Table 55. TCON Register TCON (S:88h) - Timer 0/Counter Control Register Reset Value = 0000 0000b 76543210 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 Bit Number Bit Mnemonic Description 7T F 1 Timer 1 Overflow flag Cleared by the hardware when processor vectors to interrupt routine. Set by the hardware on Timer 0/Counter overflow when Timer 1 register overflows. 6T R 1 Timer 1 Run Control bit Clear to turn off Timer 0/Counter 1. Set to turn on Timer 0/Counter 1. 5T F 0 Timer 0 Overflow flag Cleared by the hardware when processor vectors to interrupt routine. Set by the hardware on Timer 0/Counter overflow when Timer 0 register overflows. 4T R 0 Timer 0 Run Control bit Clear to turn off Timer 0/Counter 0. Set to turn on Timer 0/Counter 0. 3I E 1 Interrupt 1 Edge flag Cleared by the hardware when interrupt is processed if edge-triggered (see IT1). Set by the hardware when external interrupt is detected on the INT 1 pin. 2I T 1 Interrupt 1 Type Control bit Clear to select low level active (level triggered) for external interrupt 1 (INT 1). Set to select falling edge active (edge triggered) for external interrupt 1. 1I E 0 Interrupt 0 Edge flag Cleared by the hardware when interrupt is processed if edge-triggered (see IT0). Set by the hardware when external interrupt is detected on INT 0 pin. 0I T 0 Interrupt 0 Type Control bit Clear to select low level active (level triggered) for external interrupt 0 (INT 0). Set to select falling edge active (edge triggered) for external interrupt 0.
Table 56. TMOD Register Clear to enable Timer 1 whenever TR1 bit is set. Set to enable Timer 1 only while INT1 pin is high and TR1 bit is set. Clear for Timer 0 operation: Timer 1 counts the divided-down system clock. Set for Counter operation: Timer 1 counts negative transitions on external pin T1. 0 0 Mode 0:8-bit Timer 0/Counter (TH1) with 5-bit prescaler (TL1). 0 1 Mode 1:16-bit Timer 0/Counter. 1 0 Mode 2:8-bit auto-reload Timer 0/Counter (TL1). Reloaded from TH1 at overflow. 1 1 Mode 3:Timer 1 halted. Retains count. Clear to enable Timer 0 whenever TR0 bit is set. Set to enable Timer 0/Counter 0 only while INT0 pin is high and TR0 bit is set. Clear for Timer 0 operation: Timer 0 counts the divided-down system clock. Set for Counter operation: Timer 0 counts negative transitions on external pin T0. 0 0 Mode 0:8-bit Timer 0/Counter (TH0) with 5-bit prescaler (TL0). 1 0 Mode 2:8-bit auto-reload Timer 0/Counter (TL0). Reloaded from TH0 at overflow. 1 1 Mode 3:TL0 is an 8-bit Timer 0/Counter. TH0 is an 8-bit Timer 0 using Timer 1’s TR0 and TF0 bits.
Table 57. TH0 Register TH0 (S:8Ch) - Timer 0 High Byte Register. Table 58. TL0 Register TL0 (S:8Ah) - Timer 0 Low Byte Register. Table 59. TH1 Register TH1 (S:8Dh) - Timer 1 High Byte Register. Table 60. TL1 Register TL1 (S:8Bh) - Timer 1 Low Byte Register.
4164G–SCR–07/06 To address a device by its individual address, the SADEN mask byte must be 1111 1111b. For example: SADDR0101 0110b SADEN1111 1100b Given0101 01XXb The following is an example of how to use given addresses to address different slaves: Slave A:SADDR1111 0001b SADEN1111 1010b Given1111 0X0Xb Slave B:SADDR1111 0011b SADEN1111 1001b Given1111 0XX1b Slave C:SADDR1111 0011b SADEN1111 1101b Given1111 00X1b The SADEN byte is selected so that each slave may be addressed separately. For slave A, bit 0 (the LSB) is a don’t care bit; for slaves B and C, bit 0 is a 1. To commu- nicate with slave A only, the master must send an address where bit 0 is clear (e.g. 1111 0000b). For slave A, bit 1 is a 0; for slaves B and C, bit 1 is a don’t care bit. To communicate with slaves A and B, but not slave C, the master must send an address with bits 0 and 1 both set (e.g. 1111 0011b). To communicate with slaves A, B and C, the master must send an address with bit 0 set, bit 1 clear, and bit 2 clear (e.g. 1111 0001b). Broadcast Address A broadcast address is formed from the logical OR of the SADDR and SADEN registers with zeros defined as don’t care bits, e.g.: SADDR0101 0110b SADEN1111 1100b SADDR OR SADEN1111 111Xb The use of don’t care bits provides flexibility in defining the broadcast address, however in most applications, a broadcast address is FFh. The following is an example of using broadcast addresses: Slave A:SADDR1111 0001b SADEN1111 1010b Given1111 1X11b, Slave B:SADDR1111 0011b SADEN1111 1001b Given1111 1X11B, Slave C:SADDR = 1111 0010b SADEN1111 1101b Given1111 1111b For slaves A and B, bit 2 is a don’t care bit; for slave C, bit 2 is set. To communicate with all of the slaves, the master must send an address FFh. To communicate with slaves A and B, but not slave C, the master can send and address FBh.
4164G–SCR–07/06 Reset Addresses On reset, the SADDR, SADEN register are initialized to 00h, i.e. the given and broad- cast addresses are XXXX XXXXb (all don’t care bits). This ensures that the serial port is backwards compatible with the 80C51 microcontrollers that do not support automatic address recognition. UART Output Configuration Voltage Level The I/O Ports of UART are powered by the EVCC Regulator. The voltage of this regulator can be: Automatically controlled by the microcontroller which adapt the power supply level versus the OE input voltage level. Set at three defined levels (1.8V, 2.3V or 2.8V) These configurations are defined with the EVAUTO and VEXT0,VEXT1 Bits of SIOCON Register. Output Enable Function The UART outputs (Tx, T0) can be controlled by the Output Enable input. The Bits PMOSEN0 and PMOSEN1 in SIOCON Register are used to control this output. PMOSEN0 PMOSEN0 PMOSEN1OE (P3.3) PMOS Command (Active at 1) SFR Value0
Table 62. SADDR Register Table 63. SBUF Register
the single synchronous and the three asynchronous modes according to Table 64. Table 64. Serial I/O Port Mode Selection Generator as it allows higher and more accurate baud rates than with Timer 1. doubling of the generated baud rate. Figure 36. Timer 1 Baud Rate Generator Block Diagram ister allows doubling of the generated baud rate.
stop bit instead of the last data bit as detailed in Figure 36. Figure 46. Framing Error Block Diagram Rate Generator and allows different baud rate in reception and transmission. clock frequencies and giving baud rates closer to the standard baud rates. Figure 47. Baud Rate Source Selection (Modes 1 and 3) Figure 48. Baud Rate Formulas (Modes 1 and 3)
2 SMOD1 ⋅ FPER
Table 66. BRL (S:91h) 7 - 0 BRL7:0 Baud Rate Reload Value.
Table 67. SCON Register To select this function, set SMOD0 bit in PCON register. Set by hardware to indicate an invalid stop bit. Must be cleared by software. To select this function, clear SMOD0 bit in PCON register. Software writes to bits SM0 and SM1 to select the Serial Port operating mode. Refer to SM1 bit for the mode selections. To select this function, set SMOD0 bit in PCON register. Software writes to bits SM1 and SM0 to select the Serial Port operating mode. Clear to disable reception in mode 1, 2 and 3, and to enable transmission in mode 0. Set to enable reception in all modes. Modes 2 and 3: Software writes the ninth data bit to be transmitted to TB8. Mode 1 (SM2 cleared): Set or cleared by hardware to reflect the stop bit received. Modes 2 and 3 (SM2 set): Set or cleared by hardware to reflect the ninth bit received. Set by the transmitter after the last data bit is transmitted. Must be cleared by software. Set by the receiver after the stop bit of a frame has been received. Must be cleared by software.
Table 68. BDRCON Register The value read from this bit is indeterminate. Do not set this bit. Clear to stop the Baud Rate. Clear to select Timer 1 for the Baud Rate Generator. Set to select internal Baud Rate Generator. Clear to select Timer 1 for the Baud Rate Generator. Set to select internal Baud Rate Generator.
1 SPD
Clear to select the SLOW Baud Rate Generator when SRC = 1. Set to select the FAST Baud Rate Generator when SRC = 1. OSC/12 as the Baud Rate Generator. Set to select the internal Baud Rate Generator.
Table 69. SIOCON Register The value read from this bit is indeterminate. Do not set this bit.
3 CPRES
0 Internal pull-up is connected
1 Internal pull-up is disconnected
96 A/T8xC5121
that will periodically be executed within the time required to prevent a WDT reset. before the WDT activation sequence, and can not be modified until next reset. Table 70. WDTRST Register
Table 71. WDTPRG Register while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high. It is suggested that the WDT be reset during the interrupt service routine. is better to reset the WDT just before entering powerdown. exit Idle, service the WDT, and re-enter Idle mode. The value read from this bit is undetermined. Do not try to set this bit.
4164G–SCR–07/06
Electrical Characteristics
DC Parameters TA = -40°C to +85°C; VSS = 0 V; VCC = 2.85V to 5.4V; F = 7.36 to 16 MHz Table 72. Core DC Parameters (XTAL, RST , P0, P2, ALE, PSEN , EA)
Table 74. LED outputs DC Parameters (P3.6 and P3.7)
Table 75. Smart Card 5V Interface DC Parameters Note: 1. Capacitor = 10 µF, X7R type. Maximum ESR value is 250 mohm, Inductor = 4.7 µH. Table 76. Smart Card 3V Interface DC Parameters Note: 1. Capacitor = 10 µF, X7R type. Maximum ESR value is 250 mohm, Inductor = 4.7 µH. Table 77. Smart Card 1.8V Interface DC Parameters Note: 1. Capacitor = 10 µF, X7R type. Maximum ESR value is 250 mohm, Inductor = 4.7 µH.
Table 78. Smart Card Clock DC Parameters (Port P1.4) Table 79. Alternate Card Clock DC parameters (Port P3.6): 5V tolerant
Table 80. Smart Card I/O DC Parameters (P1.0) Table 81. Alternate Card I/O DC Parameters (P3.5) : 5V tolerant
Table 82. Smart Card RST, CC4, CC8, DC Parameters (Port P1.5, P1.3, P1.1) Table 83. Alternate Card RST DC Parameters (Port P3.7) : 5V tolerant Table 84. Card Presence DC Parameters (P1.2)
Figure 54. Typical Application Diagram
- Straight and short connections avoid any loop between:
- VCC connection of the master card must be placed as follows:
- Current is limited to 10 mA.
- CCLK should be routed far from CRST, CIO, CC4, CC8 and armored by ground plane.
4164G–SCR–07/06 6. Distance between Device pads and Smart Card connector must be less than 4 centimeters. 7. C6,C7 should be as close as possible to the Smart Card connector to reduce noise and interferences.
4164G–SCR–07/06
Ordering Information
Note: 1. Contact Atmel for availability. Part Number Code Memory Size (Bytes) Supply Voltage Temperature Range Max Frequency Package Packing Product Marking T83C5121xxx- ICSIL 16K ROM 2.85 - 5.4V Industrial 16 MHz SSOP24 Stick 83C5121-IL T83C5121xxx- ICRIL 16K ROM 2.85 - 5.4V Industrial 16 MHz SSOP24 T ape & Reel 83C5121-IL T83C5121xxx- S3SIL 16K ROM 2.85 - 5.4V Industrial 16 MHz PLCC52 (1) Stick 83C5121-IL T83C5121xxx- S3RIL 16K ROM 2.85 - 5.4V Industrial 16 MHz PLCC52 (1) Tape & Reel 83C5121-IL T85C5121-ICSIL 16K RAM 2.85 - 5.4V Industrial 16 MHz SSOP24 Stick 85C5121-IL T85C5121-ICRIL 16K RAM 2.85 - 5.4V Industrial 16 MHz SSOP24 T ape & Reel 85C5121-IL T85C5121-S3SIL 16K RAM 2.85 - 5.4V Industrial 16 MHz PLCC52 Stick 85C5121-IL T85C5121-S3RIL 16K RAM 2.85 - 5.4V Industrial 16 MHz PLCC52 Tape & Reel 85C5121-IL T89C5121-ICSIL 16K Flash RAM 2.85 - 5.4V Industrial 16 MHz SSOP24 Stick 89C5121-IL T89C5121-ICRIL 16K Flash RAM 2.85 - 5.4V Industrial 16 MHz SSOP24 T ape & Reel 89C5121-IL AT83C5121xxx- ICSUL 16K ROM 2.85 - 5.4V Industrial & Green 16 MHz SSOP24 Stick 83C5121-UL AT83C5121xxx- ICRUL 16K ROM 2.85 - 5.4V Industrial & Green 16 MHz SSOP24 T ape & Reel 83C5121-UL AT83C5121xxx- PUTUL 16K ROM 2.85 - 5.4V Industrial & Green 16 MHz QFN32 Tray 83C5121-UL AT83C5121xxx- PURUL 16K ROM 2.85 - 5.4V Industrial & Green 16 MHz QFN32 Tray 83C5121-UL AT83C5121xxx- S3SUL 16K ROM 2.85 - 5.4V Industrial & Green 16 MHz PLCC52 (1) Stick 83C5121-UL AT83C5121xxx- S3RUL 16K ROM 2.85 - 5.4V Industrial & Green 16 MHz PLCC52 (1) Tape & Reel 83C5121-UL AT85C5121- ICSUL 16K RAM 2.85 - 5.4V Industrial & Green 16 MHz SSOP24 Stick 85C5121-UL AT85C5121- ICRUL 16K RAM 2.85 - 5.4V Industrial & Green 16 MHz SSOP24 T ape & Reel 85C5121-UL AT85C5121- S3SUL 16K RAM 2.85 - 5.4V Industrial & Green 16 MHz PLCC52 Stick 85C5121-UL AT85C5121- S3RUL 16K RAM 2.85 - 5.4V Industrial & Green 16 MHz PLCC52 Tape & Reel 85C5121-UL AT89C5121- ICSUL 16K Flash RAM 2.85 - 5.4V Industrial & Green 16 MHz SSOP24 Stick 89C5121-UL AT89C5121- ICRUL 16K Flash RAM 2.85 - 5.4V Industrial & Green 16 MHz SSOP24 T ape & Reel 89C5121-UL
4164G–SCR–07/06 Package Drawings SSOP24
4164G–SCR–07/06 PLCC52
4164G–SCR–07/06 QFN32
4164G–SCR–07/06 Document Revision History for T8xC5121 Changes from 4164B - 06/02 to 4164C - 07/03 1. Ports description update. 2. Added Bootloader Autobaud table. 3. Modified I CC test conditions Figure 51. 4. Added I CCOP power supply current characteristics. 5. Added I CCO pulsed power down mode current characteristics. 6. Modified Smart card characteristics : V CC/CVCC mixed. Changes from 4164C - 07/03 to 4164D - 12/03 1. Changed value of EMV to EMV2000. Section “Features”, page 1. Changes from 4164D - 12/03 to 4164E - 01/04 1. DVcc Min/Max values changed, page 96. 2. Alternate Card Pads are 5V tolerant, page 99. Changes from 4164E - 01/04 to 4164F 11/05 1. Added green product ordering information. Changes from 4164F 11/05 to 4164F 07/06 1. Added QFN32 package to ordering information.
4164G–SCR–07/06 A/T8xC5121
4164G–SCR–07/06 A/T8xC5121
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