AT84AS003 ATMEL | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 8
Technical content
Features
10-bit Resolution 1.5 Gsps Sampling Rate Selectable 1:2 or 1:4 Demultiplexed Output 500 mVpp Differential 100Ω or Single-ended 50Ω Analog Input 100Ω Differential or Single-ended 50Ω Clock input LVDS Output Compatibility Functions: – ADC Gain Adjust – Sampling Delay Adjust – 1:4 Demultiplexed Simultaneous or Staggered Digital Outputs – Data Ready Output with Asynchronous Reset – Out-of-range Output Bit (11th Bit) Power Consumption : 6.5W Power Supplies: -5V, -2.2V, 3.3V and VPLUSD Output Power Supply Package – Cavity Down EBGA 317 (Enhanced Ball Grid Array) – 25 × 35 mm Overall Dimensions Performances 3 GHz Full-power Analog Input Bandwidth ±0.4 dB Gain Flatness from DC up to 1.5 GHz Single-tone Performance at Fs = 1.5 Gsps, Full Nyquist Zone – ENOB = 8.0 Effective Bits, F IN = 750 MHz – SNR = 52 dB, SFDR = -60 dBFS, F IN = 750 MHz Dual-tone Performance (IMD3) at Fs = 1.5 Gsps (-7 dBFS each tone) – Fin1 = 745 MHz, Fin2 = 755 MHz: IMD3 = -60 dBFS – Fin1 = 1244 MHz, Fin2 = 1255 MHz: IMD3 = -60 dBFS Screening Temperature Range: –T C > 0°C; TJ < 90°C (Commercial “C” Grade) –T C > -20°C; TJ < 110°C (Industrial “V” Grade)
Applications
Direct RF Down Conversion Ultra Wide Band Satellite Receivers Radars and Countermeasures High-speed Acquisition Systems High Energy Physics Automatic Test Equipment
Description
The AT84AS003 combines a 10-bit 1.5 Gsps analog-to-digital converter with a 1:4 DMUX, designed for accurate digitization of broadband signals. It features 8.0 Effective Number of Bits (ENOB) and -60 dBFS Spurious Free Dynamic Range (SFDR) at 1.5 Gsps over the full first Nyquist zone. 10-bit
1.5 Gsps ADC
1:4 DMUX AT84AS003 Summary This is a summary document. A complete document is not available at this time. For more information, please contact your local Atmel sales office.
2 AT84AS003
additional tuning of the synchronization between the ADC and DMUX. Figure 1. Block Diagram
20 Port B
20 Port C
20 Port D
2 DR/DRN
2 BOR/BORN
2 COR/CORN
2 DOR/DORN
5403AS–BDC–10/04 Functional The AT84AS003 is a 10-bit 1.5 Gsps ADC combined with a high-speed demultiplexer (DMUX) used to lower the LVDS output bit stream (10-bit data and one out-of range bit) by a factor of 2 or 4. The ADC works in fully differential mode from the analog input to the digital outputs. It provides an on-chip 100Ω differential termination for the clock input. The analog input is 500 mVpp on a 100 Ω differential input impedance. 50 Ω reverse terminations are required for the analog input. They should be placed as close as possible to the EBGA package input pins (2 mm maximum). The output clock and the output data are LVDS compatible (100Ω differentially terminated). The AT84AS003 ADC features two asynchronous resets: DRRB, which ensures that the first digitiz ed data corresponds to the first acquisition ASYNCRST, which initializes the DMUX The gain control pin GA is used to finely adjust the ADC gain to a unity gain. The control pin B/GB is provided to select either a binary or gray data output format. A Sampling Delay Adjust function (SDA, ac tivated via the SDAEN signal) may be used to fine-tune the ADC aperture delay by approximately 120 ps around its nominal value. This function is useful when interleaving multiple ADCs. The control pin B/GB is provided to select either a binary or Gray data output format. A tunable delay cell (controlled via CLKDACTRL) is integrated between the ADC and the DMUX on the clock path to fine-tune the data according to the clock alignment at the interface between the ADC and the DMUX. This delay can be tuned from -250 to 250 ps around a default center value, featuring a 500 ps typical tuning range. No tuning should be necessary for operating frequencies up to 1.5 Gsps. An extra stand-alone delay cell is also provided. It is controlled via analog DACTRL con- trol input and activated via DAEN. The tuning range is typically 500 ps. A pattern generator (PGEB) is integrated in the ADC block for debugging purposes or acquisition setup. Similarly, a Built-in Self Test (BIST) is provided for quick debug of the DMUX block. The demultiplexer ratio can be selected using RS (1:2 or 1:4 ratio). Two modes for the output clock (via DRTYPE) are selectable: DR mode: only the output clock’s rising egde is active, the output clock rate is the same as the output data rate DR/2 mode: both the output clock’s rising and falling edges are active, the output clock rate is half the output data rate The AT84AS003’s data is output in two different modes: Staggered: even and odd bits are output with half a data period delay Simultaneous: even and odd bits are output at the same time A sleep mode is provided to lower the power consumption of the DMUX block. Die junction temperature monitoring is also provided to facilitate management of the junction temperature, by sensing the voltage drop across two diodes implemented on the ADC and DMUX respectively, close to the chip’s hot point. The AT84AS003 is delivered in an Enhanced Ball Grid Array (EBGA). Its TCE, which is similar to that of the FR4 material, makes it highly suitable for applications exposed to large thermal variations.
4 AT84AS003
Table 1. Description of Functions
Figure 2. Device Pinout
2 AOR, AORN
2 COR, CORN
2 DOR, DORN
6 AT84AS003
5403AS–BDC–10/04
Package Information
Figure 3. EBGA 317 Package Outline (Bottom View)
5403AS–BDC–10/04
Ordering Information
Part Number Package Temperature Range Screening Comments AT84XAS003TP EBGA 317 Ambient Prototype Prototype version Please contact your local Atmel sales office AT84AS003CTP EBGA 317 Commercial “C” TC > 0°C; TJ < 90°C Standard AT84AS003VTP EBGA 317 Industrial “V” TC> -20°C; TJ < 110°C Standard AT84AS003TP-EB EBGA 317 Ambient Prototype Evaluation kit
Printed on recycled paper. Disclaimer: Atmel Corporation makes no warranty for the use of its products , other than those expressly contained in the Company’s standar d warranty which is detailed in Atmel’s Terms and Conditions locat ed on the Company’s web site. The Company assumes no responsibi lity for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time wi thout notice, and does not make any commitment to update the information contained her ein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel produc ts, expressly or by implication. Atmel’s products are not aut horized for use as critical components in life support devices or systems. Atmel Corporation Atmel Operations
2325 Orchard Parkway
San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza
77 Mody Road Tsimshatsui
Tel: (852) 2721-9778 Fax: (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Memory San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 Microcontrollers San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602
44306 Nantes Cedex 3, France
13106 Rousset Cedex, France
1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300 Fax: 1(719) 540-1759 Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 0QR, Scotland Tel: (44) 1355-803-000 Fax: (44) 1355-242-743 RF/Automotive Theresienstrasse 2 Postfach 3535
74025 Heilbronn, Germany
1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300 Fax: 1(719) 540-1759 Biometrics/Imaging/Hi-Rel MPU/ High Speed Converters/RF Datacom Avenue de Rochepleine BP 123
38521 Saint-Egreve Cedex, France
www.atmel.com/literature 5403AS–BDC–10/04 © Atmel Corporation 2004 . All rights reserved. Atmel ® and combinations thereof are the register ed trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be the trademarks of others.