AT84AD001B ATMEL | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 60
Technical content
Features
Dual ADC with 8-bit Resolution 1 Gsps Sampling Rate per Channel, 2 Gsps in Interlaced Mode Single or 1:2 Demultiplexed Output LVDS Output Format (100Ω) 500 mVpp Analog Input (Differential Only) Differential or Single-ended 50Ω PECL/LVDS Compatible Clock Inputs Power Supply: 3.3V (Analog), 3.3V (Digital), 2.25V (Output) LQFP144 Package Temperature Range: – 0°C < TA < 70°C (Commercial Grade) – -40°C < TA < 85°C (Industrial Grade) 3-wire Serial Interface – 16-bit Data, 3-bit Address – 1:2 or 1:1 Output Demultiplexer Ratio Selection – Full or Partial Standby Mode – Analog Gain (±1.5 dB) Digital Control – Input Clock Selection – Analog Input Switch Selection – Binary or Gray Logical Outputs – Synchronous Data Ready Reset – Data Ready Delay Adjustable on Both Channels – Interlacing Functions: Offset and Gain (Channel to Channel) Calibration Digital Fine SDA (Fine Sampling Delay Adjust) on One Channel – Internal Static or Dynamic Built-In Test (BIT) Performance Low Power Consumption: 0.7W Per Channel Power Consumption in Standby Mode: 120 mW 1.5 GHz Full Power Input Bandwidth (-3 dB) SNR = 42 dB Typ (6.8 ENOB), THD = -51 dBc, SFDR = -54 dBc at Fs = 1 Gsps Fin = 500 MHz 2-tone IMD3: -54 dBc (499 MHz, 501 MHz) at 1 Gsps DNL = 0.25 LSB, INL = 0.5 LSB Channel to Channel Input Offset Erro r: 0.5 LSB Max (After Calibration) Gain Matching (Channel to Channel): 0.5 LSB Max (After Calibration) Low Bit Error Rate (10 -13) at 1 Gsps Application Instrumentation Satellite Receivers Direct RF Down Conversion W L A N Dual 8-bit
1 Gsps ADC
Smart ADC™
2 AT84AD001B
2153C–BDC–04/04 Description The AT84AD001B is a monolithic dual 8-bit analog-to-digital converter, offering low 1.4W power consumption and excellent digitizing accuracy. It integrates dual on-chip track/holds that provide an enhanced dynamic performance with a sampling rate of up to 1 Gsps and an input frequency bandwidth of over 1.5 GHz. The dual concept, the inte- grated demultiplexer and the easy interleaving mode make this device user-friendly for all dual channel applications, such as direct RF conversion or data acquisition. The smart function of the 3-wire serial interfac e eliminates the need for external compo- nents, which are usually necessary for gain and offset tuning and setting of other parameters, leading to space and power reduction as well as system flexibility. Functional Description The AT84AD001B is a dual 8-bit 1 Gsps ADC based on advanced high-speed BiCMOS technology. Each ADC includes a front-end analog multiplexer followed by a Sample and Hold (S/H), and an 8-bit flash-like architecture core analog-to-digital converter. The output data is followed by a switchable 1:1 or 1:2 demultiplexer and LVDS output buffers (100Ω). Two over-range bits are provided for adjustment of the external gain control on each channel. A 3-wire serial interface (3-bit address and 16-bit data) is included to provide several adjustments: Analog input range adjustment (±1.5 dB) with 8-bit data control using a 3-wire bus interface (steps of 0.18 dB) Analog input switch: both ADCs can convert the same analog input signal I or Q Gray or binary encoder output. Output format: DMUX 1:1 or 1:2 with control of the output frequency on the data ready output signal Partial or full standby on channel I or channel Q Clock selection: – Two independent clocks: CLKI and CLKQ – One master clock (CLKI) with the same phase for channel I and channel Q – One master clock but with two phases (CLKI for channel I and CLKIB for channel Q) ISA: Internal Settling Adjustment on channel I and channel Q FiSDA: Fine Sampling Delay Adjustment on channel Q Adjustable Data Ready Output Delay on both channels Test mode: decimation mode (by 16), Built-In Test. A calibration phase is provided to set the two DC offsets of channel I and channel Q close to code 127.5 and calibrate the two gains to achieve a maximum difference of 0.5 LSB. The offset and gain error can also be set externally via the 3-wire serial interface. The AD84AD001B operates in fully differential mode from the analog inputs up to the digital outputs. The AD84AD001B features a full-power input bandwidth of 1.5 GHz.
Figure 1. Simplified Block Diagram
16 DOAI
4 AT84AD001B
Figure 2. Satellite Receiver Application
Figure 3. Dual Channel Digital Oscilloscope Application within specified operating conditions. Long exposure to maximum ratings may affect device reliability. Table 1. Absolute Maximum Ratings
6 AT84AD001B
Table 2. Recommended Conditions of Use Table 3. Electrical Operating Characteristics in Nominal Conditions
Table 3. Electrical Operating Characteristics in Nominal Conditions (Continued)
8 AT84AD001B
Note: The gain setting is 0 dB, one clock input, no stand by mode [full power mode], 1:1 DMUX, calibration off. Note: Gain setting is 0 dB, two clock inputs, no standb y mode [full power mode], 1:2 DMUX, calibration on. Table 4. Electrical Operating Characteristics
- Measured on the AT84AD001TD-EB Evaluation Board.
Table 5. AC Performances
10 AT84AD001B
phase is necessary. The gain setting is 0 dB, one input clock I, no standby mode, 1:1 DMUX, FiSDA adjustment. Table 6. AC Performances in Interlace Mode
7.1 Bits
Table 7. Switching Performances Switching Performance and Characteristics - See “Timing Diagrams” on page 12.
10 Msps
12 AT84AD001B
Figure 4. Timing Diagram, ADC I or ADC Q, 1:2 DMUX Mode, Clock I for ADC I, Clock Q for ADC Q Figure 5. 1:1 DMUX Mode, Clock I = ADC I, Clock Q = ADC Q
Figure 6. 1:2 DMUX Mode, Clock I = ADC I, Clock I = ADC Q
14 AT84AD001B
Figure 7. 1:1 DMUX Mode, Clock I = ADC I, Clock I = ADC Q
Figure 8. 1:2 DMUX Mode, Clock I = ADC I, Clock IN = ADC Q
0 X X X 1 X 0 0
16 AT84AD001B
Figure 9. 1:1 DMUX Mode, Clock I = ADC I, Clock IN = ADC Q Figure 10. 1:1 DMUX Mode, Decimation Mode Test (1:16 Factor) Notes: 1. The maximum clock input frequency in decimation mode is 750 Msps.
- Frequency(CLKOI) = Frequency(Data) = Frequency(CLKI)/16.
0 X X X 0 X 0 0
18 AT84AD001B
Figure 13. Data Ready Reset 1:2 DMUX Mode clock after reset makes the output clock return to normal mode (after TDR). after reset makes the output clock return to normal mode (after TDR).
Table 8. Description of Functions
20 AT84AD001B
Table 9. Digital Output Coding (Nominal Setting) Table 10. AT84AD001B LQFP 144 Pin Description
Table 10. AT84AD001B LQFP 144 Pin Description (Continued)
22 AT84AD001B
Figure 14. AT84AD001B Pinout (Top View)
Figure 15. Full Power Input Bandwidth
24 AT84AD001B
Note: Measured on the AT84AD001TD-EB Evaluation Board. Figure 17. Typical INL (Fs = 50 Msps, Fin = 1 MHz, Saturated Input)
Figure 18. Typical DNL (Fs = 50 Msps, Fin = 1 MHz, Saturated Input)
26 AT84AD001B
Figure 20. Step Response (Zoom) Figure 21. Step Response
28 AT84AD001B
Figure 25. THD Versus Sampling Frequency in Nyquist Conditions (Fin = Fs/2) Figure 26. SNR Versus Sampling Frequency in Nyquist Conditions (Fin = Fs/2) Figure 27. ENOB Versus Input Frequency (Fs = 1 Gsps)
30 AT84AD001B
Figure 31. Fs = 1 Gsps and Fin = 20 MHz (1:2 DMUX, Fs/2 DR Type, FiSDA = -15 ps, ISA = -50 ps) Figure 32. Fs = 1 Gsps and Fin = 500 MHz (1:2 DMUX, Fs/2 DR Type, FiSDA = -15 ps, ISA = -50 ps) Figure 33. Fs = 1 Gsps and Fin = 1 GHz (1:2 DMUX, Fs/2 DR Type, FiSDA = -15 ps, ISA = -50 ps) Note: The spectra are given with respect to the output clock frequency observed by the acquisition system (Figures 31 to 33).
32 AT84AD001B
Figure 36. ENOB Versus VCCA = VCCD (Fs = 1 Gsps, Fin = 500 MHz, 1:2 DMUX, Figure 37. SFDR Versus VCCA = VCCD (Fs = 1 Gsps, Fin = 500 MHz, 1:2 DMUX,
34 AT84AD001B
Figure 40. ENOB Versus Junction Temperature (Fs = 1 Gsps, 1:2 DMUX, Fs/4 DR Figure 41. SFDR Versus Junction Temperature (Fs = 1 Gsps, 1:2 DMUX, Fs/4 DR
1 Gsps 20 MHz
1 Gsps 502 MHz
1 Gsps 998 MHz
Figure 42. THD Versus Junction Temperature (Fs = 1 Gsps, 1:2 DMUX, Fs/4 DR Figure 43. SNR Versus Junction Temperature (Fs = 1 Gsps, 1:2 DMUX, Fs/4 DR
36 AT84AD001B
Table 11. 3-wire Serial Interface Control Settings
Table 12. 3-wire Serial Interface Address Setting Description
38 AT84AD001B
Nominal mode will be given by Data2…Data0 = 100 or Data5…Data3 = 100. Data5…Data3 = 000 or Data2…Data0 = 000: sampling time is -200 ps compared to nominal. Data2…Data0 = 111 or Data5…Data3 = 111: sampling time is 150 ps compared to nominal. We recommend setting the ISA to -50 ps to optimize the ADC’s dynamic performances.
- The Fine Sampling Delay Adjustment enables you to change the sampling time (steps of ±5 ps) on channel Q more pre-
cisely, particularly in the interleaved mode.
- A Built-In Test (BIT) function is available to rapidly test th e device’s I/O by either applying a defined static pattern to the dual
at the address 110. The maximum clock frequency in dynamic BIT mode is 750 Msps. Please refer to “Built-In Test (BIT)” on page 43 for more information about this function.
- The decimation mode enables you to lower the output bit rate (including the output clock rate) by a factor of 16, while the
internal clock frequency remains unchanged. The maximum clock frequency in decimation mode is 750 Msps.
- The “S/H transparent” mode (address 101, Data4) enables by passing of the ADC’s track/hold. This function optimizes the
ADC’s performances at very low input frequencies (Fin < 50 MHz).
- In the Gray mode, when the input signal is overflow (that is , the differential analog input is greater than 250 mV), the output
In 1:2 DMUX mode, only one out-of-range bit is provided for both A and B ports. Table 12. 3-wire Serial Interface Address Setting Description (Continued)
Table 13. 3-wire Serial Interface Data Setting Description
000 D15 D14 D13 D12 D11 D10 D9 (1) D8 D7 D6 D5 D4 D3 D2 D1 D0
40 AT84AD001B
2153C–BDC–04/04 Notes: 1. D9 must be set to “0” 2. Mode standby channel I: use analog input I Vini, Vinib and Clocki. 3. Mode standby channel Q: use analog input Q Vinq, Vinqb and Clockq. 4. Keep last calibration calculated value - no calibration phase: D11 = 0 and D10 = 1. No new calibration is required. The val- ues taken into account for the gain and offset are either from the last calibration phase or are default values (reset values). 5. No calibration phase - no calibration value: D11 = 0 and D10 = 0. No new calibration phase is required. The gain and offset compensation functions can be accessed externally by writing in the registers at address 010 for the offset compensation and at address 011 for the gain compensation. 6. The control wait bit gives the possibility to change the internal setting for the auto-calibration phase: For high clock rates (> 500 Msps) use a = b = 1. For clock rates > 250 Msps and < 500 Msps use a = 1 and b = 0. For clock rates > 125 Msps and < 250 Msps use a = 0 and b = 1. For low clock rates < 125 Msps use a = 0 and b = 0. 3-wire Serial Interface Timing
Description
The 3-wire serial interface is a synchronous write-only serial interface made of three wires: sclk: serial clock input sldn: serial load enable input sdata: serial data input The 3-wire serial interface gives write-only access to as many as 8 different internal reg- isters of up to 16 bits each. The input format is always fixed with 3 bits of register address followed by 16 bits of data. The data and address are entered with the Most Significant Bit (MSB) first. The write procedure is fully synchronous with the rising clock edge of “sclk” and described in the write chronogram (Figure 44 on page 41). “sldn” and “sdata” are sampled on each rising clock edge of “sclk” (clock cycle). “sldn” must be set to 1 when no write procedure is performed. A minimum of one rising clock edge (clock cycle) with “sldn” at 1 is required for a correct start of the write procedure. A write starts on the first clock cycle with “sldn” at 0. “sldn” must stay at 0 during the complete write procedure. During the first 3 clock cycles with “sldn” at 0, 3 bits of the register address from MSB (a[2]) to LSB (a[0]) are entered. During the next 16 clock cycles with “sldn” at 0, 16 bits of data from MSB (d[15]) to LSB (d[0]) are entered. An additional clock cycle with “sldn” at 0 is required for parallel transfer of the serial data d[15:0] into the addressed register with address a[2:0]. This yields 20 clock cycles with “sldn” at 0 for a normal write procedure. Control wait bit calibration(6) X X a b X X 0 XXXXXXXXX In 1:2 DMUX FDataReady I & Q = Fs/2 X 0 X X X X 0 XXXXXXXXX In 1:2 DMUX FDataReady I & Q = Fs/4 X 1 X X X X 0 XXXXXXXXX Table 13. 3-wire Serial Interface Data Setting Description (Continued)
42 AT84AD001B
performed. The output bit CAL goes to a high level during the entire calibration phase. can be used again for a standard data acquisition. and no gain calibration between the two channels is necessary. Figure 46. Internal Timing Calibration dual clock scheme is used during calibration, ClockQ will not be used. For high clock rates (> 500 Msps) use a = b = 1, Tcal = 10112 clock I periods. For low clock rates (< 125 Msps) use a = 0, b = 0 , Tcal = 2944 clock I periods. Table 14. Timing Description
to “manual” mode by writing 0 at bits D11 and D10 of address 000. 750 Msps. This function is controlled via the 3-wire bus interface at address 101. The BIT is active when Data0 = 1 at address 110. The BIT is inactive when Data0 = 0 at address 110. defining the Data9 to Data2 bits. Port B then outputs an 8-bit pattern equal to Data9 ... Data2, and Port A outputs an 8-bit pattern equal to NOT (Data9 ... Data2). Table 15. Matching Between Channels
44 AT84AD001B
One should then obtain 01010101 on Port B and 10101010 on Port A. a maximum output rate of 46.875 Msps. Note: Frequency (CLKO) = frequency (Data) = Frequency (CLKI)/16. The measurement method forces a 1 mA current into a diode-mounted transistor. Caution should be given to respecting the polarity of the current. The measurement setup is illustrated in Figure 47. Figure 47. Die Junction Temperature Monitoring Setup
46 AT84AD001B
Figure 50. Simplified Data Ready Reset Buffer Model Figure 51. Analog Input Model
Figure 52. Data Output Buffer Model Table 16. Definitions of Terms
48 AT84AD001B
Table 16. Definitions of Terms (Continued)
50 AT84AD001B
schemes for the dual 8-bit 1 Gsps ADC power supplies. Figure 53. VCCD and VCCA Bypassing and Grounding Scheme Figure 54. VCCO Bypassing and Grounding Scheme Note: L and C values must be chosen in accordan ce with the operation frequency of the application. Figure 55. Power Supplies Decoupling Scheme decoupling capacitors (100 pF and 10 nF) should be placed as close as possible to the device.
The analog inputs must be used in differential mode only. Figure 56. Termination Method for the ADC Analog Inputs in DC Coupling Mode
52 AT84AD001B
Figure 57. Termination Method for the ADC Analog Inputs in AC Coupling Mode Figure 58. Each path must be AC coupled with a 100 nF capacitor. Figure 58. Differential Termination Method for Clock I or Clock Q CLKQN signal paths; they may be left floating.
54 AT84AD001B
Figure 60. Example of Termination for Channel I Used in DMUX 1:1 Ratio (Port B Unused) tional DMUXes used to halve the speed of the dual ADC outputs.
Figure 61. Dual ADC and ASIC/FPGA Load Block Diagram Note: The demultiplexers may be in ternal to the ASIC/FPGA system.
56 AT84AD001B
The following model has been extracted from the ANSYS FEM simulations. Assumptions: no air, no convection and no board. Figure 62. Simplified Thermal Model for LQFP Package Note: The above are typical values with an assumption of uniform power dissipation over 2.5 x 2.5 mm 2 of the top surface of the die. Assumptions: no air, no convection and no board. The thermal resistance from the junction to the bottom of the leads is 15.2° C/W typical. Assumptions: no air, no convection and no board. The thermal resistance from the junction to the top of the case is 8.3° C/W typical. Assumptions: no air, no convection and no board. The thermal resistance from the junction to the bottom of the case is 6.4° C/W typical.
2153C–BDC–04/04 Thermal Resistance from Junction to Ambient The thermal resistance from the junction to ambient is 25.2° C/W typical. Note: In order to keep the ambient temperature of the die within the sp ecified limits of the device grade (that is T A max = 70°C in commercial grade and 85°C in industrial grade) and the die junction temperature below the maximum allowed junction temperature of 105°C, it is necessary to operate the dual ADC in air flow conditions (1m/s recom- mended). In still air conditions, the junction temper ature is indeed greater than the maximum allowed TJ. - TJ = 25.2°C/W x 1.4W + TA = 35.28 + 70 = 105.28°C for commercial grade devices - TJ = 25.2°C/W x 1.4W + TA = 35.28 + 85 = 125.28°C for industrial grade devices Thermal Resistance from Junction to Board The thermal resistance from the junction to the board is 13° C/W typical.
58 AT84AD001B
2153C–BDC–04/04
Ordering Information
Part Number Package Temperature Range Screening Comments AT84XAD001BTD LQFP 144 Ambient Prototype Prototype version Please contact your local Atmel sales office AT84AD001BCTD LQFP 144 C grade 0°C < TA < 70°C Standard AT84AD001BITD LQFP 144 I grade -40°C < TA < 85°C Standard AT84AD001TD-EB LQFP 144 Ambient Prototype Evaluation Kit
Figure 63. Type of Package Note: Thermally enhanced package: LQFP 144, 20 x 20 x 1.4 mm.
- Dimensions shown are nominal with tolerances as indicated
- L/F: eftec 64T copper or equivalent
- Foot length: "L" is measured at gauge plane
Printed on recycled paper. 2153C–BDC–04/04 0M Disclaimer: Atmel Corporation makes no warranty for the use of its products , other than those expressly contained in the Company’s standar d warranty which is detailed in Atmel’s Terms and Conditions locat ed on the Company’s web site. The Company assumes no responsibi lity for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time wi thout notice, and does not make any commitment to update the information contained her ein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel produc ts, expressly or by implication. Atmel’s products are not aut horized for use as critical components in life support devices or systems. Atmel Corporation Atmel Operations
2325 Orchard Parkway
San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza
77 Mody Road Tsimshatsui
Tel: (852) 2721-9778 Fax: (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Memory San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 Microcontrollers San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602
44306 Nantes Cedex 3, France
13106 Rousset Cedex, France
1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300 Fax: 1(719) 540-1759 Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 0QR, Scotland Tel: (44) 1355-803-000 Fax: (44) 1355-242-743 RF/Automotive Theresienstrasse 2 Postfach 3535
74025 Heilbronn, Germany
1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300 Fax: 1(719) 540-1759 Biometrics/Imaging/Hi-Rel MPU/ High Speed Converters/RF Datacom Avenue de Rochepleine BP 123
38521 Saint-Egreve Cedex, France
www.atmel.com/literature © Atmel Corporation 2004 . All rights reserved. Atmel ® and combinations thereof are the registered trademarks and Smart ADC ™ is the trade- mark of Atmel Corporation or its subsidiaries. Other terms and product names may be the trademarks of others.