AT83C24 ATMEL | Alldatasheet
Document overview
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Technical content
Features
Smart Card Interface – Compliance with ISO 7816, EMV2000, GIE-CB, GSM and WHQL Standards Card Clock Stop High or Low for Card Power-down Modes Support Synchronous Cards with C4 and C8 Contacts Card Detection and Automatic de-activation Sequence Programmable Activation Sequence – Direct Connection to the Smart Card Logic Level Shifters Short Circuit Current Limitation (see electrical characteristics) 8kV+ ESD Protection (MIL/STD 883 Class 3) – Programmable Voltage 5V ±5% at 65 mA (Class A) 3V ±0.2V at 65 mA (Class B) 1.8V ±0.14V at 40 mA – Low Ripple Noise: < 200 mV Versatile Host Interface – ICAM (Conditional Access) Compatible – Two Wire Interface (TWI) Link Programmable Address Allow up to 8 Devices – Programmable Interrupt Output – Automatic Level Shifter (1.6V to V CC) Reset Output Includes – Power-On Reset (POR) – Power-Fail Detector (PFD) High-efficiency Step-up Converter: 80 to 98% Efficiency Extended Voltage Operation: 3V to 5.5V Low Power Consumption – 180 mA Maximum In-rush Current –3 0 µA Typical Power-down Current (without Smart Card) 4 to 48 MHz Clock Input, 7 MHz Min for Step-up Converter (for AT83C24) 18 to 48MHz Clock input (for AT83C24NDS) Industrial Temperature Range: -40 to +85 °C Packages: SO28 and QFN28
Description
The AT83C24 is a smart card reader interface IC for smart card reader/writer applica- tions such as EFT/POS terminals and set top boxes. It enables the management of any type of smart card from any kind of host. Up to 8 AT83C24 can be connected in parallel using the programmable TWI address. Its high efficiency DC/DC converter, low quiescent current in standby mode makes it particularly suited to low power and portable applications. The reduced bill of material allows reducing significantly the system cost. A sophisticated protection system guar- antees timely and controlled shutdown upon error conditions. The AT83C24NDS is a dedicated version approved by NDS for use with NDS Video- Guard conditional access software in set-top boxes. All AT83C24 datasheet is applicable to AT83C24NDS. The main differences between AT83C24 and AT83C24NDS are listed below: 1/ CLASS A card supplied with CVCC = 4.75 to 5.25V for AT83C24NDS, CLASS A card supplied with CVCC = 4.6 to 5.25V for AT83C24 2/ 18MHz minimum on input clock for AT83C24NDS 3/ Up to 10µF for capacitor connected on CVCC pin for AT83C24, 3.3µF mandatory for AT83C24NDS Smart Card Reader Interface with Power Management AT83C24 AT83C24NDS
2 AT83C24
4234E–SCR–09/04 Acronyms TWI: Two-wire Interface POR: Power On Reset PFD: Power Fail Detect ART: Automatic Reset Transition ATR: Answer To Reset MSB: Most Significant Bit LSB: Least Significant bit SCIB: Smart Card Interface Bus Block Diagram PRES/ INT CLK VSS CRST CPRES CIO, CC4, CC8 CCLK CVCC LI RESET Voltage supervisor POR/PFD TWI Controller Clocks Controller DC/DC Converter Analog Drivers SCL SDA I/O, C4, C8 DVCC EVCC A2/CK, A1/RST, A0/3V, CMDVCC Timer
16 Bits
& Logic Unit CVSS CVCCIN VCC
- SOIC and QFN packages are available for AT83C24 and for AT83C24NDS
Table 1. Ports Description TWI bus slave address selection input. “transparent mode” (see page 18 ). A0/3V is used for hardware activation to select CVCC voltage (3V or 5V). necessary using INT_PULLUP bit (CONFIG4 register). A low level on this pin keeps the AT83C24 under reset even if applied on power-on. starting a new card session.
4 AT83C24
Copy of CIO pin and high level reference for EVCC. An external pull up to EVCC is needed on IO pin. I/O is the reference level for EVCC if EVCC is connected to a capacitor. This feature is unused if EVCC is connected to VCC. Activation/Shutdown of the smart card Interface. VCC is used to power the internal voltage regulators and I/O buffers. current for the charge pump of the DC/DC converter. Table 1. Ports Description (Continued)
CVCC is the programmable voltage output for the Card interface. It must be connected to external decoupling capacitors (see page 35 and page 36). This pin must be connected to CVCC. Is internally generated and used to supply the digital core. EVCC is used to supply the internal level shifters of host interface pins. parallel between EVCC pin and VSS pin. CVSS is used to sink high shunt currents from the external coil.
6 AT83C24
ond, based on a byte-oriented transfer format. Figure 1. Data transfer on TWI bus
in the address byte (A2, A1, A0 bits). has to send the commands to the possible address taken by the device. their address after A2/CK to A0/3V are fixed. Figure 2. Address Byte byte values for read/write operations are listed below. Table 2. Address Byte Values
8 AT83C24
Initializes all the logic and the TWI interface as after a power-up or power-fail reset. If a smart card is active when R ESET falls, a deactivation se quence is performed. ters. This is a five bytes command. Figure 3. Command byte format for Write CONFIG0 command A general call followed by the value 06h has the same effect as a Reset command. Table 3. Write Commands Description
- Write config 0100 A2A1A00 (10 + CONFIG0 6
- Write Timer 0100 A2A1A00 1111 1100 TIMER1 TIMER0
- Write Interface 0100 A2A1A00 (0+INTERFACE 7
1 X0 X X X X
Table 4. Read Command Description Interrupts The PRES/INT behavior depends on IT_SEL bit value (see CONFIG4 register). If IT_SEL= 0, the PRES/INT output is High by default (on chip pull up or open drain).
10 AT83C24
controlled with the CDS[2-0] bits (see CONFIG1 register). CONFIG1 register) controls this feature. CARDDET bit must be set. The inte rnal pull up can be connected. An interrupt can be generated if a card is inserted or extracted (see interrupts §). Figure 4. Card Presence Input
Figure 5. CIO, CC4, CC8 Block Diagram INTERFACE register. This is done automatically during an hardware activation. Their iddle level are 1. With IO high, CIO is pulled up. The same behavior is applicable on C4/ CC4 and C8/ CC8 pins. edges to transfer). With CLK=27MHz, the maximum frequency on this line is 1.5MHz.
- a clock for the CCLK: Four different sources can be used: CLK pin, DCCLK sig-
nal, CARDCK bit or A2/CK pin (in transparent mode).
- a clock for DC/DC converter.
12 AT83C24
Figure 6. Clock Block Diagram with Software Activation (see page 14) Figure 7. Clock Block Diagram with Hardware Activation (see page 14) value. This selection depends of the CRST_SEL bit value (see CONFIG4 register). If the ART bit is reset, CRST pin is driven by CARDRST bit.
14 AT83C24
CARDDET bit must be configured in accordance to the smart card connector polarity. A0/3V is High and 3V (Class B) is A0/3V is Low. programmed voltage (see Electrical Characteristics) and the level on A1/RST is 0. edge on A1/RST pin set the CRST pin. Note: 1. The card must be deactivated to change the voltage. Figure 10. Activation sequence with CMDVCC Note: For NDS applications, the host usually starts activation with A1/RST = 0.
4234E–SCR–09/04 Software Activation (DC/DC Started With Writing in VCARD[1:0] bits) and ART bit = 1 Initial conditions: CARDRST bit = 0, CKSTOP bit =1, IODIS bit = 1. The following sequence can be applied: 1. Card Voltage is set by software to the required value (VCARD[1:0] bits in CONFIG0 register). This writing starts the DC/DC. 2. Wait the end of the DC/DC init with a polling on VCARDOK bit (STATUS reg- ister) or wait for PRES/INT to go Low if enabled (if IT_SEL bit = 0 in CONFIG4 register). When VCARDOK bit is set (by hardware), CARDIO bit should be set by software. 3. CKSTOP, IODIS are programmed by software. CKSTOP bit is reset to have the clock running. IODIS is reset to drive the I/O, C4, C8 pins and the CIO,CC4, CC8 pins according to each other. 4. CARDRST bit (see INTERFACE register) is set by software. Automatic Reset Transition description: A 16-bit counter starts when CARDRST bit is set. It counts card clock cycles. The CRST signal is set when the counter reaches the TIMER[1-0] value which corresponds to the “tb” time (Figure 11).The counter is reseted when the CRST pin is released and it is stopped at the first start bit of the Answer To Request (ATR) on CIO pin. The CIO pin is not checked during the first 200 clock cycles (ta on Figure 11). If the ATR arrives before the counter reaches Timer[1-0] value, the activation sequence fails, the CRST signal is not set and the Capture[1-0] register contains the value of the counter at the arrival of the ATR. If the ATR arrives after the rising edge on CRST pin and before the card clock counter overflows (65535 clock cycles), the activation sequence completes. The Capture[1-0] register contains the value of the counter at the arrival of the ATR (tc time on Figure 11).
16 AT83C24
Figure 11. Software activation with ART bit = 1 Note: Timer[1-0] reset value is 400.
- Card Voltage is set by software to the required value (VCARD[1:0] bits in
CONFIG0 register). This writing starts the DC/DC.
- Wait of the end of the DC/DC init with a polling on VCARDOK bit (STATUS
- CKSTOP, IODIS are programmed by software. CKSTOP bit is reset to have
CIO,CC4, CC8 pins according to each other.
- CRST pin is controlled by software using CARDRST bit (see INTERFACE
Figure 12. Software activation without automatic control (ART bit = 0) if one TWI transfer is not acknowledged during the activation sequence. It is a self-timed sequence which cannot be interrupted when started (see Figure 13).
- T0: CARDRST is cleared, SHUTDOWN bit set.
- T0 + 5 x Td:CARDCK is cleared, CKSTOP, CARDIO and IODIS are set.
- T0 + 6 x Td: CARDIO is cleared.
18 AT83C24
Figure 13. Deactivation Sequence used to deactivate the card by software. shifters adapt the card signals to the smart card voltage selection. and easily connect two AT83C24 devices on the same TWI bus. Figure 14. Transparent Mode Description
4234E–SCR–09/04 Power Modes Two power-down modes are available to re duce the AT83C24 power consumption (see STUTDOWN bit in CONFIG1 register and LP bits in CONFIG3 register). To enter in the mode number 4 (see Table 5), the sequence is the following: – First select the Low-power mode by setting the LP bit – The activation of the SHUTDOWN bit can then be done. The AT83C24 exits Power-down if a software/hardware reset is done or if SHUTDOWN bit is cleared. The AT83C24 is then active immediately. Either a hardware reset or a TWI command clearing the SHUTDOWN bit can cause an exit from Power-down. The internal regist ers retain their value during the shutdown mode. In Power-down mode, the device is sleeping and waiting for a wake up condition. To reduce power consumption, the User should stop the clock on the CLK input after setting the SHUTDOWN bit. The clock can be enabled again just before exiting SHUT- DOWN (at least 10 µs before a START bit on SDA). Power Monitoring The AT83C24 needs only one power supply to run: VCC. If the microcontroller outputs signals with a different electrical level, the host positive supply is connected to EVCC. EVCC and VCC pins can be connected together if they have the same voltage. If EVCC and VCC have different electrical levels: The EVCC pin and RESET pin should be connected with a resistor bridge. RESET pin high level must be higher than VIH (see Table 19). When EVCC drops, RESET pin level drops too. A deactivation sequence starts if a card was active. Table 5. Power Modes Description Step up mode: VCC = 3V, CVCC = 5V, Icard = 65mA Icard = 0 2 0 X 1 11 70 mA Regulator mode: VCC = 5.25V, CVCC = 5V, Icvcc = 65mA 3 0 X X 00 3 mA DC/DC off, CLK = 10MHz, VCC=3V to 5V 4 1 0 X 00 90 µA The TWI interface of the AT83C24 is active but its analog blocs are switched off to reduce the consumption 5 1 1 X 00 30 µA Pulsed mode of the internal 3V logic regulator
20 AT83C24
4234E–SCR–09/04 Then the AT83C24 resets if R ESET pin stays low. If EVCC and VCC have the same value, then they should be connected: The AT83C24 integrates an internal 3V regulator to feed its logic from the VCC sup- ply. The bit powermon allows the user to select if the internal PFD monitors VCC or the internal regulated 3V. If the PFD monitors VCC (POWERMON bit=0), a deacti- vation is performed if VCC falls below VPFDP (see VPFDP value in the datasheet). Same deactivation is performed if the internal 3V falls below VPFDP and POWER- MON bit = 1.
Table 6. CONFIG0 (Config Byte 0) 7-6 1-0 These bits cannot be programmed and are read as 1-0.
5 ATRERR
is received before the overflow of the card clock counter). software for test purpose. The reset value is 0.
4 INSERT
It can be set by software for test purpose.
3 ICARDERR
2 VCARDERR
VCARD[1:0] writing to 1.8V, 3V, 5V starts the DC/DC if a card is detected. VCARD[1:0] writing to 0 stops the DC/DC.
22 AT83C24
Table 7. CONFIG 1 (Config Byte 1) 7 X This bit should not be set.
6 ART
Set this bit to have the CRST pin changed according to activation sequence.
5 SHUTDOWN
Clear this bit to enable VCARD[1:0] selection.
4 CARDDET
CONFIG0) even if no card is inserted or extracted.
3 PULLUP
minimize the number of external components. CC (typically a 1 MΩ resistor). extraction has no effect on PRES/INT pin.
- CCLK must be stopped with CKSTOP bit before switching from CKS = (0, 1, 2, 3, 6,
7) to CKS = (4, 5) or vice versa.
- When DCK = 0, only CKS=4 and CKS=5 are allowed.
- The user can’t directly select A2 or A2/2 after a reset or when switching from CKS =
after A2. To select A2/2, the user should select A2 first and after A2/2. Table 8. CONFIG2 (Config Byte 2) 7 X This bit should not be set. DCCLK is the DC/DC clock. It is the division of CLK input by DCK prescaler. DCCLK must be as close as possible to 4 MHz with a duty cycle of 50%. DCK must be programmed before starting the DC/DC. The other values of CLK are not allowed. DCK has to be properly configured before resetting the STEPREG bit. 3 X This bit should not be set.
24 AT83C24
Table 9. CONFIG3 (Config Byte 3) 0 0 0 EVCC = 0 the regulator is switched off. 1 X X EVCC voltage is the level detected on I/O input pin. internal EVCC regulator to decrease the consumption. inactive until a hardware reset is done.
4 ICCADJ
This bit controls the DC/DC sensitivity to any overflow current . Clear this bit to have a normal configuration. Clear this bit to disable low-power mode during shutdown mode. First select the Low-power mode by setting LP bit. The activation of SHUTDOWN bit can then be done. This bit as no effect when SHUTDOWN bit is cleared. 2 X This bit should not be set. 1 X This bit should not be set. 0 X This bit should not be set.
Table 10. CONFIG4 (Config Byte 4) 7-5 X-X-X These bits should not be set.
4 STEPREG
Clear this bit to enable the automatic step-up converter (CVCC is stable even if VCC is not higher than CVCC). This bit must be set before activating the DC/DC converter if no external coil is present.
3 INT_PULLUP
Set this bit to activate the internal pull-up (connected internally to EVCC) on PRES/INT pin. Clear this bit to deactivate the internal pull-up. PRES/INT is an open drain output with a programmable internal pull up.
2 POWERMON
Set this bit to monitor any glitch on the Digital Supply Voltage (DVCC) of the AT83C24. Clear this bit to monitor any glitch on VCC.
1 IT_SEL
Clear this bit to have all the interrupt sources enabled and active Low. IT_SEL must be set to enable a hardware activation with CMDVCC .
0 CRST_SEL
Set this bit to have the CRST pin driven by hardware through the A1 pin (only with hardware activation). Clear this bit to have the CRST pin driven by software through the CARDRST bit. CRST_SEL must be set when CMDVCC is used (hardware activation).
26 AT83C24
Table 11. INTERFACE (Interface Byte)
0 IODIS CKSTOP CARDRST CARDC8 CARDC4 CARDCK CARDIO
7 0 This bit should not be set.
6 IODIS
5 CKSTOP
mode (GSM) or to drive CCLK by software. Clear this bit to have CCLK running according to CKS. This can be used to activate asynchronous cards.
- CKSTOP must be set before switching on the DC/DC with VCARD[1:0].
4 CARDRST
Set this bit to enter a reset sequence according to ART bit value. Clear this bit to drive a low level on the CRST pin.
3 CARDC8
an input (read in STATUS register). Clear this bit to drive a low level on the CC8 pin (according to IODIS bit value).
2 CARDC4
an input (read in STATUS register). Clear this bit to drive a low level on the CC4 pin (according to IODIS bit value).
1 CARDCK
Set this bit to set a high level on the CCLK pin (according to CKSTOP bit value). Clear this bit to drive a low level on the CCLK pin.
0 CARDIO
an input (read in STATUS register). Clear this bit to drive a low level on the CIO pin (according to IODIS bit value).
Table 12. STATUS (Status Byte)
7 CC8
This bit provides the actual level on the CC8 pin when read.
6 CC4
This bit provides the actual level on the CC4 pin when read.
5 CARDIN
This bit is set when a card is detected.
4 VCARD_OK
voltage range specified by VCARD[1:0] bits. 3 X This bit should not be set.
2 VCARD_INT
This bit is set when VCARD_OK bit is set. This bit is cleared when read by the microcontroller.
1 CRST
This bit provides the actual level on the CRST pin when read.
0 CIO
This bit provides the actual level on the CIO pin when read. Table 13. TIMER 1 (Timer MSB)
28 AT83C24
Table 14. TIMER 0 (Timer LSB) Table 15. CAPTURE 1 (Capture MSB) 7 - 0 bits 15 - 8 See “software activation with ART = 1”, page 15. Table 16. CAPTURE 0 (Capture LSB) 7 - 0 bits 7 - 0 See “software activation with ART = 1”, page 15.
4234E–SCR–09/04
Electrical Characteristics
Absolute Maximum Ratings * () Exposed die attached pad must be soldered to ground Thermal resistor are measured on multilayer PCB with 0 m/s air flow. (*) including shortages between any groups of smart card pins. AC/DC Parameters EVCC connected to host power supply: from 1.6V to 5.5V. TA = -40°C to +85°C; VSS = 0V; VCC = 3V to 5.5V. CLASS A card supplied with CVCC = 4.75 to 5.25V for AT83C24NDS CLASS A card supplied with CVCC = 4.6 to 5.25V for AT83C24 CLASS B card supplied with CVCC = 2.8V to 3.2V CLASS C card supplied with CVCC = 1.68V to 1.92V Thermal resistor of QFN pack- *NOTICE: Stresses at or above those listed under “Absolute Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Power Dissipation value is based on the maxi- mum allowable die temperature and the thermal resistance of the package. Table 17. Core (VCC) trise, tfall VDD rise and fall time 1 µs 600s Not tested. Table 18. Host Interface (I/O, C4, C8, CLK, A2, A1, A0, CMDVCC , PRES/INT)
30 AT83C24
Table 18. Host Interface (I/O, C4, C8, CLK, A2, A1, A0, CMDVCC , PRES/INT) (Continued) Table 19. Host Interface (SCL, SDA, RESET) Table 20. Smart Card Class A
Replacing 3.3µF by 2.2µF in parrallel with 1µF is better for ESR and noise reduction.
4.8 V AT83C24
Table 21. Smart Card Class B
32 AT83C24
Replacing 3.3µF by 2.2µF in parrallel with 1µF is better for ESR and noise reduction. Replacing 3.3µF by 2.2µF in parrallel with 1µF is better for ESR and noise reduction. Table 22. Smart Card Class C Table 23. Smart Card Clock (CCLK pin)
0.12 V/ns
Table 23. Smart Card Clock (CCLK pin) (Continued) Table 24. Smart Card I/O (CIO, CC4, CC8 pins)
34 AT83C24
Table 25. Smart Card RST (CRST pin) Table 26. Card Presence Table 27. TWI (SDA, SCL pins)
Figure 1. Typical Standard Mode Application Diagram for 3 AT83C24 (up to 8 AT83C24 if needed) Note: 1. The external resistor on I/O can be removed if the host pin has an internal resistor.
36 AT83C24
Figure 2. Typical NDS Standard Mode Application Diagram for 1 AT83C24NDS. Note: 1. The external resistor on I/O can be removed if the host pin has an internal resistor.
- The internal pull up on PRES/INT is disabled during reset (recommended external
- Refer to application note for AT83C24NDS software configuration.
4234E–SCR–09/04
Ordering Information
Part Number Supply Voltage Temperature Range Package Packing AT83C24-PRTIL(2) 3V to 5.5V Industrial QFN28 Tray AT83C24-PRRIL(2) 3V to 5.5V Industrial QFN28 Tape&Reel AT83C24-PRTIM(2) 4.00V to 5.5V Industrial QFN28 Tray AT83C24-PRRIM(2) 4.00V to 5.5V Industrial QFN28 Tape&Reel AT83C24-TISIL 3V to 5.5V Industrial SO28 Stick AT83C24-TIRIL 3V to 5.5V Industrial SO28 Tape&Reel AT83C24-TISIM 4.00V to 5.5V Industrial SO28 Stick AT83C24-TIRIM 4.00V to 5.5V Industrial SO28 Tape&Reel AT83C24NDS-PRTIL (1)(2) 3V to 5.5V Industrial QFN28 Tray AT83C24NDS-PRRIL (1)(2) 3V to 5.5V Industrial QFN28 Tape&Reel AT83C24NDS-PRTIM (1)(2) 4.00V to 5.5V Industrial QFN28 Tray AT83C24NDS-PRRIM (1)(2) 4.00V to 5.5V Industrial QFN28 Tape&Reel AT83C24NDS-TISIL (1) 3V to 5.5V Industrial SO28 Stick AT83C24NDS-TIRIL (1) 3V to 5.5V Industrial SO28 Tape&Reel AT83C24NDS-TISIM (1) 4.00V to 5.5V Industrial SO28 Stick AT83C24NDS-TIRIM (1) 4.00V to 5.5V Industrial SO28 Tape&Reel LEAD FREE/ HALOGEN FREE: AT83C24-PRTUL(2) 3V to 5.5V Industrial QFN28 Tray AT83C24-PRRUL(2) 3V to 5.5V Industrial QFN28 Tape&Reel AT83C24-PRTUM(2) 4.00V to 5.5V Industrial QFN28 Tray AT83C24-PRRUM(2) 4.00V to 5.5V Industrial QFN28 Tape&Reel AT83C24-TISUL 3V to 5.5V Industrial SO28 Stick AT83C24-TIRUL 3V to 5.5V Industrial SO28 Tape&Reel AT83C24-TISUM 4.00V to 5.5V Industrial SO28 Stick AT83C24-TIRUM 4.00V to 5.5V Industrial SO28 Tape&Reel AT83C24NDS-PRTUL (1)(2) 3V to 5.5V Industrial QFN28 Tray AT83C24NDS-PRRUL (1)(2) 3V to 5.5V Industrial QFN28 Tape&Reel AT83C24NDS-PRTUM(1)(2) 4.00V to 5.5V Industrial QFN28 Tray
38 AT83C24
4234E–SCR–09/04 Note: 1. Enhanced AC/DC parameters, see first page for differences between AT83C24 and AT83C24NDS. 2. Refer to index mark for proper placement. AT83C24NDS-PRRUM (1)(2) 4.00V to 5.5V Industrial QFN28 Tape&Reel AT83C24NDS-TISUL (1) 3V to 5.5V Industrial SO28 Stick AT83C24NDS-TIRUL (1) 3V to 5.5V Industrial SO28 Tape&Reel AT83C24NDS-TISUM (1) 4.00V to 5.5V Industrial SO28 Stick AT83C24NDS-TIRUM (1) 4.00V to 5.5V Industrial SO28 Tape&Reel Part Number Supply Voltage Temperature Range Package Packing
4234E–SCR–09/04 Package Drawings QFN28
4234E–SCR–09/04 Datasheet Change Log Changes from 4234A- 05/03 to 4234B-02/04 1. Addition of CRST, CIO, CCLK controllers descriptions, page 10. 2. Update of Hardware\\Software activation description, page 14. 3. Suppression of low voltage regulator mode for power down modes, page 19. 4. Modification of clock values in CONFIG2 regsiter, page 22. 5. Addition of a point on QFN pinout view, page2. 6. Update of electrical characteristics, page 29. Changes from 4234B- 02/04 to 4234C - 04/04 1. Addition of references in ordering information 2. Update of EVCC description 3. Update of CARDDET bit and INSERT bit description Changes from 4234C- 04/04 to 4234D - 07/04 1. Update for Rev 4 silicon version (index 4 on component). 2. Software workaround for A2 or A2/2 selection in CKS register. 3. Max speed on IO/CIO transfer 4. New conditions for hardware activation (see IT_SEL). 5. SO28 drawing package (error with SO32). 6. Adjusted electrical parameters for NDS compliance, pages 28, 29, 30. Changes from 4234D- 04/04 to 4234E - 09/04 1. QFN28 new package drawing. 2. Clock input parameters for AT83C24 and AT83C24NDS.
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