AT83C24NDS-PRTUM

AT83C24B_05 ATMEL | Alldatasheet

Document overview

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Technical content

Features

• Smart Card Interface – Compliance with ISO 7816, EMV2000, GIE-CB, GSM and WHQL Standards Card Clock Stop High or Low for Card Power-down Modes Support Synchronous Cards with C4 and C8 Contacts Card Detection and Automatic de-activation Sequence Programmable Activation Sequence – Direct Connection to the Smart Card Logic Level Shifters Short Circuit Current Limitation (see electrical characteristics) 8kV+ ESD Protection (MIL/STD 883 Class 3) – Programmable Voltage 5V ±5% at 65 mA (Class A) 3V ±0.2V at 65 mA (Class B) 1.8V ±0.14V at 40 mA – Low Ripple Noise: < 200 mV
• Versatile Host Interface – ICAM (Conditional Access) Compatible – Two Wire Interface (TWI) Link Programmable Address Allow up to 8 Devices – Programmable Interrupt Output – Automatic Level Shifter (1.6V to VCC)
• Reset Output Includes – Power-On Reset (POR) – Power-Fail Detector (PFD)
• High-efficiency Step-up Converter: 80 to 98% Efficiency
• Extended Voltage Operation: 3V to 5.5V
• Low Power Consumption – 180 mA Maximum In-rush Current – 30 μA Typical Power-down Current (without Smart Card)
• 4 to 48 MHz Clock Input, 7 MHz Min for Step-up Converter (for AT83C24)
• 18 to 48MHz Clock input (for AT83C24NDS)
• Industrial Temperature Range: -40 to +85°C
• Packages: SO28 and QFN28

Description

The AT83C24 is a smart card reader interface IC for smart card reader/writer applica- tions such as EFT/POS terminals and set top boxes. It enables the management of any type of smart card from any kind of host. Up to 8 AT83C24 can be connected in parallel using the programmable TWI address. Its high efficiency DC/DC converter, low quiescent current in standby mode makes it particularly suited to low power and portable applications. The reduced bill of material allows reducing significantly the system cost. A sophisticated protection system guar antees timely and controlled shutdown upon error conditions. The AT83C24NDS is a dedicated version approved by NDS for use with NDS Video - Guard conditional access software in set-top boxes. All AT83C24 datasheet is applicable to AT83C24NDS. The main differences between AT83C24 and AT83C24NDS are listed below: 1/ CLASS A card supplied with CVCC = 4.75 to 5.25V for AT83C24NDS, CLASS A card supplied with CVCC = 4.6 to 5.25V for AT83C24 2/ 18MHz minimum on input clock for AT83C24NDS 3/ Up to 10µF for capacitor connected on CVCC pin for AT83C24, 3.3µF mandatory for AT83C24NDS Smart Card Reader Interface with Power Management AT83C24B AT83C24NDS 4234F–SCR–10/05

4234F–SCR–10/05 AT83C24 Acronyms TWI: Two-wire Interface POR: Power On Reset PFD: Power Fail Detect ART: Automatic Reset Transition ATR: Answer To Reset MSB: Most Significant Bit LSB: Least Significant bit SCIB: Smart Card Interface Bus Block Diagram PRES/ INT CLK VSS CRST CPRES CIO, CC4, CC8 CCLK CVCC LI RESET Voltage supervisor POR/PFD TWI Controller Clocks Controller DC/DC Converter Analog Drivers SCL SDA I/O, C4, C8 DVCC EVCC A2/CK, A1/RST, A0/3V, CMDVCC Timer

16 Bits

& Logic Unit CVSS CVCCIN VCC

1. SOIC and QFN packages are available for AT83C24 and for AT83C24NDS

Table 1. Ports Description TWI bus slave address selection input. “transparent mode” (see page 17 ). A0/3V is used for hardware activation to select CVCC voltage (3V or 5V). necessary using INT_PULLUP bit (CONFIG4 register).

• Power-on reset
• A low level on this pin keeps the AT83C24 under reset even if applied on power-on. It also resets the AT83C24 if applied when the AT83C24 is running (see Power monitoring §).
• Asserting RESET when the chip is in Shut-down mode returns the chip to normal operation.
• AT83C24 is driving the Reset pin Low on power-on-reset or if power fail on VCC or DVCC (see POWERMON bit in CONFIG4 register), this can be used to reset or interrupt other devices. After reset, AT83C24 needs to be reconfigured before starting a new card session.

Copy of CIO pin and high level reference for EVCC. An external pull up to EVCC is needed on IO pin. I/O is the reference level for EVCC if EVCC is connected to a capacitor. This feature is unused if EVCC is connected to VCC. Activation/Shutdown of the smart card Interface. VCC is used to power the internal voltage regulators and I/O buffers. current for the charge pump of the DC/DC converter. Table 1. Ports Description (Continued)

according to Mil/STD 883 Class3. Recommended capacitors soldered on CVCC and VCC pins. CVCC is the programmable voltage output for the Card interface. It must be connected to external decoupling capacitors (see page 34 and page 36). This pin must be connected to CVCC. Is internally generated and used to supply the digital core. EVCC is used to supply the internal level shifters of host interface pins. parallel between EVCC pin and VSS pin. CVSS is used to sink high shunt currents from the external coil.

byte-oriented transfer format. call) but A2/CK, A1/RST, A0/3V can be used for transparent mode after the reset. Figure 1. Data transfer on TWI bus

address byte (A2, A1, A0 bits). the commands to the possible address taken by the device. Figure 2. Address Byte read/write operations are listed below. Table 2. Address Byte Values

Figure 3. Command byte format for Write CONFIG0 command A general call followed by the value 06h has the same effect as a Reset command. Table 3. Write Commands Description

1. Write config 0100 A2A1A00 (10 + CONFIG0 6
2. Write Timer 0100 A2A1A00 1111 1100 TIMER1 TIMER0
3. Write Interface 0100 A2A1A00 (0+INTERFACE 7

1 X0 X X X X

• STATUS, CONFIG0, CONFIG1, CONFIG2, CONFIG3, INTERFACE, TIMER1, TIMER0, CAPTURE1, CAPTURE0
• FFh is completing the transfer if the microcon troller attempts to read beyond the last byte. Note: Flags are only reset after the corresponding byte read has been acknowledged by the master.

Table 4. Read Command Description Interrupts The PRES/INT behavior depends on IT_SEL bit value (see CONFIG4 register).

• If IT_SEL= 0, the PRES/ INT output is High by default (on chip pull up or open drain). PRES/INT is driven Low by any of the following event: – INSERT bit set in CONFIG0 register (card insertion/extraction or bit set by software ) – VCARD_INT bit set in STATUS register (the DC/DC output voltage has settled) – over-current detection on CVCC – VCARDERR bit set in CONFIG0 register (out of range voltage on CVCC or bit set by software) – ATRERR bit set in CONFIG0 register (no ATR before the card clock counter overflows or bit set by software).This control of ATR timing is only available if ART bit =1. If IT_SEL=0, a read command of STATUS register and of CONFIG0 register will release PRES/ INT pin to high level. Several AT83C24 devices can share the same in terrupt and the microcontroller can identify the interrupt sources by polling the status of the AT83C24 devices using TWI commands.
• If IT_SEL= 1 (mandatory for NDS applications and for software compatibility with existing devices) the PRES/INT output is High to indicate a card is present and none of the following event has occured: Byte Description Byte Value Address byte 0100 A2A1A01 Data byte 1 STATUS Data byte 2 CONFIG0 Data byte 3 CONFIG1 Data byte 4 CONFIG2 Data byte 5 CONFIG3 Data byte 6 CONFIG4 Data byte 7 INTERFACE Data byte 8 TIMER 1 (MSB) Data byte 9 TIMER 0 (LSB) Data byte 10 CAPTURE 1 (MSB) Data byte 11 CAPTURE 0 (LSB) Data byte 12 0xFF

with the CDS[2-0] bits (see CONFIG1 register). DET bit must be set. The internal pull up can be connected. An interrupt can be generated if a card is inserted or extracted (see interrupts §). Figure 4. Card Presence Input

reset, data are bidirectional between respectively I/O, C4, C8 pins and CIO, CC4, CC8 pins. Figure 5. CIO, CC4, CC8 Block Diagram FACE register. This is done automatically during an hardware activation. Their iddle level are 1. With IO high, CIO is pulled up. The same behavior is applicable on C4/ CC4 and C8/ CC8 pins. transfer). With CLK=27MHz, the maximum frequency on this line is 1.5MHz.

1. a clock for the CCLK: Four different sources can be used: CLK pin, DCCLK signal,

CARDCK bit or A2/CK pin (in transparent mode).

1. a clock for DC/DC converter.

CARDDET bit must be configured in accordance to the smart card connector polarity.

• CIO / CC4 / CC8 and IO / C4 / C8 are respective ly linked together (IODIS bit is cleared).
• The DC/DC is started and CVCC is set according to the A0/3V pin: 5V (Class A) if A0/3V is High and 3V (Class B) is A0/3V is Low.
• CCLK signal is enabled (CKSTOP bit cleared) when CVCC has settled to the programmed voltage (see Electrical Characteristics) and the level on A1/RST is 0. The CCLK source can be DCCLK signal, CLK signal , A2/CK signals or CARDCK bit (see Figures 5).
• CRST signal is linked with A1/RST pin as soon as A1/RST pin level is 0. A rising edge on A1/RST pin set the CRST pin. Note: 1. The card must be deactivated to change the voltage.

Figure 10. Activation sequence with CMDVCC Note: For NDS applications, the host usually starts activation with A1/RST = 0.

Initial conditions: CARDRST bit = 0, CKSTOP bit =1, IODIS bit = 1.

1. Card Voltage is set by so ftware to the required value (VCARD[1:0] bits in CONFIG0

register). This writing starts the DC/DC.

1. Wait the end of the DC/DC init with a polling on VCARDOK bit (STATUS register) or

wait for PRES/INT to go Low if enabled (if IT_SEL bit = 0 in CONFIG4 register). When VCARDOK bit is set (by hardware), CARDIO bit should be set by software.

1. CKSTOP , IODIS are programmed by software. CKSTOP bit is reset to have the

pins according to each other.

1. CARDRST bit (see INTERFACE register) is set by software.

the Answer To Request (ATR) on CIO pin. not set and the Capture[1-0] register contains the value of the counter at the arrival of the ATR. value of the counter at the arrival of the ATR (tc time on Figure 11). Figure 11. Software activation with ART bit = 1

Note: Timer[1-0] reset value is 400.

1. Card Voltage is set by so ftware to the required value (VCARD[1:0] bits in CONFIG0

register). This writing starts the DC/DC.

1. Wait of the end of the DC/DC init with a polling on VCARDOK bit (STATUS register)

or wait for PRES/INT to go Low if enabled (if IT_SEL bit = 0 in CONFIG4 register). When VCARDOK bit is set (by hardware), CARDIO bit should be set by software.

1. CKSTOP , IODIS are programmed by software. CKSTOP bit is reset to have the

pins according to each other.

1. CRST pin is controlled by software using CARDRST bit (see INTERFACE register).

Figure 12. Software activation without automatic control (ART bit = 0) TWI transfer is not acknowledged during the activation sequence.

• ICARDERR bit is set by hardware CVCC CRST CCLK CIO ATR

• VCARDERR bit is set by ha rdware (or by software)
• INSERT is set and CARDIN is cleared (card extraction)
• SHUTDOWN is set by software
• CMDVCC goes from Low to High
• Power fail on VCC (see POWE RMON bit in CONFIG4 register)
• Reset pin going low It is a self-timed sequence which cannot be interrupted when started (see Figure 13). Each step is separated by a delay based on Td equal to 8 periods of the DC/DC clock, typically 2 µs: 1. T0: CARDRST is cleared, SHUTDOWN bit set. 2. T0 + 5 x Td:CARDCK is cleared, CKSTOP , CARDIO and IODIS are set. 3. T0 + 6 x Td: CARDIO is cleared. 4. T0 + 7 x Td: VCARD[1-0] = 00.

Figure 13. Deactivation Sequence deactivate the card by software. signals to the smart card voltage selection. devices on the same TWI bus.

4234F–SCR–10/05 AT83C24 Figure 14. Transparent Mode Description DOWN bit in CONFIG1 register and LP bits in CONFIG3 register). – The activation of the SHUTDOWN bit can then be done. cleared. The AT83C24 is then active immediately. Power-down. The internal registers retain their value during the shutdown mode. In Power-down mode, the device is sleeping and waiting for a wake up condition. µs before a START bit on SDA). Table 5. Power Modes Description Step up mode: VCC = 3V, CVCC = 5V, Icard = 65mA Icard = 0 2 0 X 1 11 70 mA Regulator mode: VCC = 5.25V, CVCC = 5V, Icvcc = 65mA 3 0 X X 00 3 mA DC/DC off, CLK = 10MHz, VCC=3V to 5V 4 1 0 X 00 90 µA The TWI interface of the AT83C24 is active but its analog blocs are switched off to reduce the consumption 5 1 1 X 00 30 µA Pulsed mode of the internal 3V logic regulator

4234F–SCR–10/05 AT83C24 Power Monitoring The AT83C24 needs only one power supply to run: VCC. If the microcontroller outputs signal s with a different electrical leve l, the host positive supply is connected to EVCC. EVCC and VCC pins can be connected together if they have the same voltage.

• If EVCC and VCC have different electrical levels: The EVCC pin and RESET pin shou ld be connected with a resist or bridge. RESET pin high level must be higher than VIH (see Table 19) . When EVCC drops, RESET pin level drops too. A deactivation sequence starts if a card was active. Then the AT83C24 resets if RESET pin stays low.
• If EVCC and VCC have the same value, then they should be connected: The AT83C24 integrates an internal 3V regulator to feed its logic from the VCC supply. The bit powermon allows the user to select if the internal PFD monitors VCC or the internal regu- lated 3V. If the PFD monitors VCC (POWERMON bit=0), a deactivation is performed if VCC falls below VPFDP (see VPFDP value in the dat asheet). Same deactivation is performed if the internal 3V falls below VPFDP and POWERMON bit = 1.

Table 6. CONFIG0 (Config Byte 0) 7-6 1-0 These bits cannot be programmed and are read as 1-0.

5 ATRERR

is received before the overflow of the card clock counter). software for test purpose. The reset value is 0.

4 INSERT

It can be set by software for test purpose.

3 ICARDERR

2 VCARDERR

VCARD[1:0] writing to 1.8V, 3V, 5V starts the DC/DC if a card is detected. VCARD[1:0] writing to 0 stops the DC/DC.

Table 7. CONFIG 1 (Config Byte 1) 7 X This bit should not be set.

6 ART

Set this bit to have the CRST pin changed according to activation sequence.

5 SHUTDOWN

Clear this bit to enable VCARD[1:0] selection.

4 CARDDET

CONFIG0) even if no card is inserted or extracted.

3 PULLUP

minimize the number of external components. connected to VCC (typically a 1 MΩ resistor). extraction has no effect on PRES/INT pin.

actual configuration changes can be delayed by half a period to two periods of CCLK.

1. CCLK must be stopped with CKSTOP bit before s witching from CKS = (0, 1, 2, 3, 6, 7) to CKS
2. When DCK = 0, only CKS=4 and CKS=5 are allowed.
3. The user can’t directly select A2 or A2/2 after a reset or when switching from CKS = (0, 1, 2, 3,

A2/2, the user should select A2 first and after A2/2. Table 8. CONFIG2 (Config Byte 2) 7 X This bit should not be set. DCCLK is the DC/DC clock. It is the division of CLK input by DCK prescaler. DCCLK must be as close as possible to 4 MHz with a duty cycle of 50%. DCK must be programmed before starting the DC/DC. The other values of CLK are not allowed. DCK has to be properly configured before resetting the STEPREG bit. 3 X This bit should not be set.

Table 9. CONFIG3 (Config Byte 3) 0 0 0 EVCC = 0 the regulator is switched off. 1 X X EVCC voltage is the level detected on I/O input pin. internal EVCC regulator to decrease the consumption. inactive until a hardware reset is done.

4 ICCADJ

This bit controls the DC/DC sensitivity to any overflow current . Clear this bit to have a normal configuration. Clear this bit to disable low-power mode during shutdown mode.

• First select the Low-power mode by setting LP bit.
• The activation of SHUTDOWN bit can then be done. This bit as no effect when SHUTDOWN bit is cleared. The reset value is 0. 2 X This bit should not be set. 1 X This bit should not be set. 0 X This bit should not be set.

Table 10. CONFIG4 (Config Byte 4) 7-5 X-X-X These bits should not be set.

4 STEPREG

Clear this bit to enable the automatic step-up converter (CVCC is stable even if VCC is not higher than CVCC). This bit must be set before activating the DC/DC converter if no external coil is present.

3 INT_PULLUP

Set this bit to activate the internal pull-up (connected internally to EVCC) on PRES/INT pin. Clear this bit to deactivate the internal pull-up. PRES/INT is an open drain output with a programmable internal pull up.

2 POWERMON

Set this bit to monitor any glitch on the Digital Supply Voltage (DVCC) of the AT83C24. Clear this bit to monitor any glitch on VCC.

1 IT_SEL

Clear this bit to have all the interrupt sources enabled and active Low. IT_SEL must be set to enable a hardware activation with CMDVCC.

0 CRST_SEL

Set this bit to have the CRST pin driven by hardware through the A1 pin (only with hardware activation). Clear this bit to have the CRST pin driven by software through the CARDRST bit. CRST_SEL must be set when CMDVCC is used (hardware activation).

Table 11. INTERFACE (Interface Byte)

0 IODIS CKSTOP CARDRST CARDC8 CARDC4 CARDCK CARDIO

7 0 This bit should not be set.

6 IODIS

5 CKSTOP

mode (GSM) or to drive CCLK by software. Clear this bit to have CCLK running according to CKS. This can be used to activate asynchronous cards.

1. CKSTOP must be set before swit ching on the DC/DC with VCARD[1:0].

4 CARDRST

Set this bit to enter a reset sequence according to ART bit value. Clear this bit to drive a low level on the CRST pin.

3 CARDC8

an input (read in STATUS register). Clear this bit to drive a low level on the CC8 pin (according to IODIS bit value).

2 CARDC4

an input (read in STATUS register). Clear this bit to drive a low level on the CC4 pin (according to IODIS bit value).

1 CARDCK

Set this bit to set a high level on the CCLK pin (according to CKSTOP bit value). Clear this bit to drive a low level on the CCLK pin.

0 CARDIO

an input (read in STATUS register). Clear this bit to drive a low level on the CIO pin (according to IODIS bit value).

Table 12. STATUS (Status Byte)

7 CC8

This bit provides the actual level on the CC8 pin when read.

6 CC4

This bit provides the actual level on the CC4 pin when read.

5 CARDIN

This bit is set when a card is detected.

4 VCARD_OK

voltage range specified by VCARD[1:0] bits. 3 X This bit should not be set.

2 VCARD_INT

This bit is set when VCARD_OK bit is set. This bit is cleared when read by the microcontroller.

1 CRST

This bit provides the actual level on the CRST pin when read.

0 CIO

This bit provides the actual level on the CIO pin when read. Table 13. TIMER 1 (Timer MSB)

Table 14. TIMER 0 (Timer LSB) Table 15. CAPTURE 1 (Capture MSB) 7 - 0 bits 15 - 8 See “software activation with ART = 1”, page 15. Table 16. CAPTURE 0 (Capture LSB) 7 - 0 bits 7 - 0 See “software activation with ART = 1”, page 15.

4234F–SCR–10/05 AT83C24

Electrical Characteristics

Absolute Maximum Ratings * () Exposed die attached pad must be soldered to ground Thermal resistor are measured on multilayer PCB with 0 m/s air flow. (*) including shortages between any groups of smart card pins. AC/DC Parameters EVCC connected to host power supply: from 1.6V to 5.5V. TA = -40°C to +85°C; VSS = 0V; VCC = 3V to 5.5V. CLASS A card supplied with CVCC = 4.75 to 5.25V for AT83C24NDS CLASS A card supplied with CVCC = 4.6 to 5.25V for AT83C24 CLASS B card supplied with CVCC = 2.8V to 3.2V CLASS C card supplied with CVCC = 1.68V to 1.92V Thermal resistor of QFN pack- *NOTICE: Stresses at or above those listed under “Absolute Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Power Dissipation value is based on the maxi- mum allowable die temperature and the thermal resistance of the package. Table 17. Core (VCC) trise, tfall VDD rise and fall time 1 μs 600s Not tested. Table 18. Host Interface (I/O, C4, C8, CLK, A2, A1, A0, CMDVCC, PRES/INT)

Table 18. Host Interface (I/O, C4, C8, CLK, A2, A1, A0, CMDVCC, PRES/INT) (Continued) Table 19. Host Interface (SCL, SDA, RESET) Table 20. Smart Card Class A

Replacing 3.3µF by 2.2µF in parrallel with 1µF is better for ESR and noise reduction.

4.8 V AT83C24

Table 21. Smart Card Class B

Replacing 3.3µF by 2.2µF in parrallel with 1µF is better for ESR and noise reduction. Replacing 3.3µF by 2.2µF in parrallel with 1µF is better for ESR and noise reduction. Table 22. Smart Card Class C Table 23. Smart Card Clock (CCLK pin)

0.12 V/ns

Table 23. Smart Card Clock (CCLK pin) (Continued) Table 24. Smart Card I/O (CIO, CC4, CC8 pins)

Table 25. Smart Card RST (CRST pin) Table 26. Card Presence Table 27. TWI (SDA, SCL pins)

Figure 1. Typical Standard Mode Application Diagram for 3 AT83C24 (up to 8 AT83C24 if needed) Note: 1. The external resistor on I/O can be removed if the host pin has an internal resistor.

Figure 2. Typical NDS Standard Mode Application Diagram for 1 AT83C24NDS. Note: 1. The external resistor on I/O can be remo ved if the host pin has an internal resistor.

1. The internal pull up on PRES/INT is disabled during reset (recommended external 20kOhms
2. Refer to application note for AT83C24NDS software configuration.

4234F–SCR–10/05 AT83C24

Ordering Information

Part Number Supply Voltage Temperature Range Package Packing AT83C24B-PRTIL(2) 3V to 5.5V Industrial QFN28 Tray AT83C24B-PRRIL(2) 3V to 5.5V Industrial QFN28 Tape&Reel AT83C24B-PRTIM(2) 4.00V to 5.5V Industrial QFN28 Tray AT83C24B-PRRIM(2) 4.00V to 5.5V Industrial QFN28 Tape&Reel AT83C24B-TISIL 3V to 5.5V Industrial SO28 Stick AT83C24B-TIRIL 3V to 5.5V Industrial SO28 Tape&Reel AT83C24B-TISIM 4.00V to 5.5V Industrial SO28 Stick AT83C24B-TIRIM 4.00V to 5.5V Industrial SO28 Tape&Reel AT83C24NDS-PRTIL (1)(2) 3V to 5.5V Industrial QFN28 Tray AT83C24NDS-PRRIL (1)(2) 3V to 5.5V Industrial QFN28 Tape&Reel AT83C24NDS-PRTIM (1)(2) 4.00V to 5.5V Industrial QFN28 Tray AT83C24NDS-PRRIM (1)(2) 4.00V to 5.5V Industrial QFN28 Tape&Reel AT83C24NDS-TISIL (1) 3V to 5.5V Industrial SO28 Stick AT83C24NDS-TIRIL (1) 3V to 5.5V Industrial SO28 Tape&Reel AT83C24NDS-TISIM (1) 4.00V to 5.5V Industrial SO28 Stick AT83C24NDS-TIRIM (1) 4.00V to 5.5V Industrial SO28 Tape&Reel AT83C24B-PRTUL(2) 3V to 5.5V Industrial & Green QFN28 Tray AT83C24B-PRRUL(2) 3V to 5.5V Industrial & Green QFN28 Tape&Reel AT83C24B-PRTUM(2) 4.00V to 5.5V Industrial & Green QFN28 Tray AT83C24B-PRRUM(2) 4.00V to 5.5V Industrial & Green QFN28 Tape&Reel AT83C24B-TISUL 3V to 5.5V Industrial & Green SO28 Stick AT83C24B-TIRUL 3V to 5.5V Industrial & Green SO28 Tape&Reel AT83C24B-TISUM 4.00V to 5.5V Industrial & Green SO28 Stick AT83C24B-TIRUM 4.00V to 5.5V Industrial & Green SO28 Tape&Reel AT83C24NDS-PRTUL (1)(2) 3V to 5.5V Industrial & Green QFN28 Tray AT83C24NDS-PRRUL (1)(2) 3V to 5.5V Industrial & Green QFN28 Tape&Reel AT83C24NDS-PRTUM(1)(2) 4.00V to 5.5V Industrial & Green QFN28 Tray AT83C24NDS-PRRUM (1)(2) 4.00V to 5.5V Industrial & Green QFN28 Tape&Reel

4234F–SCR–10/05 AT83C24 Note: 1. Enhanced AC/DC parameters, see first page for differences between AT83C24 and AT83C24NDS. 2. Refer to index mark for proper placement. AT83C24NDS-TISUL (1) 3V to 5.5V Industrial & Green SO28 Stick AT83C24NDS-TIRUL (1) 3V to 5.5V Industrial & Green SO28 Tape&Reel AT83C24NDS-TISUM (1) 4.00V to 5.5V Industrial & Green SO28 Stick AT83C24NDS-TIRUM (1) 4.00V to 5.5V Industrial & Green SO28 Tape&Reel Part Number Supply Voltage Temperature Range Package Packing

4234F–SCR–10/05 AT83C24 Package Drawings QFN28

4234F–SCR–10/05 AT83C24 Datasheet Change Log Changes from 4234A-05/03 to 4234B-02/04 1. Addition of CRST, CIO, CCLK controllers descriptions, page 10. 2. Update of Hardware\\Software activation description, page 14. 3. Suppression of low voltage regulator mode for power down modes, page 18. 4. Modification of clock values in CONFIG2 regsiter, page 22. 5. Addition of a point on QFN pinout view, page2. 6. Update of electrical characteristics, page 28. Changes from 4234B-02/04 to 4234C - 04/04 1. Addition of references in ordering information 2. Update of EVCC description 3. Update of CARDDET bit and INSERT bit description Changes from 4234C-04/04 to 4234D - 07/04 1. Update for Rev 4 silicon version (index 4 on component). 2. Software workaround for A2 or A2/2 selection in CKS register. 3. Max speed on IO/CIO transfer 4. New conditions for hardware activation (see IT_SEL). 5. SO28 drawing package (error with SO32). 6. Adjusted electrical parameters for NDS compliance, pages 28, 29, 30. Changes from 4234D-04/04 to 4234E - 09/04 1. QFN28 new package drawing. 2. Clock input parameters for AT83C24 and AT83C24NDS. Changes from 4234E - 09/04 to 4234F - 10/05 1. Updated green product ordering information.

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