Microcontroller

AT80C51RD2-3CSIM

ATMEL Corporation

80C51 High Performance ROM 8-bit Microcontroller

Manufacturer: ATMEL Corporation

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Features

80C52 Compatible – Four 8-bit I/O Ports – Three 16-bit Timer/Counters – 256 Bytes Scratch Pad RAM – 8 Interrupt Sources with 4 Priority Levels – Dual Data Pointer Variable Length MOVX for Slow RAM/Peripherals High-speed Architecture – 10 to 40 MHz in Standard Mode 16K/32K Bytes On-Chip ROM Program T80C51RD2 ROMless Versions On-Chip 1024 bytes Expanded RAM (XRAM) – Software Selectable Size (0, 256, 512, 768, 1024 bytes) – 256 Bytes Selected at Reset for AT87C51RB2/RC2 Compatibility Keyboard Interrupt Interface on Port P1 8-bit Clock Prescaler 64K Program and Data Memory Spaces Improved X2 Mode with Independant Selection for CPU and Each Peripheral Programmable Counter Array 5 Channels with: – High-speed Output – Compare/Capture – Pulse Width Modulator – Watchdog Timer Capabilities Asynchronous Port Reset Full Duplex Enhanced UART Dedicated Baud Rate Generator for UART Low EMI (Inhibit ALE) Hardware Watchdog Timer (One-time Enabled with Reset-out) Power Control Modes –I d l e M o d e – Power-down Mode – Power-off Flag Power Supply: 2.7V to 5.5V or 2.7V to 3.6V Temperature Ranges: Commercial (0 to +70°C) and Industrial (-40°C to +85°C) Packages: PDIL40, PLCC44, VQFP44

Description

AT8xC51Rx2 microcontrollers are high performance ROM versions of the 80C51 8-bit microcontrollers. They contain a 0K, 16K or 32K bytes ROM memory block for program. The microcontrollers retain all features of the Atmel 80C52 with 256 bytes of internal RAM, a 7-source 4-level interrupt controller and three timer/counters. In addition, the microcontrollers have a Programmable Counter Array, an XRAM of 1024 byte, a Hardware Watchdog Timer, a Keyboard Interface, a more versatile serial channel that facilitates multiprocessor communication (EUART) and a speed improve- ment mechanism (X2 mode). The microcontrollers have 2 software-selec table modes of reduc ed activity and 8 bit clock prescaler for further reduction in power consumption. In Idle mode, the CPU is frozen while the peripherals and the interrupt system are still operating. In the Power- down mode, the RAM is saved and all other functions are inoperative. 80C51 High Performance ROM 8-bit Microcontroller AT80C51RD2 AT83C51RB2 AT83C51RC2

2 AT80C51RD2/AT83C51Rx2

Table 1. Memory Size

Alternate function of Port 3

4113B–8051–03/05 Pin Configurations P1.7CEX4 P1.4/CEX1 RST P3.0/RxD P3.1/TxD P1.3CEX0 P1.5/CEX2 P1.6/CEX3 P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD XTAL2 XTAL1 VSS P2.0/AD8 P2.1/AD9 P2.2/AD10 P2.3/AD11 P2.4/AD12 P0.4/AD4 P0.6/AD6 P0.5/AD5 P0.7/AD7 ALE/PROG PSEN EA P2.7/AD15 P2.5/AD13 P2.6/AD14 P1.0/T2 P1.2/ECI P1.1/T2EX VCC P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 PDIL40 43 42 41 40 3944 38 37 36 35 34 P1.4/CEX1 P1.0/T2 P1.1/T2EX P1.3/CEX0 P1.2/ECI NIC* VCC P0.0/AD0 P0.2/AD2 P0.3/AD3 P0.1/AD1 P0.4/AD4 P0.6/AD6 P0.5/AD5 P0.7/AD7 ALE/PROG PSEN EA NIC* P2.7/A15 P2.5/A13 P2.6/A14 P1.5/CEX2 P1.6/CEX3 P1.7/CEX4 RST P3.0/RxD NIC* P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD XTAL2 XTAL1 VSS P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 NIC* 12 13 17 161514 20 1918 21 22 VQFP44 1.4 18 19 23 222120 26 2524 27 28 5 4 3 2 1 6 44 43 42 41 40 P1.4/CEX1 P1.0/T2 P1.1/T2EX P1.3/CEX0 P1.2/ECI NIC* VCC P0.0/AD0 P0.2/AD2 P0.1/AD1 P0.4/AD4 P0.6/AD6 P0.5/AD5 P0.7/AD7 ALE/PROG PSEN EA NIC* P2.7/A15 P2.5/A13 P2.6/A14 P3.6/WR P3.7/RD XTAL2 XTAL1 VSS P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P1.5/CEX2 P1.6/CEX3 P1.7/CEx4 RST P3.0/RxD NIC* P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P0.3/AD3 NIC* PLCC44 *NIC: No Internal Connection

4 AT80C51RD2/AT83C51Rx2

Table 2. Pin Description emitting 1s. Port 0 also inputs the code bytes during EPROM programming. byte during memory programming and verification.

that use 8-bit addresses (MOVX @Ri), Port 2 emits the contents of the P2 SFR. the 80C51 family, as listed below. watchdog forces a system reset. bit. With this bit set, ALE will be inactive during internal fetches. Table 2. Pin Description (Continued)

4113B–8051–03/05 SFR Mapping The Special Function Registers (SFRs) of the microcontroller fall into the following categories: C51 core registers: ACC, B, DPH, DPL, PSW, SP I/O port registers: P0, P1, P2, P3 Timer registers: T2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2, RCAP2L, RCAP2H Serial I/O port registers: SADDR, SADEN, SBUF, SCON PCA (Programmable Counter Array) registers: CCON, CCAPMx, CL, CH, CCAPxH, CCAPxL (x: 0 to 4) Power and clock control registers: PCON Hardware Watchdog Timer registers: WDTRST, WDTPRG Interrupt system registers: IE0, IPL0, IPH0, IE1, IPL1, IPH1 Keyboard Interface registers: KBE, KBF, KBLS BRG (Baud Rate Generator) registers: BRL, BDRCON Clock Prescaler register: CKRL Others: AUXR, AUXR1, CKCON0, CKCON1

8 AT80C51RD2/AT83C51Rx2

Table 3 shows all SFRs with their address and their reset value. Table 3. SFR Mapping

4113B–8051–03/05 Oscillators Overview One oscillator is available for CPU: OSC used for high frequency (3 MHz to 40 MHz) In order to optimize the power consumption and the execution time needed for a specific task, an internal prescaler feature has been implemented between the selected oscilla- tor and the CPU. Registers Table 4. Clock Reload Register Reset Value = 1111 1111b Not bit addressable Prescaler Divider A hardware RESET puts the prescaler divider in the following state: CKRL = FFh: F CLK CPU = FCLK PERIPH = FOSC/2 (Standard C51 feature) KS signal selects OSC: FCLK OUT = FOSC Any value between FFh down to 00h can be written by software into CKRL register in order to divide frequency of the selected oscillator: – CKRL = 00h: minimum frequency FCLK CPU = FCLK PERIPH = FOSC/1020 (Standard Mode) FCLK CPU = FCLK PERIPH = FOSC/510 (X2 Mode) – CKRL = FFh: maximum frequency FCLK CPU = FCLK PERIPH = FOSC/2 (Standard Mode) FCLK CPU = FCLK PERIPH = FOSC (X2 Mode) –F CLK CPU and FCLK PERIPH In X2 mode: In X1 mode: 76543210 Bit Number Bit Mnemonic Description 7:0 CKRL Clock Reload Register: Prescaler value FCPU F= CLKPERIPH FOSC FCPU F= CLKPERIPH FOSCA

10 AT80C51RD2/AT83C51Rx2

Divides frequency crystals by 2 (cheaper crystals) while keeping same CPU power. Increases CPU power by 2 while keeping same crystal frequency. by the CPU core and the peripherals. bypassed, the signals on XTAL1 must have a cyclic ratio between 40 to 60%. shows the switching mode waveforms. Figure 2. Clock Generation Diagram

Figure 3. Mode Switching Waveforms the X2 bit activates the X2 feature (X2 mode). eral clock cycle) to fast peripheral speed (6 clock periods per peripheral clock cycle). These bits are active only in X2 mode.

12 AT80C51RD2/AT83C51Rx2

Table 5. CKCON0 Register when X2 is low, this bit has no effect). Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. CPU clock X2 is set; when X2 is low, this bit has no effect). Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. CPU clock X2 is set; when X2 is low, this bit has no effect). Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. X2 is low, this bit has no effect). Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. X2 is low, this bit has no effect). Cleared to select 6 clock periods per peripheral clock cycle. X2 is low, this bit has no effect). Cleared to select 6 clock periods per peripheral clock cycle. individual peripherals "X2" bits.

code to switch between them (Refer to Figure 4). Figure 4. Use of Dual Pointer Table 6. AUXR1 Register Note: 1. Bit 2 stuck at 0; this allows to use INC AUXR1 to toggle DPS without changing GF3. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. 3 GF3 This bit is a gener al purpose user flag. The value read from this bit is indeterminate. Do not set this bit.

14 AT80C51RD2/AT83C51Rx2

4113B–8051–03/05 Assembly Language ; Block move using dual data pointers ; Modifies DPTR0, DPTR1, A and PSW ; note: DPS exits opposite of entry state ; unless an extra INC AUXR1 is added 00A2 AUXR1 EQU 0A2H 0000 909000MOV DPTR,#SOURCE ; address of SOURCE 0003 05A2 INC AUXR1 ; switch data pointers 0005 90A000 MOV DPTR,#DEST ; address of DEST

0008 LOOP:

0008 05A2 INC AUXR1 ; switch data pointers 000A E0 MOVX A,@DPTR ; get a byte from SOURCE 000B A3 INC DPTR ; increment SOURCE address 000C 05A2 INC AUXR1 ; switch data pointers 000E F0 MOVX @DPTR,A ; write the byte to DEST 000F A3 INC DPTR ; increment DEST address 0010 70F6JNZ LOOP ; check for 0 terminator 0012 05A2 INC AUXR1 ; (optional) restore DPS INC is a short (2 bytes) and fast (12 clocks) way to manipulate the DPS bit in the AUXR1 SFR. However, note that the INC instruction does not directly force the DPS bit to a par- ticular state, but simply toggles it. In simple routines, such as the block move example, only the fact that DPS is toggled in the proper sequence matters, not its actual value. In other words, the block move routine works the same whether DPS is '0' or '1' on entry. Observe that without the last instruction (INC AUXR1), the routine will exit with DPS in the opposite state.

space for increased data parameter handling and high level language usage. Table 7. Expanded RAM The T8xc51Rx2 has internal data memory that is mapped into four separate segments.

The Lower 128 bytes of RAM (addresses 00h to 7Fh) are directly and indirectly
The Upper 128 bytes of RAM (addresses 80h to FFh) are indirectly addressable
The Special Function Registers (SFRs) (addresses 80h to FFh) are directly
The expanded RAM bytes are indirectly accessed by MOVX instructions, and

with the EXTRAM bit cleared in the AUXR register (see Table 7). physically separate from SFR space. Figure 5. Internal and External Data Memory Address

128 Bytes

16 AT80C51RD2/AT83C51Rx2

4113B–8051–03/05 When an instruction accesses an internal location above address 7Fh, the CPU knows whether the access is to the upper 128 bytes of data RAM or to SFR space by the addressing mode used in the instruction. Instructions that use direct addressing access SFR space. For example: MOV 0A0H, # data, accesses the SFR at location 0A0h (which is P2). Instructions that use indirect addressing access the Upper 128 bytes of data RAM. For example: MOV @R0, # data where R0 contains 0A0h, accesses the data byte at address 0A0h, rather than P2 (whose address is 0A0h). The XRAM bytes can be accessed by indirect addressing, with EXTRAM bit cleared and MOVX instructions. This part of memory which is physically located on-chip, logically occupies the first bytes of external data memory. The bits XRS0 and XRS1 are used to hide a part of the available XRAM as explained in Table 7. This can be useful if external peripherals are mapped at addresses already used by the internal XRAM. With EXTRAM = 0, the XRAM is indirectly addressed, using the MOVX instruction in combination with any of the registers R0, R1 of the selected bank or DPTR. An access to XRAM will not affect ports P0, P2, P3.6 (WR) and P3.7 (RD). For example, with EXTRAM = 0, MOVX @R0, # data where R0 contains 0A0H, accesses the XRAM at address 0A0H rather than external memory. An access to external data memory locations higher than the accessible size of the XRAM will be performed with the MOVX DPTR instructions in the same way as in the standard 80C51, with P0 and P2 as data/address busses, and P3.6 and P3.7 as write and read timing signals. Accesses to XRAM above 0FFH can only be done by the use of DPTR. With EXTRAM = 1 , MOVX @Ri and MOVX @DPTR will be similar to the standard 80C51. MOVX @ Ri will provide an eight-bit address multiplexed with data on Port 0 and any output port pins can be used to output higher order address bits. This is to provide the external paging capability. MOVX @DPTR will generate a sixteen-bit address. Port2 outputs the high-order eight address bits (the contents of DPH) while Port0 multiplexes the low-order eight address bits (DPL) with data. MOVX @ Ri and MOVX @DPTR will generate either read or write signals on P3.6 (WR ) and P3.7 (RD). The stack pointer (SP) may be located anywhere in the 256 bytes RAM (lower and upper RAM) internal data memory. The stack may not be located in the XRAM. The M0 bit allows to stretch the XRAM ti mings; if M0 is set, the read and write pulses are extended from 6 to 30 clock periods. This is useful to access external slow peripherals.

Table 8. AUXR Register Set to stretch MOVX control: the RD and the WR pulse length is 30 clock periods. Cleared to access internal XRAM using MOVX @ Ri/ @ DPTR. Set to access external memory. (HSB), default setting, XRAM selected.

18 AT80C51RD2/AT83C51Rx2

4113B–8051–03/05 Timer 2 The Timer 2 in the T8xc51Rx2 is the standard C52 Timer 2. It is a 16-bit timer/counter: the count is maintained by two eight-bit timer registers, TH2 and TL2 are cascaded. It is controlled by T2CON (Table 9) and T2MOD (Table 10) reg- isters. Timer 2 operation is similar to Timer 0 and Timer 1. C/T2 selects FOSC/12 (timer operation) or external pin T2 (counter oper ation) as the timer clock input. Setting TR2 allows TL2 to be incremented by the selected input. Timer 2 has 3 operating modes: capture, auto-reload and Baud Rate Generator. These modes are selected by the combination of RCLK, TCLK and CP/RL2 (T2CON). Refer to the Atmel 8-bit Microcontroller Hardware description for Capture and Baud Rate Generator Modes. Timer 2 includes the following enhancements: Auto-reload mode with up or down counter Programmable clock-output Auto-reload Mode The auto-reload mode configures Timer 2 as a 16-bit timer or event counter with auto- matic reload. If DCEN bit in T2MOD is cleared, Timer 2 behaves as in 80C52 (refer to the Atmel 8-bit Microcontroller Hardware description). If DCEN bit is set, Timer 2 acts as an Up/down timer/counter as shown in Figure 6. In this mode the T2EX pin controls the direction of count. When T2EX is high, Timer 2 counts up. Timer overflow occurs at FFFFh which sets the TF2 flag and generates an interrupt request. The overflow also causes the 16-bit value in RCAP2H and RCAP2L registers to be loaded into the timer registers TH2 and TL2. When T2EX is low, Timer 2 counts down. Timer underflow occurs when the count in the timer registers TH2 and TL2 equals the value stored in RCAP2H and RCAP2L registers. The underflow sets TF2 flag and reloads FFFFh into the timer registers. The EXF2 bit toggles when Timer 2 overflows or underflows according to the direction of the count. EXF2 does not generate any interrupt. This bit can be used to provide 17-bit resolution.

Figure 6. Auto-Reload Mode Up/Down Counter (DCEN = 1) Set T2OE bit in T2MOD register. reload value or a different one depending on the application. To start the timer, set TR2 run control bit in T2CON register. independent since both functions use the values in the RCAP2H and RCAP2L registers.

20 AT80C51RD2/AT83C51Rx2

Figure 7. Clock-Out Mode C/T2 = 07

Table 9. T2CON Register Must be cleared by software. Set by hardware on Timer 2 overflow, if RCLK = 0 and TCLK = 0. Cleared to use timer 1 overflow as receive clock for serial port in mode 1 or 3. Set to use Timer 2 overflow as receive clock for serial port in mode 1 or 3. Cleared to use timer 1 overflow as transmit clock for serial port in mode 1 or 3. Set to use Timer 2 overflow as transmit clock for serial port in mode 1 or 3. Cleared to ignore events on T2EX pin for Timer 2 operation. detected, if Timer 2 is not used to clock the serial port. Cleared to turn off Timer 2.

0 CP/RL2#

Set to capture on negative transitions on T2EX pin if EXEN2 = 1.

22 AT80C51RD2/AT83C51Rx2

Table 10. T2MOD Register The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. Cleared to program P1.0/T2 as clock input or I/O port. Set to program P1.0/T2 as clock output.

0 DCEN

Cleared to disable Timer 2 as up/down counter. Set to enable Timer 2 as up/down counter.

4113B–8051–03/05 Programmable Counter Array (PCA) The PCA provides more timing capabilities with less CPU intervention than the standard timer/counters. Its advantages include reduced software overhead and improved accu- racy. The PCA consists of a dedicated timer/counter which serves as the time base for an array of five compare/capture modules. Its clock input can be programmed to count any one of the following signals: Peripheral clock frequency (F CLK PERIPH) ÷ 6 Peripheral clock frequency (F CLK PERIPH) ÷ 2 Timer 0 overflow External input on ECI (P1.2) Each compare/capture modules can be programmed in any one of the following modes: Rising and/or falling edge capture Software timer High-speed output Pulse width modulator Module 4 can also be programmed as a Watchdog Timer (see Section "PCA Watchdog Timer", page 34). When the compare/capture modules are programmed in the capture mode, software timer, or high-speed output mode, an interrupt can be generated when the module exe- cutes its function. All five modules plus the PCA timer overflow share one interrupt vector. The PCA timer/counter and compare/capture modules share Port 1 for external I/O. These pins are listed below. If the port is not used for the PCA, it can still be used for standard I/O. The PCA timer is a common time base for all five modules (see Figure 8). The timer count source is determined from the CPS1 and CPS0 bits in the CMOD register (Table 11) and can be programmed to run at: 1/6 the peripheral clock frequency (FCLK PERIPH) 1/2 the peripheral clock frequency (FCLK PERIPH) The Timer 0 overflow The input on the ECI pin (P1.2) PCA Component External I/O Pin 16-bit Counter P1.2/ECI 16-bit Module 0 P1.3/CEX0 16-bit Module 1 P1.4/CEX1 16-bit Module 2 P1.5/CEX2 16-bit Module 3 P1.6/CEX3

24 AT80C51RD2/AT83C51Rx2

Figure 8. PCA Timer/Counter

Table 11. CMOD Register The CIDL bit which allows the PCA to stop during idle mode. The WDTE bit which enables or disables the watchdog function on module 4. the CCON SFR) to be set when the PCA timer overflows. timer (CF) and each module (see Table 12). only be cleared by software. can only be cleared by software. Cleared to program the PCA Counter to continue functioning during idle Mode. Set to program PCA to be gated off during idle. Cleared to disable Watchdog Timer function on PCA Module 4. Set to enable Watchdog Timer function on PCA Module 4. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. Cleared to disable CF bit in CCON to inhibit an interrupt. Set to enable CF bit in CCON to generate an interrupt.

26 AT80C51RD2/AT83C51Rx2

Table 12. CCON Register The watchdog timer function is implemented in module 4 (see Figure 11). The PCA interrupt system is shown in Figure 9. Must be cleared by software to turn the PCA counter off. Set by software to turn the PCA counter on. The value read from this bit is indeterminate. Do not set this bit.