AT7912EKF-SV

AT7912E ATMEL | Alldatasheet

Document overview

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Technical content

Features

• Also known as SMCS116SpW
• Single Bidirectional SpaceWire link allowing – Full duplex communication – Transmit rate from 1.25 up to 200 Mbit/s in each d irection – Supports Serial Transfer Universal Protocol (STUP)
• Derived from the T7906 Single Point to Point IEEE 1355 High Speed Controller – Known anomalies of the T7906 chip corrected
• Host interface – Gives read/write accesses to the AT7912E configura tion registers – Gives read/write accesses to the SpaceWire channel
• ADC/ DAC interface – Allows direct connection of an ADC with a width of up to 16 bits – Allows direct connection of a DAC with up to 16 data lines and the required control signals
• FIFO interface
• RAM interface – 16-bit data bus and 16-bit address bus – Four chip selects to address 4 different memory pa rtitions
• Two independent UART interfaces
• 24 Bidirectional General Purpose I/Os
• Two 32-Bit Timers / Event Counters
• SpaceWire Link Performance – At 3.3V : 100Mbit/s full duplex communication – At 5V : 200Mbit/s full duplex communication
• Operating range – Voltages
• 3V to 3.6V
• 4.5V to 5.5V – Temperature
• - 55° C to +125° C
• Maximum Power consumption – At 3.6V with a 5MHz clock: 150mW – At 5.5V with a 5MHz clock: 700mW
• Radiation Performance – Total dose tested successfully up to 50 Krad (Si) – No single event latchup below a LET of 80 MeV/mg/c m2
• ESD better than 2000V
• Quality Grades – QML-Q or V with SMD
• Package: 100pins MQFPF
• Mass: 3grams Single SpaceWire link High Speed Controller AT7912E

SpaceWire Standard ECSS-E-50-12A and several different interfaces. CMOS 0.5µm radiation tolerant sea of gates technolo gy. Atmel technical support at assp-applab.hotline@nto.atmel.com . Manual' . This user manual is available at www.atmel.com . A block diagram of the AT7912E is given in figure 1. Figure 1. AT7912E Block Diagram

(Serial Transfer Universal Protocol) for efficient packet oriented data transfer.

• Host interface
• ADC interface
• DAC interface
• RAM interface
• FIFO interface
• General purpose I/O
• UART interfaces
• Timers / Event Counters
• JTAG (IEEE 1149.1) 2. Pin Configuration

Table 1. Pin assignment

1 PLLOUT 26 IOB9 51 DATA4 76 TMR2_CLK

2 GND 27 VCC 52 DATA5 77 RxD1

3 VCC 28 GND 53 DATA6 78 TMR1_EXP

4 VCC 29 IOB10 54 DATA7 79 TMR2_EXP

5 LDO 30 IOB11 55 DATA8 80 TxD1

6 LSO 31 IOB12 56 VCC 81 HDATA0

7 LDI 32 IOB13 57 GND 82 HDATA1

8 LSI 33 IOB14 58 DATA9 83 HDATA2

9 GND 34 IOB15 59 DATA10 84 HDATA3

10 TCK 35 IOB16 60 DATA11 85 HDATA4

11 TMS 36 IOB17 61 VCC 86 HDATA5

12 TDI 37 IOB18 62 GND 87 HDATA6

13 TRST* 38 IOB19 63 DATA12 88 VCC

14 TDO 39 IOB20 64 DATA13 89 GND

15 GND 40 IOB21 65 DATA14 90 HDATA7

16 VCC 41 IOB22 66 DATA15 91 HDATNADR*

17 IOB0 42 IOB23 67 GPIO0 92 HSEL*

18 IOB1 43 IOB24 68 GPIO1 93 HWRNRD

19 IOB2 44 IOB25 69 GPIO2 94 HINTR*

20 IOB3 45 IOB26 70 GPIO3 95 RESET*

21 IOB4 46 IOB27 71 GPIO4 96 CLK

22 IOB5 47 DATA0 72 GPIO5 97 VCC_3VOLT

23 IOB6 48 DATA1 73 GPIO6 98 GND

24 IOB7 49 DATA2 74 GPIO7 99 GND

25 IOB8 50 DATA3 75 TMR1_CLK 100 VCC

Table 2. Pin description the address register or to the AT7912E registers. from the address register or the AT7912E registers. from/to the internal AT7912E (data) registers. reads/writes address from/to the address register.

7743A–AERO–07/07 Notes: 1. Groups of pins represent busses where the h ighest number is the MSB. 2. O = Output; I = Input; Z = High Impedance 3. (*) = active low signal 4. O/Z = if using a configuration with two AT7912Es these signals can directly be con- nected together (WIROR) TMS I Test Mode Select. Used to control the test state machine. This input should be left unconnected or tied to ground during normal op eration TDI I Test Data Input. Provides serial data for the boundary scan logic TDO O/Z Test Data Output. Serial scan output of the boundary scan path 3 1.5 50 RESET* I AT7912E Reset. Sets the AT7912E to a known state. This input must be asserted (low) at power-up. The minimum width of RE SET low is 2 cycles when CLK is running CLK I External clock input to AT7912E (max. 5 MHz) PLLOUT O Output of internal PLL. Used to connect a network of external RC filter dev ices. VCC_3VOLT I PLL Control signal Configure PLL for 3.3V or 5V operation VCC = 5 Volt: connect this signal with GND VCC = 3.3 Volt: connect this signal with VCC VCC Power Supply GND Ground Signal Name (1)(3) Type (2)(4) Function 5V ± 0.5V max. output current [mA] 3.3V ± 0.3V max. output current [mA] load [pF]

7743A–AERO–07/07

3.1 Signals Organization

This section describes the signals of the AT7912E. Groups of signals represent buses where the highest number is the MSB. Figure 3-1. Signals Organization

7743A–AERO–07/07

3.2 Shared I/O

Some of the functions of the AT7912E share the same I/O pins. This means that some functions are mutually exclusive. As an example, th e GPIO port shares some of its I/O pins with the host interface. If the host interface is not used, these pins are available for GPIO; otherwise they are used as the host address a nd data bus. The selection of which functions are being used is made by programmi ng the appropriate registers after a chip reset. A short overview of the signals allocation for the various functions is given in the table below. Table 3-1. Shared I/Os description Signal Functions GPIO I/O RAM Interface I/O FIFO Interface I/O DAC/ADC Interface I/O UART & Interrupts I/O HDATA[7:0] GPIO2[7:0] I/O GPIO0 GPIO0_0 I/O RTS1* I GPIO1 GPIO0_1 I/O CTS1* I GPIO2 GPIO0_2 I/O EXT_IRQ0* I GPIO3 GPIO0_3 I/O EXT_IRQ1* I GPIO4 GPIO0_4 I/O TxD2 O GPIO5 GPIO0_5 I/O RxD2 I GPIO6 GPIO0_6 I/O RTS2* O GPIO7 GPIO0_7 I/O RTS2* I IOB[7:0] GPIO1[7:0] I/O RAM_ADDR[7:0] O ADC_ADDR[7:0] O IOB8 RAM_ADDR8 O ADC_CS* O IOB9 RAM_ADDR9 O ADC_R/C* O IOB10 RAM_ADDR10 O DAC_WR* O IOB11 RAM_ADDR11 O DAC_ADDR0 O IOB12 RAM_ADDR12 O DAC_ADDR1 O IOB13 RAM_ADDR13 O DAC_ADDR2 O IOB14 RAM_ADDR14 O FIFO_TRM_EOP_ACK O IOB15 RAM_ADDR15 O FIFO_RCV_PAR FIFO_EOPL I/O IOB16 RAM_WR* O FIFO_RCVEOP O IOB17 RAM_RD* O FIFO_RCVEEP O IOB18 RAM_CS0* O FIFO_RD* I/O IOB19 RAM_CS1* O FIFO_WR* I/O IOB20 RAM_CS2* O FIFO_EMPTY* I/O IOB21 RAM_CS3* O FIFO_FULL* I/O

7743A–AERO–07/07 IOB22 RAM_TEST O ADC_RDY I IOB23 RAM_TMR_RDY O ADC_TRIG I IOB24 RAM_RCV_RDY O FIFO_TRMEOP I IOB25 RAM_BUS_REQ* I FIFO_TRMEEP I IOB26 RAM_START_TRM I FIFO_RCV_EOP_ACK I IOB27 RAM_START_RCV I FIFO_TRM_PAR FIFO_EOPH I/O Signal Functions GPIO I/O RAM Interface I/O FIFO Interface I/O DAC/ADC Interface I/O UART & Interrupts I/O

7743A–AERO–07/07 4. Interfaces The AT7912E provides an interface between a SpaceWi re link according to the SpaceWire Standard ECSS-E-50-12A and several different interfaces:

• Host interface
• ADC/DAC interface
• RAM interface
• FIFO interface
• General purpose I/O
• UART interfaces
• Timers / Event Counters

4.1 Host Interface

Although the AT7912E is primarily designed to be re motely controlled, it can neverthe- less be programmed and controlled by a local host if required. For that purpose the host interface provides 8 multiplexed data and address lines.

4.2 ADC/DAC interface

The ADC interface allows connecting an ADC with a width of up to 16 bits directly to the AT7912E. The AD conversion can be started by reques t via link or in a cyclic manner triggered by the on chip timers. When the AD conver sion is ready, this is recognized by an external signal like "ready" or by an internal t rigger, for example from the on chip timer. After reading the sample from the ADC it is then sent over the link. An 8-bit address generator is provided to allow multiplexing of analog signals. The address gen- erator will start at a pre-programmed start address and will be incremented after each conversion. The DAC interface is very similar to the ADC interf ace. It provides up to 16 data lines and the required control signals. The data to be sent to the DAC is received from the link and is stored in a register until the command "star t DAC" is received. After that com- mand the register values will be put to the DAC.

4.3 RAM Interface

The RAM interface provides a 16-bit data bus and 16 -bit address bus. Four chip select lines allow addressing four different memory partitions (banks). This partitioning into dif- ferent banks is done using 4 internal address bound ary registers. These are 8 bit wide and provide a minimum page size of 1024 words. The memory interface can be pro- grammed to use 0 to 7 wait states.

7743A–AERO–07/07

4.4 FIFO interface

The FIFO (8-bit or 16-bit data width) interface pro vides the control signals full, write, empty and read, depending on the direction of the data flow (receive/transmit). Data received from the FIFO interface is sent over the SpaceWire link grouped in pack- ets. The length of a packet (in bytes) can be speci fied either by setting an internal counter or by external signals. This interface can be programmed to use 0 to 7 wait states. The FIFO interface handles two operating modes:

• An active mode where the AT7912E FIFO controller r eads and writes from/to an external FIFO
• A passive mode where an external controller reads and writes from/to the AT7912E internal FIFO.

4.5 GPIO Interface

The general purpose I/O (GPIO Interface) provides u p to 24 bidirectional signal lines. The direction (input or output) of each GPIO line c an be set individually via register. Data to/from the GPIO lines is written / read via t he GPIO data register. The GPIO pro- vides 8 dedicated I/O lines, the remaining 16 lines of the port are shared with the ADC address and host data bus. These GPIO lines are available when the corresponding unit (e.g. the host data bus) of the AT7912E is not being used (disabled).

4.6 UART interface

Two independent UARTs are included in the AT7912E a s well. One UART uses dedi- cated I/O lines whereas the second UART is sharing its pins with the GPIO port. The transmit rate of the UARTs in bps can be programmed via a 12-bit wide register with a maximum bit rate of about 780 kbit/s. Each UART has a 4-byte FIFO in transmit, and a 4-byte FIFO in receive direction. The UARTs can optionally use hardware handshake (rts/cts).

4.7 Timers / Event Counter

Two 32-bit on-chip timers are available on the AT7912E. Each timer provides a 32-bit counter and a 32-bit r eload register. The two timers can be operated independently or cascaded. The timers can be used to set an external signal wh en the timeout value is reached. Each timer can generate periodic interrupts or only one interrupt, depending on configu- ration. An external output, TMR_EXP, signals to oth er devices that the timer count has expired. An external input, TMR_CLK, is provided wh ich can be used as trigger source for the timer.

7743A–AERO–07/07 5. Operating Modes

5.1 Configuration of the AT7912E

The AT7912E provides registers and ports for config uration. Each register contains exactly one byte (read / write), whereas a port (e. g. a FIFO interface) behaves like a FIFO, meaning that multiple data bytes can be read or written from/to the port. The ports of the AT7912E such as the FIFO, UART, AD C and RAM interfaces are accessed by a read/write command to the correspondi ng port address. In the case of FIFO, Host, UART and memory interfaces, a packet or iented access is also possible (meaning transferring multiple data bytes with a single command). The read/write selec- tion of a command is done by setting bit 7 (MSB) of the first byte to one (read) or zero (write). All internal registers are 8-bit wide addressable. Two simple commands, read and write, suffice to access all registers of the AT7912E. Configuration/Programming of the AT7912E internal registers is done via either a simple protocol over the SpaceWire link or STUP over the S paceWire link or directly via the host interface.

• The simple protocol over the SpaceWire, compatible with the T7906 (SCMCS116) link requires a command byte and, if necessary, one or more data bytes. The simple protocol ignores following bytes, if more bytes are sent.
• The STUP over the SpaceWire link uses 4 bytes for commands. It also supports logical addressing.
• The host interface provides a direct access to the internal registers through a 8-bit multiplexed address/data bus. After reset, the host interface is enabled. After a chip reset the AT7912E is configured via th e internal controller. This can be either by receiving the configuration data from the SpaceWire link or by an external con- troller connected to the host port of the AT7912E.

7743A–AERO–07/07 6. Test Interface

6.1 JTAG

This represents the boundary scan testing provision s specified by IEEE Standard 1149.1 of the Joint Testing Action Group (JTAG). The AT7912E test access port and on- chip circuitry is fully compliant with the IEEE 114 9.1 specification. The test access port enables boundary scan testing of circuitry connected to the AT7912E I/O pins. 7. AT7912E differences with theT7906E A few differences between the AT7912E and the T7906 E exist in the registers, the sig- nals and the pinout. These differences are detailed in the section 15 of the ‘SMCS116SpW User Manual”.

7743A–AERO–07/07 9. PLL Filter The AT7912E embeds a PLL to generate its internal c lock reference. The PLLOUT pin of the PLL is the output of the AT7912E that allows connection of the external filter of the PLL. The following figure presents the connection of the PLL filter. Figure 9-1. PLL filter Table 9-1. PLL filter recommended components 10. Power Supply To achieve its fast cycle time, the AT7912E is desi gned with high speed drivers on out- put pins. Large peak currents may pass through a ci rcuit board's ground and power lines, especially when many output drivers are simu ltaneously charging or discharging their load capacitances. These transient currents c an cause disturbances on the power and ground lines. To minimize these effects, the AT 7912E provides separate supply pins for its internal logic and for its external drivers. All GND pins should have a low impedance path to gr ound. A ground plane is required in AT7912E systems to reduce this impedance, minimizing noise. The VCC pins should be bypassed to the ground plane using 8 high-frequency capaci- tors (0.1 µF ceramic). Keep each capacitor's lead a nd trace length to the pins as short as possible. This low inductive path provides the A T7912E with the peak currents required when its output drivers switch. The capaci tors' ground leads should also be short and connect directly to the ground plane. Thi s provides a low impedance return path for the load capacitance of the AT7912E output drivers. The following pins must have a capacitor: 3, 4, 16, 27, 56, 61, 88 and 100. R1 1,5 k Ω ± 5%, ¼W C1 22pF, ± 5% C2 1.8nF, ± 5% AT7912E

7743A–AERO–07/07 11. Electrical Characteristics

11.1 Absolute Maximum Ratings

Table 11-1. Absolute Maximum Ratings Stresses above those listed may cause permanent damage to the device. Parameter Symbol Value Unit Supply Voltage VCC -0.5 to +7 V I/O Voltage -0.5 to VCC + 0.5 V Operating Temperature Range (Ambient) TA -55 to +125 ° C Junction Temperature TJ TJ < TA +20 ° C Storage Temperature Range Tstg -65 to +150 ° C Thermal resistance Junction to case RThJC 5 ° C/W

7743A–AERO–07/07

11.2 DC Electrical Characteristics

The AT7912E can work with VCC = + 5 V ± 0.5 V and V CC = + 3.3V ± 0.3V. Although specified for TTL outputs, all AT7912E outputs are CMOS compatible and will drive to VCC and GND assuming no DC loads. Table 11-2. 5V operating range DC Characteristics. Notes: 1. Applicable for HDATA[7:0], HINTR*, TMR1_EXP , TMR2_EXP , TxD1, DATA[15:0], GPIO[7:0], IOB[24:22], IOB27 and TDO pins 2. Applicable for IOB[21:0] pins 3. Applicable for LDO and LSO pins Table 11-3. 3.3V operating range DC Characteristics. Notes: 1. Applicable for HDATA[7:0], HINTR*, TMR1_EXP , TMR2_EXP , TxD1, DATA[15:0], GPIO[7:0], IOB[24:22], IOB27 and TDO pins 2. Applicable for IOB[21:0] pins 3. Applicable for LDO and LSO pins Parameter Symbol Min. Max. Unit Conditions Operating Voltage VCC 4.5 5.5 V Input HIGH Voltage VIH 2.2 V Input LOW Voltage VIL 0.8 V Output HIGH Voltage VOH 2.4 V IOL = 1.5, 3, 6mA / VCC = VCC(min) Output LOW Voltage VOL 0.4 V IOH = 1, 2, 4mA / VCC = VC C(min) Output Short circuit current IOS 90 (1) 180 (2) 270 (3) mA mA mA VOUT = VCC VOUT = GND Parameter Symbol Min. Max. Unit Conditions Operating Voltage VCC 3.0 3.6 V Input HIGH Voltage VIH 2.0 V Input LOW Voltage VIL 0.8 V Output HIGH Voltage VOH 2.4 V IOL = 3, 6, 12mA / VCC = VCC(min) Output LOW Voltage VOL 0.4 V IOH = 3, 6, 12mA / VCC = V CC(min) Output Short circuit current IOS 50 (1) 100 (2) 155 (3 mA mA mA VOUT = VCC VOUT = GND

7743A–AERO–07/07

11.3 Power consumption

Maximum power consumption figures at Vcc = 5.5V; -55° C; CLK = 5 MHz are presented in the following table. Table 11-4. 5V Power Consumption Maximum power consumption figures at Vcc = 3.6V; -55° C; CLK = 5 MHz are presented in the following table. Table 11-5. 3.3V Power Consumption Operation Mode Power consumption [mA] not clocked 2 AT7912E in RESET 22 AT7912E in IDLE (1) 1. IDLE means clk = 5 MHz, link started and running at 10Mbit/s, no activity on the other interfaces. Maximum 120 Operation Mode Power consumption [mA] not clocked 1 AT7912E in RESET 10 AT7912E in IDLE (1) 1. IDLE means clk = 5 MHz, link started and running at 10Mbit/s, no activity on the other interfaces. Maximum 40

7743A–AERO–07/07

11.4 AC Electrical Characteristics

The following table gives the worst case timings measured by Atmel on the 4.5V to 5.5V operating range Table 11-6. 5V operating range timings. The following table gives the worst case timings measured by Atmel on the 3.0V to 3.6V operating range Table 11-7. 3.3V operating range timings For guaranteed timings on the two operating voltage ranges, refer to the section 12 of the ‘SMCS116SpW User Manual’ Parameter Symbol Min. Max. Unit Propagation delay TCK Low to TDO Low Tp1 20 ns Propagation delay CLK High to TMR1_EXP Low Tp2 23 ns Propagation delay CLK High to LDO Low Tp3 16 ns Propagation delay CLK High to HINTR* Low Tp4 25 ns Propagation delay CLK High to IOB18 Low Tp5 16 ns Parameter Symbol Min. Max. Unit Propagation delay TCK Low to TDO Low Tp1 33 ns Propagation delay CLK High to TMR1_EXP Low Tp2 38 ns Propagation delay CLK High to LDO Low Tp3 27 ns Propagation delay CLK High to HINTR* Low Tp4 41 ns Propagation delay CLK High to IOB18 Low Tp5 27 ns

7743A–AERO–07/07 12. Package Drawings

12.1 MQFPF100

100 pins Ceramic Quad Flat Pack (MQFPF 100)

7743A–AERO–07/07 13. Ordering Information (*) according to Atmel Quality flow document 4288, see Atmel web site. Part-number Temperature Range Package Quality Flow AT7912EKF-E 25° C MQFPF100 Engineering sample AT7912EKF-MQ -55° C to +125° C MQFPF100 Mil Level B (*) AT7912EKF-SV -55° C to +125° C MQFPF100 Space Level B (* )

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literature@atmel.com Web Site http://www.atmel.com 7743A–AERO–07/07 xM ©2007 Atmel Corporation. All rights reserved. Atmel ®, logo and combinations thereof are registered tra demarks, or are the trademarks of Atmel Corporation or its subsidiaries. Other terms and pr oduct names may be trademarks of others.