AT76C551

AT76C551 ATMEL | Alldatasheet

Document overview

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Technical content

Features

• Implements Bluetooth™ Specification on Short Distance Wireless Communication in

2.4 GHz ISM Band

 Provides 1 Mbps Aggregate Bit Rate  Supports Frequency Hopping Spread Spectrum Physical-layer Interface to Dedicated Transceiver with Frequency Hopping Algorithm Implemented in Hardware  Provides Baseband Functions in Hardware which Implement Bluetooth Low-level Bit Processing Such as Forward Error Correction (FEC), Header Error Check (HEC) and CRC Generation/Checking and Encryption/Decryption  Integrated ARM7TDMI® RISC Processor  Glueless SRAM Interface, Supporting Up to 256K Bytes of Memory  Glueless Flash Memory Interface, Supporting Up to 256K Bytes of Nonvolatile Memory  Glueless PCMCIA Bus Interface Conforming to PC Card Standard – Feb. 1995  USB Interface Conforming to Universal Serial Bus Standard Version 1.1  16550 UART Core Offering 32-byte Receive FIFO and Programmable Baud Rate  Programmable 8/16-bit Wide External Memory Interface  Supports Multiple Reference Clock Frequencies (13.000, 14.400, 16.800, 19.440 MHz)  176-lead LQFP  3.3V Supply System Level Block Diagram RSSI ARMClock Generator Transmit Data Processing 3-Wire Control Bus Memory Interface Internal RAM PCMCIA Interface USB Slave AMBA Bus Interface Voice CODEC Receive Sequencing Manager UART Power Management Receive Data Front-end Receive Data Processing Single Chip Bluetooth™ Controller AT76C551 Rev. 1612D–08/01

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1612D–08/01 Overview The AT76C551 is a single chip controller providing the functionality for high data rate, short distance wireless communications in the free ISM band. In conjunction with a 2.4 GHz trans- ceiver, it provides a cost effective networking solution for a wide range of digital communication devices and computer peripherals. Integration is simplified due to the incorpo- ration of three different interfaces: USB and 16550 UART compatible interfaces and a PCMCIA interface conforming to the PC Card 95 specification. Additionally, a voice cod- ing/decoding module is provided. The AT76C551 is comprised of a baseband processor. This processor carries out all bit-level processing after modulation/demodulation of the Bluetooth bitstream. It controls the trans- ceiver and dedicated voice coding/decoding. The AT76C551 has an ARM7TDMI processor core with support for internal and external memory, as well as the interface core logic. The powerful RISC processor in the ARM7TDMI carries out all but the low level baseband functions. between portable devices such as mobile phones and digital peripherals. Typical usages would include:  Wireless network cards  Mobile phones  Laptop and desktop computers  Pagers  Digital cameras  PDAs  Wireless computer peripherals (printers, etc.)

1612D–08/01 Typical AT76C551 Home Application Typical AT76C551 Mobile Application RS-232RS-232 Fax Laptop Computer Printer Keyboard USB AT76C551 Powered Mouse USB PCMCIA AT76C551 Bluetooth Adapter AT76C551 Bluetooth Adapter AT76C551 Bluetooth Adapter AT76C551 Bluetooth Adapter AT76C551 Bluetooth Adapter USB USB Tower Box Monitor Pen Computer RS-232 AT76C551 Powered Cell Phone RS-232 AT76C551 Bluetooth Adapter AT76C551 Bluetooth Adapter AT76C551 Bluetooth Adapter AT76C551 Bluetooth Adapter Printer

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1612D–08/01 Functional Diagram A S B A P B ARM Memory Interface External Flash External RAM 64K Bytes Internal RAM 1K Byte D.P.RAM 64K Bytes D.P.RAM ASB/APB Bridge Voice CODEC 32K Bytes D.P.RAM 32K Bytes D.P.RAM UART Register Bank USB PCMCIA ADC Interrupt Controller Timer0 Timer1 BT Controller DAC 64K Bytes D.P.RAM 64K Bytes D.P.RAM TxSync D.P.RAM RxFrontEnd RSSI ADC 32K Bytes D.P.RAM

1612D–08/01 Pinout and Package Options The AT76C551 controller will be available in three different packages, each will have the same basic functionality but with a different system interface (PCMCIA 8-bit, full-speed USB, extended speed RS-232). The prototype version comes in a LQFP-176 package and supports the three different interfaces simultaneously. Pinout of the Prototype Version Pin 1 is marked for orientation NCx = No Connection 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 PC_A1 PC_A2 PC_A3 PC_A4 PC_A5 PC_A6 PC_A7 VCC PC_A8 PC_A9 PC_A10 PC_A11 PC_A12 PC_A13 PC_A14 P_OR_UN GND DM DP VCC U_CD_ USART_RX U_DSR_ GND U_CTS_ U_RI_ USART_TX U_DTR_ U_RTS_ MA0 MA1 MA2 MA3 MA4 MA5 MA6 VCC GND MA7 MA8 MA9 MA10 MA11 MA12 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 ADO ADI GND ACLK ABCLK ASYNC VCC ACLK_IN ABCLK_IN ASYNC_IN CSFL 16 CSSR CSFL CSSFH CSFLH NWRITE NRED NWORD MDH7 MDH6 MDH5 MDH4 MDH3 GND VCC MDH2 MDH1 MDH0 MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0 GND VCC MA18 MA17 MA16 MA15 MA14 MA13 CLK_MODE1 CLK MODE0 OSC_MODE GND LFT GND PLL_TEST_PIN PC_RESET TST_ECK TEST_CTRL VCC XTAL2 XTAL1 GND TDO TMS TDI TCK NTRST VCC DB_CLK DB_DATA GND NIREQ NINPACK NWAIT NREG NIOWR NIORD NCE1 NCE NWE VCC GND PC-D0 PC-D1 PC-D2 PC-D3 PC-D4 PC-D5 PC-D6 PC_D7 GND PC_A0 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 VCC EXT_13_MHz EXT-13-MHz_OUT GND EXT_OSC GND TC_ENABL TC_DATA TC_CLK VCC TC_TXON TXPIN TC_PUPLL TC_PURXTX TC_PUVCO TC_I_CP_SW TC_PUREG TC_RXON TC_LD GND CLK_RXPIN VCC RXPIN RXMODE RXF_PD RXF_CLK RXF_OE_ RXF-D7 RXF-D6 RXF_D5 RXF_D4 RXF_D3 GND RXF_D2 RXF_D1 RXF_D0 VDDAC AGND RSSI AVCC VC_IN AGND VC_OUT AVCC PC_A1 PC_A2 PC_A3 PC_A4 PC_A5 PC_A6 PC_A7 VCC PC_A8 PC_A9 PC_A10 PC_A11 PC_A12 PC_A13 PC_A14 P_OR_UN GND DM DP VCC U_CD_ USART_RX U_DSR_ GND U_CTS_ U_RI_ USART_TX U_DTR_ U_RTS_ MA0 MA1 MA2 MA3 MA4 MA5 MA6 VCC GND MA7 MA8 MA9 MA10 MA11 MA12 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 ADO ADI GND ACLK ABCLK ASYNC VCC ACLK_IN ABCLK_IN ASYNC_IN CSFL 16 CSSR CSFL CSSFH CSFLH NWRITE NRED NWORD MDH7 MDH6 MDH5 MDH4 MDH3 GND VCC MDH2 MDH1 MDH0 MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0 GND VCC MA18 MA17 MA16 MA15 MA14 MA13 CLK_MODE1 CLK MODE0 OSC_MODE GND LFT GND PLL_TEST_PIN PC_RESET TST_ECK TEST_CTRL VCC XTAL2 XTAL1 GND TDO TMS TDI TCK NTRST VCC DB_CLK DB_DATA GND NIREQ NINPACK NWAIT NREG NIOWR NIORD NCE1 NCE NWE VCC GND PC-D0 PC-D1 PC-D2 PC-D3 PC-D4 PC-D5 PC-D6 PC_D7 GND PC_A0

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1612D–08/01 Pin Summary – Pin Assignment in Numerical Order Pin # Pin Name Type Pin # Pin Name Type Pin # Pin Name Type

1 VCC Digital Supply 38 AGND Analog Ground 75 MEM_DATA5 B

2 EXT_13_MHz I 39 RSSI I 76 MEM_DATA4 B

3 EXT_13_MHz_OUT O 40 AVCC 77 MEM_DATA3 B

4 GND Digital Ground 41 VC_IN LOG 1 78 MEM_DATA2 B

5 EXT_OSC I 42 AGND Analog Ground 79 MEM_DATA1 B

6 GND Digital Ground 43 VC_OUT LOG O 80 MEM_DATA0 B

7 TC_ENABL O 44 AVCC 81 GND Digital Ground

8 TC_DATA O 45 ADO O 82 VCC Digital Supply

9 TC_CLK O 46 ADI I 83 MEM_ADDR18 O

10 VCC Digital Supply 47 GND Digital Ground 84 MEM_ADDR17 O

11 TC_TXON O 48 ACLK O 85 MEM_ADDR16 O

12 TXPIN O 49 ABCLK O 86 MEM_ADDR15 O

13 TC_PUPLL O 50 ASYNC O 87 MEM_ADDR14 O

14 TC_PURXTX O 51 VCC Digital Supply 88 MEM_ADDR13 O

15 TC_PUVCO O 52 ACLK_IN I 89 MEM_ADDR12 O

16 TC_I_CP_SW O 53 ABCLK_IN I 90 MEM_ADDR11 O

17 TC_PUREG O 54 ASYNC_IN I 91 MEM_ADDR10 O

18 TC_RXON O 55 CSFL16 O 92 MEM_ADDR9 O

19 TC_LD I 56 CSSR O 93 MEM_ADDR8 O

20 GND Digital Ground 57 CSFL O 94 MEM_ADDR7 O

21 CLK_PXPIN I 58 CSSFH 95 GND Digital Ground

22 VCC Digital Supply 59 CSFLH O 96 VCC Digital Supply

23 RXPIN I 60 NWRITE O 97 MEM_ADDR6 O

24 RXMODE I 61 NRED 98 MEM_ADDR5 O

25 RXF_PD O 62 NWORD I 99 MEM_ADDR4 O

26 RXF_CLK O 63 MEM_DATAH7 B 100 MEM_ADDR3 O

27 RXF_OE_ O 64 MEM_DATAH6 B 101 MEM_ADDR2 O

28 RXF_D7 I 65 MEM_DATAH5 B 102 MEM_ADDR1 O

29 RXF_D6 I 66 MEM_DATAH4 B 103 MEM_ADDR0 O

30 RXF_D5 I 67 MEM_DATAH3 B 104 U_RTS_ O

31 RXF_D4 I 68 GND Digital Ground 105 U_DTR_ O

32 RXF_D3 I 69 VCC Digital Supply 106 USART_TX O

33 GND Digital Ground 70 MEM_DATAH2 B 107 U_RI_ I

34 RXF_D2 I 71 MEM_DATAH1 B 108 U_CTS_ I

35 RXF_D1 I 72 MEM_DATAH0 B 109 GND Digital Ground

36 RXF_D0 I 73 MEM_DATA7 B 110 U_DSR_ I

37 VDDAC 74 MEM_DATA6 B 111 USART_RX I

1612D–08/01

112 U_CD_ I 134 GND Digital Ground 156 DB_CLK O

113 VCC Digital Supply 135 PC_D7 B 157 VCC Digital Supply

114 DP B 136 PC_D6 B 158 NTRST I

115 DM B 137 PC_D5 B 159 TCK I

116 GND Digital Ground 138 PC_D4 B 160 TDI I

117 P_OR_UN I 139 PC_D3 B 161 TMS I

118 PC_A14 I 140 PC_D2 B 162 TDO I

119 PC_A13 I 141 PC_D1 B 163 GND Digital Ground

120 PC_A12 I 142 PC_D0 B 164 XTAL1 I

121 PC_A11 I 143 GND Digital Ground 165 XTAL2 I

122 PC_A10 I 144 VCC Digital Supply 166 VCC Digital Supply

123 PC_A9 I 145 NWE I 167 TEST_CTRL I

124 PC_A8 I 146 NCE 168 TST_ECK I

125 VCC Digital Supply 147 NCE1 I 169 PC_RESET I

126 PC_A7 I 148 NIORD I 170 PLL_TEST_PIN I

127 PC_A6 I 149 NIOWR I 171 GND Digital Ground

128 PC_A5 I 150 NREG I 172 LFT

129 PC_A4 I 151 NWAIT O 173 GND Digital Ground

130 PC_A3 I 152 NINPACK O 174 OSC_MODE

131 PC_A2 I 153 NIREQ 175 CLK _MODE0

132 PC_A1 I 154 GND Digital Ground 176 CLK _MODE1

133 PC_A0 I 155 DB_DATA O

Pin Summary – Pin Assignment in Numerical Order (Continued) Pin # Pin Name Type Pin # Pin Name Type Pin # Pin Name Type

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1612D–08/01 Pin Summary – Pin Assignment in Alphabetical Order Pin # Pin Name Type Pin # Pin Name Type Pin # Pin Name Type

49 ABCLK O 81 GND Digital Ground 67 MEM_DATAH3 B

53 ABCLK_IN I 95 GND Digital Ground 66 MEM_DATAH4 B

48 ACLK O 109 GND Digital Ground 65 MEM_DATAH5 B

52 ACLK_IN I 163 GND Digital Ground 64 MEM_DATAH6 B

46 ADI I 171 GND Digital Ground 63 MEM_DATAH7 B

45 ADO O 173 GND Digital Ground 146 NCE

38 AGND Analog Ground 172 LFT 147 NCE1 I

42 AGND Analog Ground 103 MEM_ADDR0 O 152 NINPACK O

50 ASYNC O 102 MEM_ADDR1 O 148 NIORD I

54 ASYNC_IN I 91 MEM_ADDR10 O 149 NIOWR I

40 AVCC 90 MEM_ADDR11 O 153 NIREQ

44 AVCC 89 MEM_ADDR12 O 61 NRED

175 CLK_MODE0 88 MEM_ADDR13 O 150 NREQ I

176 CLK_MODE1 87 MEM_ADDR14 O 158 NTRST I

21 CLK_PXPIN I 86 MEM_ADDR15 O 151 NWAIT O

57 CSFL O 85 MEM_ADDR16 O 145 NWE I

55 CSFL16 O 84 MEM_ADDR17 O 62 NWORD I

59 CSFLH O 83 MEM_ADDR18 O 60 NWRITE O

58 CSSFH 101 MEM_ADDR2 O 174 OSC_MODE

56 CSSR O 100 MEM_ADDR3 O 117 P_OR_UN I

156 DB_CLK O 99 MEM_ADDR4 O 133 PC_A0 I

155 DB_DATA O 98 MEM_ADDR5 O 132 PC_A1 I

115 DM B 97 MEM_ADDR6 O 122 PC_A10 I

114 DP B 94 MEM_ADDR7 O 121 PC_A11 I

2 EXT_13_MHz I 93 MEM_ADDR8 O 120 PC_A12 I

3 EXT_13_MHz_OUT O 92 MEM_ADDR9 O 119 PC_A13 I

5 EXT_OSC I 80 MEM_DATA0 B 118 PC_A14 I

4 GND Digital Ground 79 MEM_DATA1 B 131 PC_A2 I

6 GND Digital Ground 78 MEM_DATA2 B 130 PC_A3 I

20 GND Digital Ground 77 MEM_DATA3 B 129 PC_A4 I

33 GND Digital Ground 76 MEM_DATA4 B 128 PC_A5 I

116 GND Digital Ground 75 MEM_DATA5 B 127 PC_A6 I

47 GND Digital Ground 74 MEM_DATA6 B 126 PC_A7 I

68 GND Digital Ground 73 MEM_DATA7 B 124 PC_A8 I

134 GND Digital Ground 72 MEM_DATAH0 B 123 PC_A9 I

143 GND Digital Ground 71 MEM_DATAH1 B 142 PC_D0 B

154 GND Digital Ground 70 MEM_DATAH2 B 141 PC_D1 B

1612D–08/01

140 PC_D2 B 9 TC_CLK O 107 U_RI_ I

139 PC_D3 B 8 TC_DATA O 104 U_RTS_ O

138 PC_D4 B 7 TC_ENABL O 111 USART_RX I

137 PC_D5 B 16 TC_I_CP_SW O 106 USART_TX O

136 PC_D6 B 19 TC_LD I 41 VC_IN LOG 1

135 PC_D7 B 13 TC_PUPLL O 43 VC_OUT LOG O

169 PC_RESET I 17 TC_PUREG O 1 VCC Digital Supply

170 PLL_TEST_PIN I 14 TC_PURXTX O 10 VCC Digital Supply

39 RSSI I 15 TC_PUVCO O 22 VCC Digital Supply

26 RXF_CLK O 18 TC_RXON O 113 VCC Digital Supply

36 RXF_D0 I 11 TC_TXON O 125 VCC Digital Supply

35 RXF_D1 I 159 TCK I 51 VCC Digital Supply

34 RXF_D2 I 160 TDI I 69 VCC Digital Supply

32 RXF_D3 I 162 TDO I 144 VCC Digital Supply

31 RXF_D4 I 167 TEST_CTRL I 82 VCC Digital Supply

30 RXF_D5 I 161 TMS I 96 VCC Digital Supply

29 RXF_D6 I 168 TST_ECK I 157 VCC Digital Supply

28 RXF_D7 I 12 TXPIN O 166 VCC Digital Supply

27 RXF_OE_ O 112 U_CD_ I 37 VDDAC

25 RXF_PD O 108 U_CTS_ I 164 XTAL1 I

24 RXMODE I 110 U_DSR_ I 165 XTAL2 I

23 RXPIN I 105 U_DTR_ O

Pin Summary – Pin Assignment in Alphabetical Order (Continued) Pin # Pin Name Type Pin # Pin Name Type Pin # Pin Name Type

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1612D–08/01 Signal Description – Pin Name Order I = Input, O = Output, B = Bidirectional, Analog I = Analog Input, Analog O = Analog Output Pin Name Type Description Supply Pins AGND Power Analog Ground AVCC Power Analog Supply GND Power Digital Ground VCC Power Digital Supply Global Pin PC_RESET I Global Reset pin Oscillator Pins XTAL1 I Crystal oscillator input XATL2 O Crystal oscillator output EXT_13_MHZ I 13 MHz input clock EXT_13_MHZ_OUT O 13 MHz output clock EXT_OSC I External oscillator input CLK_MODE1, CLK_MODE0 I Clock Frequency Configuration OSC_MODE I Internal/Extenal Clock Selector LFT PLL Filter PLL loop filter pin Memory Interface Pins CSFL16 O Chip select when 16-bit Flash is used CSSR O Chip select for low byte 8-bit SRAM CSFL O Chip select for low byte Flash CSSRH O Chip select for high byte SRAM CSFLH O Chip select for high byte Flash NWRITE O Memory write NREAD O Memory read NWORD I Selects between 8 and 16 memory access MEM_ADDR [18:0] O Memory Address Bus – Signals MEM_ADDR [18:0] are address-bus output lines of Flash and SRAM. MEM_DATA [7:0] B Memory Data Bus – Signals MEM_DATA [7:0] are the bi-directional data bus lines for the SRAM and Flash memory. MEM_DATAH [7:0] B Memory Data Bus – Signals MEM_DATAH [7:0] are the bi-directional data bus lines for the SRAM and Flash memory. These lines are used during 16-bit memory configuration. P_OR_UN I Selects whether PCMCIA or USB will have direct access to the memories. When “1” PCMCIA has direct access while when “0” USB has access

1612D–08/01 Baseband Interface Pins TC_CLK O Clock output for transceiver control bus TC_DATA O Data output for transceiver control bus TC_ENBL O Enable output for transceiver control bus TC_LD I Lock detect input TC_PU_REG O Transceiver voltage regulator power up TC_PU_PLL O Power up output for transceiver PLL TC_PU_VCO O VCO power up output TC_PU_RXTX O Power up output for Transmit/Receive sections of transceiver TC_RX_ON O RX section power up control output TC_TX_ON O TX section power up control output TC_I_CP_SW O Transceiver Current Pump external switch signal RSSI I Receive signal strength indicator input from transceiver TXPIN O Transmit data output to transceiver RXPIN I Receive data input from transceiver CLK_RXPIN I Clock driven to internal RxFront module RX_MODE I If “0”, internal clock recovery enabled and data extracted from external A/D. If “1” only BT packet processing carried out. Clock generation and recovery must be carried out externally RXF_PD O Power Down signal for external A/D RXF_CLK O Clock driven to external A/D RXF_OE_ O Output enable signal for external A/D RXF_D[7:0] I A/D RXF_D[7:0] output bus PCMCIA Interface Pins PC_A[14:0] I Address Bus – Signals A0 through A14 are address-bus input lines. Signal A0 is always used since the data interface is 8 bits wide. PC_D[7:0] B Data Bus – Signals D7 through D0 are the bi-directional data bus for PCMCIA. The most significant bit is D7. NWE I Write Enable – Used to strobe memory write data into the chip from the PCMCIA data bus. Should be deasserted during memory read cycles. It is used for both Common memory and Attribute memory accesses. NOE I Output Enable – Active low output enable signal. It is used to gate memory read data from the BT device onto PCMCIA data bus. It is used for Common memory accesses and Attribute memory Accesses. NCE1 I Card Enable – Used to enable even-numbered word address bytes. A0 is used to select between the even and odd number bytes within the addressed word Signal Description – Pin Name Order (Continued) I = Input, O = Output, B = Bidirectional, Analog I = Analog Input, Analog O = Analog Output Pin Name Type Description

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1612D–08/01 NIORD I I/O Read – Asserted by the host system to indicate to BT that a read from the I/O address space is required. The chip will not respond until it has been configured for I/O operation by the system. NIOWR I I/O Write – Asserted by the host system to indicate to the chip that a write to its I/O address space is required. The device will not respond until it has been configured for I/O operation by the system. NREG I Attribute Memory Select – Driven by the host to select between Attribute memory or I/O space (REG asserted) and Common memory (REG deasserted) in the device and the PCMCIA card. NWAIT O Extend Bus Cycle – This signal is asserted by the device to delay completion of the access cycle currently in progress. NINPACK O Input Acknowledge – It is asserted when the BT device is selected and can respond to an I/O read cycle at the address currently applied on the address bus. It is used by the host to control the enable of any input buffer between the card and the CPU. It will be inactive during card configuration. NIREQ O Interrupt Request – Asserted by the chip to indicate to the host that software service should take place. UART Interface Pins U_CTS_ I Clear To Send U_DSR_ I Data Set Ready U_DTR_ O Data Terminal Ready U_RI_ I Ring Indicator U_RTS_ O Request To Send USART_RX I Serial Input Port USART_TX O Serial Output Port U_CD_ I Carrier Detect USB Interface Pins DP B Upstream Plus USB I/O. This pin should be connected to CEXT through an external 1.5 kΩ pull-up resistor. DPLUS and DMINUS form the differential signal pin pairs connected to the Host Controller or an upstream Hub. DM B Upstream Minus USB I/O Analog Voice CODEC Pins VC_IN LOG I Voice Input VC_OUT LOG O Voice Output Digital Voice CODEC Pins ADO O Data Transmit ADI I Data Receive ACLK O Master Clock – Out ABCLK O Bit Clock – Out Signal Description – Pin Name Order (Continued) I = Input, O = Output, B = Bidirectional, Analog I = Analog Input, Analog O = Analog Output Pin Name Type Description

1612D–08/01 ASYNC O Frame Sync – Out ACLK_IN I Master Clock – In ABCLK_IN I Bit Clock – In ASYNC_IN I Frame Sync – In JTAG Pins DB_DATA O Debug data port DB_CLK O Debug clock port NTRST I JTAG reset input TCK I JATG clock TDI I JTAG data input TDO I JTAG data output TMS I JTAG master select input TEST Pins TEST_CTRL I For production test TEST_ECK I For production test PLL_TEST_PIN I For production test. Signal Description – Pin Name Order (Continued) I = Input, O = Output, B = Bidirectional, Analog I = Analog Input, Analog O = Analog Output Pin Name Type Description

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1612D–08/01 Functional Description – Pin Name Order Name Type Description Supply Pins AGND Power Analog Ground – used by the RSSI ADC, the Voice CODEC ADC and DAC AVCC Power Analog Supply – used by the RSSI ADC, the Voice CODEC ADC and DAC GND Power Digital Ground VCC Power Digital Supply Global Pin PC_RESET I Global Reset Pin Oscillator Pins XTAL1 I Crystal oscillator input XATL2 O Crystal oscillator output EXT_13_MHZ I 13 MHz input clock EXT_13_MHZ_OUT O 13 MHz output clock EXT_OSC I External oscillator input CLK_MODE1 Clock Frequency Configuration (see “Support for Different Operating Frequencies”) CLK_MODE0 I Clock Frequency Configuration (see “Support for Different Operating Frequencies”) OSC_MODE I Selects if the PLL will use the internal clock oscillator connected to the XTAL1, XTAL2 pins or an external clock oscillator connected to the EXT_OSC pin. LFT PLL Filter PLL loop filter pin Memory Interface Pins CSFL16 O Chip Select when 16-bit Flash is used CSSR O Chip select for low byte 8-bit SRAM CSFL O Chip select for low byte Flash CSSRH O Chip select for high byte SRAM CSFLH O Chip select for high byte Flash NWRITE O Memory write NREAD O Memory read NWORD I Selects between 8 and 16 memory access MEM_ADDR [18:0] O Memory Address Bus – Signals MEM_ADDR [18:0] are address-bus output lines of Flash and SRAM. MEM_DATA [7:0] B Memory Data Bus – Signals MEM_DATA [7:0] are the bi-directional data bus lines for the SRAM and Flash memory. MEM_DATAH [7:0] B Memory Data Bus – Signals MEM_DATAH [7:0] are the bi-directional data bus lines for the SRAM and Flash memory. These lines are used during 16-bit memory configuration P_OR_UN I Selects whether PCMCIA or USB will have direct access to the memories When “1” PCMCIA has direct access while when “0” USB has access

1612D–08/01 Baseband Interface Pins TC_CLK O Clock output for transceiver control bus TC_DATA O Data output for transceiver control bus TC_ENBL O Enable output for transceiver control bus TC_LD I Lock detect input TC_PUREG O Transceiver voltage regulator power up TC_PUPLL O Power up output for transceiver PLL TC_PUVCO O VCO power up output TC_PURXTX O Power up output for Transmit/Receive sections of transceiver TC_RXON O RX section power up control output TC_TXON O TX section power up control output TC_I_CP_SW O Transceiver Current Pump external switch signal RSSI I Receive signal strength indicator input from transceiver TXPIN O Transmit data output to transceiver RXPIN I Receive data input from transceiver CLK_RXPIN I Clock driven to internal RxFront module RXMODE I If “0”, internal clock recovery enabled and data extracted from external A/D. If “1” only BT packet processing carried out. Clock generation and recovery must be carried out externally. RXF_PD O Power Down signal for external A/D RXF_CLK O Clock driven to external A/D RXF_OE_ O Output enable signal for external A/D RXF_D[7:0] I A/D RXF_D[7:0] output bus PCMCIA Interface Pins PC_A[14:0] I Address Bus – Signals A0 through A14 are address-bus input lines. Signal A0 is always used since the data interface is 8-bits wide. PC_D[7:0] B Data Bus – Signals D7 through D0 are the bi-directional data bus for PCMCIA. The most significant bit is D7. NWE I Write Enable – Used to strobe memory write data into the chip from the PCMCIA data bus. Should be deasserted during memory read cycles. It is used for both Common memory and Attribute memory accesses. NOE I Output Enable – Active low output enable signal. It is used to gate memory read data from the BT device onto PCMCIA data bus. It is used for Common memory accesses and Attribute memory Accesses. NCE1 I Card Enable – Used to enable even-numbered word address bytes. A0 is used to select between the even and odd number bytes within the addressed word NIORD I I/O Read – Asserted by the host system to indicate to BT that a read from the I/O address space is required. The chip will not respond until it has been configured for I/O operation by the system. Functional Description – Pin Name Order (Continued) Name Type Description

16 AT76C551

1612D–08/01 NIOWR I I/O Write – Asserted by the host system to indicate to the chip that a write to its I/O address space is required. The device will not respond until it has been configured for I/O operation by the system. NREG I Attribute Memory Select – Driven by the host to select between Attribute memory or I/O space (REG asserted) and Common memory (REG deasserted) in the device and the PCMCIA card. NWAIT O Extend Bus Cycle – This signal is asserted by the device to delay completion of the access cycle currently in progress. NINPACK O Input Acknowledge – It is asserted when the BT device is selected and can respond to an I/O read cycle at the address currently applied on the address bus. It is used by the host to control the enable of any input buffer between the card and the CPU. It will be inactive during card configuration. NIREQ O Interrupt Request – Asserted by the chip to indicate to the host that software service should take place. UART Interface Pins U_CTS_ I Clear to Send U_DSR_ I Data Set Ready U_DTR_ O Data Terminal Ready U_RI_ I Ring Indicator U_RTS_ O Request to Send USART_RX I Serial input port USART_TX O Serial output port U_CD_ I Carrier Detect USB Interface Pins DP B Upstream Plus USB I/O. This pin should be connected to CEXT through an external 1.5 k Ω pull-up resistor. DPLUS and DMINUS form the differential signal pin pairs connected to the Host Controller or an upstream Hub. DM B Upstream Minus USB I/O Analog Voice CODEC Pins VC_IN LOG I Voice input VC_OUT LOG O Voice output Digital Voice CODEC Pins ADO O Data Transmit ADI I Data Receive ACLK O Master Clock – Out ABCLK O Bit clock – Out ASYNC O Frame Sync – Out ACLK_IN I Master Clock – In ABCLK_IN I Bit Clock – In ASYNC_IN I Frame Sync – In Functional Description – Pin Name Order (Continued) Name Type Description

1612D–08/01 Internal Architecture The AT76C551 chip is based on the ARM7TDMI processor. All modules are connected to the processor through a 32-bit bus including 32 KB internal SRAM. The processor operates at 24 MHz while low speed operation of the ARM ® processor and power-down of virtually all inter- faces is possible. ARM Core The controller contains the ARM7TDMI (ARM7) core, a 32-bit RISC processor. The ARM7 core can execute all the functionally called for by the Bluetooth specification. ARM7 supports two alternative instruction sets: 1. Powerful 32-bit code can be executed by the processor in ARM ® operating mode. 2. Thumb ®, which stores a subset of 32-bit instructions as compressed 16-bit instructions and decompresses them back to 32 bits upon execution. Utilization of Thumb mode will exploit full processor power with limited external memory resources. Note: ARM7TDMI operating mode can be changed at run time with negligible overhead. Memory Interface The memory interface interfaces the ARM processor to the 32K internal SRAM and external Flash and SRAM memory that accompanies a complete design. Flash memory contains the Bluetooth and Host Interface firmware and the Card Information Structure (CIS) used by the host PCMCIA subsystem. Either 8-bit or 16-bit Flash memories and 8-bit SRAMs can be used. The internal 32K SRAM memory accommodates ARM core stack, firmware status variables, structures supporting host/firmware interface and network data buffers. When the host driver software passes network data through the PCMCIA interface unit, the data can be automati- cally routed to either internal or external memories. Note: Firmware performance is optimized by permanently storing it in a slow Flash. Upon initialization it is loaded onto faster SRAM to fetch the instructions. External memory can be either 8-bit or 16-bit wide. External memory width is configured via the NWORD pin. When 8-bit memory is used, up to 512 kilobytes of SRAM and Flash memory is supported. When 16-bit memory is used, up to 1 megabyte of SRAM and Flash memory is supported. JTAG Pins DB_DATA O Debug data port DB_CLK O Debug clock port NTRST I JTAG reset input TCK I JATG clock TDI I JTAG data input TDO I JTAG data output TMS I JTAG master select input TEST Pins TEST_CTRL I For production test TEST_ECK I For production test PLL_TEST_PIN I For production test Functional Description – Pin Name Order (Continued) Name Type Description

18 AT76C551

1612D–08/01 The memory interface supports two ports for efficient use of the memory unit. Each port pro- vides access to all memories independently of the other. A round-robin priority scheme is used when both ports require access to the same memory. One port is dedicated to the ARM inter- face while the other can be used by either the PCMCIA interface or the USB interface. The selection is determined by the PC_OR_UN pin. PCMCIA Interface Unit The PCMCIA interface unit implements a PCMCIA 2.1/JEIDA 4.2 compatible 8-bit wide PC- card front-end interface. The PCMCIA interface unit provides the host with master access to internal/external SRAM and external Flash memory. The PCMCIA interface unit contains a number of general purpose registers to allow configuration and/or status information exchange between the host and Bluetooth firmware. Moreover, the PCMCIA interface unit provides the host and the ARM core with the capability to raise interrupts to each other. Consequently, the host driver software uses the PCMCIA interface unit to exchange configura- tion information, to monitor operation, to receive network indications and to transfer network data from/to network data buffers in SRAM. Baseband Processor The baseband processor unit carries out the low-level Bluetooth link functions. This unit has been designed to automatically handle many time-critical physical network management tasks used by the Bluetooth link control. Bluetooth Clock and Internal Hardware Timers A 28-bit counter running at 3.2 kHz provides the timing signals required for the baseband pro- cessing. Also other timers are included which provide general purpose interrupts or determine the timing of specific transceiver programming events. Frequency Hopping Sequence Generator The frequency hopping sequence generator chooses the correct hop frequency depending on the Bluetooth clock, the device address and the device mode. Access Code Generation and Detection This module generates the correct access code for access to other Bluetooth devices from the corresponding Lower Address Part (LAP) of the utilized Bluetooth Device address. A correla- tor is used to detect a Bluetooth transmission with a valid access code. Forward Error Correction (FEC) Two types of forward error correction are used. The first type is a simple 3-times repetition code where each bit is repeated three times. Majority decision decoding is used in the receiver. The second type of code is a (15,10) shortened Hamming code. The data is divided into 10-bit blocks. Each block is allocated a 15-bit code word. This code can correct all single-bit errors while it can detect double bit errors in each code word. Header Error Check (HEC) Dedicated header error generation and checking is provided to guarantee correct decoding of the important information included in the header. The generator calculates the HEC field in the header of a transmitted Bluetooth packet while the HEC detects corrupted packet headers. Cyclic Redundancy Generation and Check (CRC) A 16-bit CRC is used to protect the payload data transmitted using certain types of Bluetooth packets. During transmission, the CRC is automatically generated and appended at the end of the packet. Checking for received BT packets is a fully automated fund of the CRC in the ARM Core. It is a simple matter of checking the corresponding CRC status bit.

1612D–08/01 Encryption/ Decrytion Encryption and decryption is provided with the use of a secret key. Encryption and decryption are carried out on-the-fly with minimal intervention from the processor. The encryption/decryp- tion data are interchanged between the other Bluetooth low-level processing modules automatically. Authentication Processing Accelerator Processing-intensive authentication procedures are implemented in the hardware which reduce the time for authentication key production. Receiver Signal Strength Indicator (RSSI) This module provides a metric of the received signal strength of a Bluetooth transmission. It uses an 8-bit A/D to read the RSSI value of the transceiver. 64-byte TX and RX FIFOs A 64-byte Transmit and a 64-byte Receive FIFO are used to buffer data between the Blue- tooth baseband and the ARM processor. Baseband TX and RX Processing Sequencer Two dedicated sequencers are used, one for the Transmit direction and one for the Receive direction, these automate the Bluetooth packet transactions. These sequencers, in conjunction with firmware running on the ARM core, execute the link control functions. The sequencer is used to free the ARM processor from the sequencing of bit-level processing. The processing needed by the various Bluetooth packets differs from packet type-to-packet type. The processing sequencers can be programmed according to the different packet types and carry out the required processing functions without further ARM processor intervention for the transmission of corresponding packet. The baseband processor also eases the task of ensuring reliable data delivery. All bit-inten- sive tasks are done in hardware. The ARM core configures the modules and reads the results. Access code generation and correlation with received packet is carried out in hardware ensur- ing minimal decoding delay. With the firmware reading the results of a successful packet reception the HEC computation and header recognition is fully automated. The receive engine is automatically configured according to the packet header and, when required, payload header information, decodes the packet and stores it in the RX FIFO without further interven- tion from the processor. 8-bit ADC Interface for Bluetooth RX Data An 8-bit external interface is used to connect an external analog-to-digital converter providing the digital representation of the analog signal decoded by the transceiver during reception. The analog signal is sampled at 4M samples per second requiring an external ADC capable of handling this sample rate. Automatic DC- offset Cancellation and Symbol Recovery Modern low-cost transceivers used in FSK applications, employing open loop modulation and/or demodulation together with limiter-discriminator detection at the receiver, produce out- put baseband signals which suffer from moderate to severe DC-offset fluctuation. The useful signal is a small fraction of the magnitude of the maximum DC-offset fluctuation. The number of symbols available to a Bluetooth baseband controller for DC-offset compensation and sym- bol timing recovery (STR) purposes are a mere 4 preamble bits, preceding the device access code (DAC) in every packet. Fast symbol timing acquisition is a prerequisite to successful decoding of the DAC and synchronization to the master device in a Bluetooth piconet. Due to this fact and in order to comply with tight slot timing requirements, a state-of-the-art DC-offset canceller, bit-symbol recovery circuit has been integrated. This module is capable of recover- ing the original Bluetooth bitstream in the noisiest of environments.

20 AT76C551

1612D–08/01 Voice CODEC The voice CODEC module supports both CVSD (Continuous Variable Slope Delta) coding and log PCM coding (A-law and U-law). The coded voice data from both coding algorithms will be transferred with a constant bit rate of 64 kbits/sec. The voice CODEC hardware consists of the following modules: A digital-to-analog converter (D/AC) for converting linear PCM data to the analog domain, an analog-to-digital converter (ADC), a digital interface for connection of external integrated voice codecs, a codec submod- ule, which implements the CVSD and log PCM alogrithms and two 32-byte FIFOs which are capable of holding 4 ms of coded voice data in each direction. Interrupts are generated when a programmable level of data in the FIFOs has been reached. Two externally connected low- pass filters are required to use a microphone and earphones. Coded voice data from the Bluetooth interface can be transferred to an external voice codec through a digital interface. This interface can be configured as either a master or a slave. The interface accepts two possible clock formats: Short Frame Sync and Long Frame Sync. USB Function Interface The USB functionality is executed by an USB hardware block and firmware running on the ARM controller. This configuration allows acceleration of the intensive function processing while allowing flexibility in the implementation of higher level protocols over USB. The USB hardware block consists of a Serial Interface Engine (SIE), a Serial Bus Controller (SBC) and a System Interface. The SIE performs the clock/data separation, NRZI encoding and decoding, bit insertion and deletion, CRC generation and checking, and the serial-parallel data conversion. The SBC consists of a protocol engine and a USB device with 6 endpoints, each with dedicated double buffered FIFOs. One endpoint has an 8-byte FIFO, two endpoints have 16-byte FIFOs, two have 32-byte FIFOs and two have 128-byte FIFOs. The SBC man- ages the device address, monitors the status of the transactions, manages the FIFOs and communicates to the processor through a set of status and control registers. The System Interface connects the Serial Bus Controller to the processor.

16550 Compatible

The UART hardware module is a universal asynchronous receiver and transmitter with 16- byte Transmit and Receive FIFO. A programmable baud rate generator is provided to select, transmit and receive clock rates from 1200 bps to 921 Kbps. The input clock to the baud rate generator is generated from a 96 MHz clock (derived from the internal clock generator). The required division ratios and the relative error are shown in Table 1 for a 96 MHz clock.

serial and serial-to-parallel data conversions for both the transmitter and receiver sections. required with digital data systems. checked by the receiver for any transmission bit errors. periodic or one-shot fashion. MHz and 19.44 MHz. Table 2 shows the correct configuration for each frequency. Table 1. Need Table Caption Table 2. Correct Configuration Frequencies

22 AT76C551

Figure 1. Memory Map of Prototype Version

1612D–08/01 Register

Description

The Memory Controller Register Set can be configured to cooperate with various types of external Flash and SRAM memories. The configuration parameters are held by Memory Con- figuration Registers (MCR) which are mapped into AMBA ™ memory space. After AT76C551 resets, MCR default values guarantee correct operation of external Flash or SRAM memories connected to AT76C551. AT76C551 firmware adjusts MCR in order to achieve Flash and SRAM safe operation with minimum wait states. In the reset configuration the external Flash can be found at the bottom of the address map. If the bit 0 of the remap register is set high, then the Memory Controller switches to the normal memory map in where there is internal SRAM. SRAM Configuration Register (MCR0) addr: E00000 hex R/W 8 bits  Bit 7 – Reserved  Bits 6..4 – SWW[2:0] Number (0 - 7) of wait states during SRAM write cycles  Bit 3 – Reserved  Bits 2..0 – SWR[2:0] Number (0 - 7) of wait states during SRAM read cycles Note: Default Value: 77 hex Flash Memory Configuration Register (MCR1) addr: E00004 hex R/W 8 bits  Bits 7 – Reserved  Bits 6..3 Number (0 - 7) of wait states during write access of Flash memory latches  Bits 2..0 – FWR[2:0] Number (0 - 7) of wait states during Flash memory read cycles Note: Default Value: 07 hex Flash and Internal SRAM remap Register (MCR2) addr: E00008 hex R/W 8 bits  Bits 7..1 – Reserved  Bit 0 – REMAP Remap enable Note: Default Value: 00 hex

24 AT76C551

1612D–08/01 PCMCIA Configuration Registers The PCMCIA configuration registers are required by the PCMCIA standard. These registers are mapped into PCMCIA attribute memory space to allow the host to configure basic param- eters of the PCMCIA device. They are accessible by the host but they are not accessible by ARM core. COR: Configuration Option Register PCMCIA addr: 0800 hex R/W 8 bits  Bit 7 – SRES: System Reset By setting this bit, the device is reset in a way equivalent to PCMCIA hardware reset signal activation. Note: Tthis bit is not automatically cleared after set.  Bit 6 – IEVREQ Logic 1: Level mode interrupt. Logic 0: Pulse mode interrupt  Bits 5..0 – CFX[5:0]: Configuration Index This field is written with the index number of the entry in the card ’s configuration table which the host selects. When all the field bits are zero, the device is in memory only mode. Note: Default Value: 00 hex CSR: Configuration and Status Register PCMCIA addr: 0802 hex R/W 8 bits  Bits 7..6 – Reserved  Bit 5 – IOIS8 Logic 1: The host is only capable of 8-bit I/O accesses. Logic 0: The host is capable of 8-bit and 16-bit I/O accesses.  Bits 4..0 – Reserved Note: Default Value: 00 hex System Interface Registers The System Interface Registers (SIR) lie in the PCMCIA interface unit. They are mapped into PCMCIA I/O space, i.e. they are directly accessible by the host but they are not directly acces- sible by the ARM core. They allow the host to configure and communicate with AT76C551 through host I/O space. Note: All AMBA memory space (16M bytes address space) can be accessed by the host through the PCMCIA interface unit, via SIR1 - SIR5. SIR0 – GCR: General Configuration Register PCMCIA addr: 0000 hex R/W 8 bits Bit 7 – SWRES: Software Reset By setting this bit, all SIR registers are reset. However, AT76C551 units on the AMBA bus (ARM core, PAI, etc.) are not be reset by SWRES bit activation. This bit is automatically cleared after set.

1612D–08/01  Bit 6 – CORES: Core Reset While this bit is set, AT76C551 units on the AMBA bus (including ARM core) are held in reset state. When this bit is cleared, AT76C551 units on the AMBA bus exit reset state and ARM core, in particular, begins code execution by fetching its reset exception vector. Note: This bit is not automatically cleared after it is set.  Bit 5 – 16/8-bit: 16/8-bit Access Mode If set, enables the 16-bit access of PCMCIA module with the system memory. If cleared, the access is 8-bit (see SIR1 - SIR5).  Bit 4 – Reserved  Bit 3 – AIH: ARM Interrupt to Host This bit is set if an interrupt to the host has been generated by the ARM core (see bit AIH of MIR0) and is still pending. To acknowledge the interrupt and clear this bit, the host driver soft- ware must write 1 on this bit.  Bit 2 – HIA: HOst Interrupt to ARM When this bit is set by the host, an interrupt to the ARM core is generated (see bit HIA of MIR0). This bit is automatically cleared when the ARM core acknowledges the interrupt (see MIR0).  Bit 1 – AIHEN: ARM to Host Interrupt Enable Logic 0: Interrupts from ARM core to the host disabled Logic 1: Interrupts from ARM core to the host enabled  Bit 0 – Reserved Note: Default Value: 00 hex – The host driver software is responsible for AT76C551 reset. The host driver software has to set CORES bit of GCR first. This will reset ARM core and all other units on AMBA bus. The host driver must next set SWRES bit of GCR. This will reset SIR and clear both CORES and SWRES bits, forcing ARM core to leave reset state and begin firmware pro- gram execution. SIR1 – AMBA BSR: Bank Select Register PCMCIA addr: 0001 hex R/W 8 bits  Bits 7..4 – AD[23:20] This register is used by the host in conjunction with SIR2, SIR3, SIR4 and SIR5 in order to access AMBA bus resources (Flash and internal or external SRAM) through the PCMCIA interface unit. Each time DLR (SIR4) is accessed, the AMBA Bank Select Register (BSR) drives AMBA address lines 23 … 20 and 18 … 15. AMBA address line 19 is always driven to logic 0.  Bits 3..0 – AD[18:15] Note: Default Value: 00 he SIR2 – AMBA ALSR: Address Low Select Register PCMCIA addr: 0002 hex R/W 8 bits  Bits 7..0 – AD[7:0] This register is used by the host in conjunction with SIR1, SIR3, SIR4 and SIR5 in order to access AMBA bus resources (Flash and internal or external SRAM) through the PCMCIA interface unit. Each time SIR4 is accessed, the AMBA ALSR drives AMBA address lines 7..0. Note: Default Value: 00 hex

26 AT76C551

1612D–08/01 SIR3 – AMBA AHSR: Address High Select Register PCMCIA addr: 0003 hex R/W 8 bits  Bit 7 – Reserved  Bits 6..0 – AD[14:8] This register is used by the host in conjunction with SIR1, SIR2, SIR4 and SIR5 in order to access AMBA bus resources (Flash and internal or external SRAM) through the PCMCIA interface unit. Each time SIR4 is accessed, the AMBA AHSR drives AMBA address lines 14..8. Note: Default Value: 00 he SIR4 – AMBA I/O DLR: Data Low Register PCMCIA addr: 0004 hex R/W 8 bits  Bits 7..0 – D[7:0] This register is used by the host in conjunction with SIR1, SIR2, SIR3 and SIR5 in order to access AMBA bus resources (Flash and internal or external SRAM) through the PCMCIA interface unit. Note: Default Value: 00 hex Writing the AMBA DLR initiates an AMBA write cycle. AMBA address lines are driven by SIR1, SIR2 and SIR3 while AMBA data lines are driven by SIR4 and SIR5. As a result an AMBA resource is written. Reading the AMBA DLR initiates an AMBA read cycle. AMBA address lines are driven by SIR1, SIR2 and SIR3 while AMBA data lines are reflected to SIR4 and SIR5. As a result, an AMBA resource is read. SIR5 – AMBA I/O DHR: Data High Register PCMCIA addr: 0005 hex R/W 8 bits This register is used by the host in conjunction with SIR1, SIR2, SIR3 and SIR4 in order to access 16-bit AMBA bus resources (Flash and internal or external SRAM) through the PCM- CIA interface unit. Note: Default Value: 00 hex Writing/reading SIR4 causes an AMBA write/read cycle. During this cycle the SIR4 is con- nected to AMBA data lines 7..0 while the AMBA Data High Register (DHR) is connected to AMBA data lines 15..8. In order to write a 16-bit AMBA resource, the first most significant 8-bit write the AMBA DHR and second least significant 8-bit write the AMBA DLR. Writing to the AMBA DLR initiates the AMBA write cycle. In order to read a 16-bit AMBA resource, the least stanching 8 bits must be read first for AMBA DLR and secondly the most significant 8 bits are read for AMBA DHR. Reading the AMBA DLR initiates the AMBA read cycle. Note: Writing/reading only the AMBA DHR without writing/reading the AMBA DLR does not cause an AMBA write/read cycle.

1612D–08/01  SIR6 – GPR1: General Purpose Register 1 GPR1 PCMCIA addr: 0006 hex W 8 bits  Bits 7..0 – GPR1[7:0] core can read them. Note: Default Value: 00 hex SIR7 – GPR2: General Purpose Register 2 PCMCIA addr: 0007 hex 8 bits  Bits 7..0 – GPR2[7:0] core can read them. Note: Default Value: 00 hex SIR8 – GPR3: General Purpose Register 3 PCMCIA addr: 0008 hex W 8 bits  Bits 7..0 – GPR3[7:0] core can read them. Note: Default Value: 00 hex In general, General Purpose Registers provide a means of one-way communication from the host driver software to AT76C551 firmware. Each GPR bit, or field, can carry any kind of infor- mation (configuration information, status information, command signaling) required by the interface between host driver software and AT76C551 firmware.  SIR9 – MR1: Mirror Register 1 PCMCIA addr: 000E hex R 8 bits  Bits 7..0 – MR1[7:0] the ARM core. Note: Default Value: 00 hex SIR10 – MR2: Mirror Register 2 PCMCIA addr: 000F hex R 8 bits  Bits 7..0 – MR2[7:0] the ARM core. Note: Default Value: 00 hex SIR11 – MR3: Mirror Register 3 PCMCIA addr: 0010 hex R 8 bits  Bits 7..0 – MR3[7:0] the ARM core. Note: Default Value: 00 hex

28 AT76C551

1612D–08/01 SIR12 – MR4: Mirror Register 4 PCMCIA addr: 0011 hex R 8 bits  Bits 7..0 – MR4[7:0] which can be written by the ARM core. SIR13 – MR5: Mirror Register 5 PCMCIA addr: 0012 hex R 8 bits  Bits 7..0 – MR5[7:0] the ARM core. Note: Default Value: 00 hex SIR14 – MR6: Mirror Register 6 PCMCIA addr: 0013 hex R 8 bits  Bits 7..0 – MR6[7:0] the ARM core. Note: Default Value: 00 hex SIR15 – MR7: Mirror Register 7 PCMCIA addr: 0014 hex R 8 bits  Bits 7..0 – MR7[7:0] the ARM core. Note: Default Value: 00 hex SIR16 – MR8: Mirror Register 8 PCMCIA addr: 0015 hex R 8 bits  Bits 7..0 – MR8[7:0] the ARM core. Note: Default Value: 00 hex In general, Mirror Registers provide a means of one-way communication from AT76C551 firm- ware to the host driver software. See also MIR0 - MIR3.

1612D–08/01 MAC Interface Registers MAC Interface Registers (MIR) lie in the PCMCIA interface unit. They are mapped into AMBA memory space, i.e. they are directly accessible by the ARM core but they are not directly accessible by the host. MIRs allow AT76C551 firmware to communicate with the host and to generate interrupts to the host processor. MIR0 – PIR1: Processor Interface Register 1 addr: 800000 hex R/W 16 bits  Bits 15..4 – PIR1[15:4] General purpose I/O  Bit 3 – HIA: Host Interrupt to ARM This bit is set if an interrupt to the ARM core has been generated by the host (see bit HIA of SIR0) and is still pending. To acknowledge the interrupt and clear this bit, AT76C551 firmware must write 1 on this bit.  Bit 2 – AIH: ARM Interrupt to Host When this bit is set by the ARM core, an interrupt to the host is generated (see bit AIH of SIR0). This bit is automatically cleared when the host acknowledges the interrupt.  Bit 1 – HIAEN: Host to ARM Interrupt Enable Logic 0: Interrupts from the host to ARM core disabled Logic 1: Interrupts from the host to ARM core enabled  Bit 0 – Reserved Note: Default Value: 0000 hex MIR1 – PIR2: Processor Interface Register 2 addr: 800004 hex R/W 16 bits  Bits 15..8 – PIR2[15:8] General purpose I/O  Bits 7..0 – PIR2[7:0] General purpose I/O Note: Default Value: 0000 hex Table MIR2 – PIR3: Processor Interface Register 3 addr: 800008 hex R/W 16 bits  Bits 15..8 – PIR3[15:8] General purpose I/O  Bits 7..0 – PIR3[7:0] General purpose I/O Note: Default Value: 0000 hex

30 AT76C551

1612D–08/01 MIR3 – PIR4: Processor Interface Register 4 addr: 80000C hex R/W 16 bits  Bits 15..8 – PIR4[15:8] General purpose I/O  Bits 7..0 – PIR4[7:0] General purpose I/O Note: Default Value: 0000 hex MIR0 – MIR3 provide a means of one-way communication from AT76C551 firmware to the host driver software. Each MIR bit, or field, can carry any kind of information required by the interface between host driver software and AT76C551 firmware. The MIR4-MIR5 provide a means of one-way communication from the host driver software to AT76C551 firmware. See also GCR (SIR0) and GPR1 - GPR3 (SIR6 - SIR8). MIR4 – PIR5: Processor Interface Register 5 addr: 800010 hex R/W 16 bits  Bits 15..8 – PIR5[15:8] General purpose I/O  Bits 7..0 – PIR5[7:0] General purpose I/O Note: Default Value: 0000 hex MIR5 – PIR6: Processor Interface Register 6 addr: 800014 hex R/W 16 bits  Bits 15..8 – PIR6[15:8] General purpose I/O  Bits 7..0 – PIR6[7:0] General purpose I/O Note: Default Value: 0000 hex

band registers, grouped in functional sections. Table 3. Bluetooth Register Set Address1 600004 Access code, packet encoding, encryption, etc.

32 AT76C551

Table 3. Bluetooth Register Set (Continued)

1612D–08/01 Address0 addr: 600000 hex R/W 32 bits  Bits 31..0 – ADDR[31:0] Sets ADDR field, used in access code generation, packet encoding, encryption and frequency hopping. Note: Default Value: 00000000 hex Address1 addr: 600004 hex R/W 32 bits  Bits 15..0 – ADDR[47:32] Sets ADDR field, used in access code generation, packet encoding, encoding and frequency hopping.  Bits 31..16 – Reserved Note: Default Value: 00000000 hex Pgrsp_counter addr: 600008 hex R/W 32 bits  Bits 31..5 – Reserved  Bits 4..0 – PageRspCounter[4:0] Sets page response counter value to be used for page response routine and data whitening initialization prior FHS packet transmission or reception. Note: Default Value: 00000000 hex Parity0 addr: 60000C hex R/W 32 bits  Bits 31..0 – ParityBits[31:0] When channel access code is generated from FHS syncword, sets the ParityBits[31:0] to be used in channel access code construction. When channel access code is generated from BD_ADDR only, gets the ParityBits[31:0] of the channel access code. Note: Default Value: 00000000 hex Parity1 addr: 600010 hex R/W 32 bits  Bits 31..2 – Reserved  Bits 1..0 – ParityBits[33:32] When channel access code is generated from FHS syncword, sets the ParityBits[33:32] to be used in channel access code construction. When channel access code is generated from BD_ADDR only, gets the ParityBits[33:32] of the channel access code Note: Default Value: 00000000 hex

34 AT76C551

1612D–08/01 RSSI_CtrlStatus addr: 600014 hex R/W 32 bits  Bits 31..16 – Reserved  Bits 15..8 R – ADC data Result of last conversion (last RSSI value sampled)  Bit 7 – R ADC Status Set by hardware when conversion procedure has been completed  Bits 6..4 – Reserved  Bits 3..2 W – ADC Mode 00: ADC idle 01: One shot conversion 10: Continuous conversion  Bit 1 – W ADC Start Set by firmware to start a conversion procedure when ADC mode is “one shot conversion ” (auto-clear).  Bit 0 – W ADC Power 0: ADC off 1: ADC on Note: Default Value: 0000 hex Controlstatus1 addr: 600018 hex R/W 32 bits  Bits 31..19 – Reserved  Bits 18..9 – Packet_header Sets packet header before packet TX. Gets packet header after packet header RX during packet RX.  Bits 8..0 – Payload_length Sets payload body length before data packet TX Gets payload body length after payload header RX during packet RX Note: Default Value: 00000000 hex CtrlStatus2 addr: 60001C hex R/W 32 bits  Bits 31..20 – Reserved  Bit 19 R – AccCodeBusy Set by hardware during access code calculation or transmission  Bit 18 R – CipherBusy Set by hardware during ciphering/deciphering  Bit 17 R – E_funBusy Set by hardware during E_function calculation

1612D–08/01  Bit 16 R – TxDataBusy Set by hardware while TX data is being streamed out  Bit 15 R – RxDataBusy Set by hardware while RX data is being streamed in  Bits 14...13 W – E_funType Selects the type of E function to be calculated 00: E1 (used for authentication) 01: E21 (used for link key generation) 10: E22 (used for link key generation) 11: E3 (used for encryption key generation)  Bit 12 R/W – EfunEnblBusy Set by firmware to start E function calculation Reset by hardware when calculation is complete  Bit 11 W – CipherMode 0: No encryption used 1: Packet payload is encrypted in TX and decrypted in RX  Bits 10..4 W – CorrelThresh Sliding correlator threshold value, default = 51 Sets sliding correlator sensitivity.  Bit 3 W– GetFHS_syncword Set by firmware to start access code recovery from LAP and FHS packet parity bits. Auto-clear  Bit 2 W – EvalAccCode Set by firmware to start access code calculation from BD_ADDR only. Auto-clear  Bit 1 W – AccCodeType 0: Access code TXed (and loaded on sliding correlator) has no trailer bits, thus access code size is 68 bits. 1: Access code TXed (and loaded on sliding correlator) has trailer bits, thus access code size is 72 bits.  Bit 0 W – RxFHS 0: The packet expected to be RXed is not an FHS packet. 1: An FHS packet RX is expected. Note: Default Value: 00000000 hex CLKN addr: 600020 hex R 32 bits Bits 31..28 – Reserved

36 AT76C551

1612D–08/01  Bits 27..0 – CLKN[27:0] Provides native clock current value to firmware. Note: Default Value: 00000000 hex CLOCK addr: 600024 hex R/W 32 bits  Bits 31..28 – Reserved  Bits 27..0 – CLOCK[27:0] In this register specific fields of device ’s native clock or of transmitter ’s estimated in receiver native clock are set. Note: Default Value: 00000000 hex CLKPhase addr: 600028 hex R/W 32 bits  Bits 31..15 – Reserved  Bits 14..0 – CLKPhase[14:0] Provides native clock phase current value to firmware. Native clock phase is estimated in sys- tem clock cycles. Note: Default Value: 00000000 hex CLKPhaseCorrelCorrect addr: 60002C hex R/W 32 bits  Bits 31..15 – Reserved  Bits 14..0 CLKPhase_, Correl_, Correct[14:0] Provides slave’s hardware with the proper native clock phase value just after correlator trigger. At this moment slave ’s hardware automatically adjusts CLKN with CLKN of corresponding master. Note: Default Value: 00000000 hex CLKPhaseLimit addr: 600030 hex R/W 32 bits  Bits 31..15 – Reserved  Bits 14..0 – CLKPhase_, Limit[14:0] Sets native clock phase maximum value in system clock cycles. Effectively sets half-slot dura- tion in system clock cycles. Note: Default Value: 00000000 hex CLKPhaseWhenCorrel addr: 600034 hex R/W 32 bits  Bits 31..15 – Reserved  Bits 14..0 – CLKPhase_, When_, Correl[14:0] Samples and holds native clock phase at correlator trigger. Thus enables slave-to-master clock drift estimation. Note: Default Value: 00000000 hex

1612D–08/01 CLKCtrl addr: 600038 hex R/W 32 bits  Bits 31..4 – Reserved  Bit 3 – cmpCLKN0_invert 0: Native clock bit 0 is not inverted for timer comparisons. 1: Native clock bit 0 is inverted for timer comparisons. Bit 3 value is “don’t care” if bit 0 of the register is reset.  Bit 2 – ForcePhase_, Adjust Set by firmware to force native clock phase adjustment, i.e. set native clock phase equal to CLKPhaseCorrelCorrect register contents. Auto-clear.  Bit 1 – AutoPhaseAdjust 0: Native clock phase is not auto-adjusted. 1: Native clock phase is auto-adjusted, i.e. set equal to CLKPhaseCorrelCorrect register con- tents just after each correlator trigger.  Bit 0 – cmpCLKN0_ enable 0: Compare timer event is generated when compare timer bits 14 - 0 are equal to native clock phase. 1: Compare timer event is generated when compare timer bits 14 - 0 are equal to native clock phase AND compare timer bit 15 is equal to native clock bit 0 (possibly inverted). Note: Default Value: 00000000 hex CmpTimer_RxTxStart addr: 60003C hex R/W 32 bits  Bits 15..0 – CmpTimer_, RxTxStart[15:0] Sets compare timer for packet RX or TX procedure start Note: Default Value: 00000000 hex CmpTimer_GenPurpose addr: 600040 hex R/W 32 bits  Bits 15..0 – CmpTimer_, GenPurpose[15:0] Sets general purpose compare timer Note: Default Value: 00000000 hex Compare timers are used to notify an event during a full-slot or a half-slot. Each compare timer is compared to current native clock phase. Optionally, MSB of each compare timer can be compared to bit 0 of native clock (possibly inverted). When compare timer matches current native clock phase and current native clock bit 0, the corresponding event is generated. CmpTimer_RxTxStart generates a maskable interrupt and starts RX or TX procedure, if the corresponding bit of TcCommand register has been set. CmpTimer_GenPurpose only generates a maskable interrupt.

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1612D–08/01 RxTxSettleTimes addr: 600044 hex R/W 32 bits  Bits 31..24 – Reserved  Bits 23..16 – TC_TXON, settleTime[7:0] Microseconds from TC_TXON rise to outgoing packet data transmission.  Bits 15..8 – TC_RXON, settleTime[7:0] Microseconds from TC_RXON rise to correlator activation.  Bits 7..0 – TC_PURX/TX, settleTime[7:0] Microseconds from TC_PURX/TX rise to TC_TXON or TC_RXON rise. Note: Default Value: 00000000 hex TcCtrlStatus addr: 600048 hex R/W 32 bits  Bits 31..9 – Reserved  Bit 8 TC_LD Reflects transceiver TC_LD pin level  Bit 7 R/W – TC_PUREG Sets transceiver TC_PUREG pin level  Bit 6 R/W – TC_PUVCO Sets transceiver TC_PUVCO pin level  Bit 5 R/W – TC_PUPLL Sets transceiver TC_PUPLL pin level  Bit 4 R/W – TC_PURXTX Sets transceiver TC_PURXTX pin level, when bit 1 of this register is reset  Bit 3 R/W – TC_RXON Sets transceiver TC_RXON pin level, when bit 1 of this register is reset  Bit 2 R/W – TC_TXON Sets transceiver TC_TXON pin level, when bit 1 of this register is reset  Bit 1 R/W – RX/TX_auto Selects control mode for transceiver signals TC_RXON, TC_TXON & TC_PURXTX 1: The transceiver signals are controlled automatically. 0: The transceiver signals are set to reflect bits 4...2 of this register. Sets transceiver TC_I_CP_SW pin level Note: Default Value: 00000000 hex TcCommand addr: 60004C hex W 32 bits  Bits 31..3 – Reserved  Bit 2 – RxEnable Set by firmware to start a RX cycle at then next event generated by compare timer CmpTimer_RxTxStart

1612D–08/01  Bit 1 – TxEnable Set by firmware to start a RX cycle at then next event generated by compare timer CmpTimer_RxTxStart.  Bit 0 – RxTx_, Abort Set by firmware to immediately abort current RX or TX cycle, or to cancel the programmed RX or TX cycle due to start. Note: Default Value: 00000000 hex Provided that bit 1 of TcCtrlStatus register is set the Bluetooth baseband processor has the ability to automatically generate the sequence of signals necessary to implement TX and RX. To initiate an automatic RX cycle, the firmware has to program CmpTimer_RxTxStart register and then set bit 2 of TcCommand register. When the compare timer generates its event the RX cycle begins and PU_RX/TX signal is raised. After PU_RX/TX settle time the RX_ON sig- nal is raised. After RX_ON settle time baseband data acquisition circuits are enabled and the correlator begins to search for a known access code. If correlator is triggered, then the correla- tor is powered down and RX packet data is acquired. After RX packet completion the RX cycle ends and the transceiver is powered down. Note: The transceiver and the correlator will be held active until correlator trigger occurs, or RX cycle is aborted by firmware, i.e. firmware sets bit 0 of TcCommand register. To initiate an automatic TX cycle the firmware has to program CmpTimer_RxTxStart register and then set bit 1 of the TcCommand register. When the compare timer generates its event, the TX cycle begins and PU_RX/TX signal is raised. After PU_RX/TX settle time the TX_ON signal is raised causing TX ramp rise. While TX ramp rises, the transmitter is fed with a 0/1- alternating data stream. After TX_ON settle time (which should include TX ramp set time), the actual TX packet data stream is given to the transceiver. After TX packet completion, the TX cycle ends and the transceiver is powered down. A RX or TX automatic cycle can be aborted at any moment. To abort a current RX or TX cycle the firmware will set bit 0 of TcCommand register. This will power down the transceiver and reset all baseband internal state machines to an idle state. To cancel the program, which has not yet started, RX or TX automatic cycle firmware can also use bit 0 of TcCommand register. Note: Please note that the baseband is aware of RX or TX packet type and length therefore it has the ability to trace RX or TX packet fields and decide the FEC encoding, CRC calculation, etc. TcProg addr: 600050 hex R/W 32 bits  Bits 31..26 – Reserved  Bit 25 – 3wb_, EnableBusy Set by firmware to initiate serial data send on the 3-wire bus. Reset by hardware to indicate that 3-wire bus access is complete.  Bit 2 – 3wb_,ClockRate 0: 3-wire bus clock is generated by system clock division by 4. 1: 3-wire bus clock is generated by system clock division by 8.

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1612D–08/01  Bits 23..0 – 3wb_, Data[23:0] 24-bit data word to be send on the 3-wire bus. MSB is sent first. Note: Default Value: 00000000 hex IntStatus addr: 600054 hex R 32 bits  Bits 31..13 – Reserved  Bit 12 – TxFifoAlmEmpty_IntStatus TX FIFO almost empty interrupt status.  Bit 11 – RxFifoAlmFull_IntStatus RX FIFO almost full interrupt.  Bit 10 – GenPurpTim_ IntStatus General purpose compare timer interrupt.  Bit 9 – TxAcCodeComplete_IntStatus RX/TX start compare timer interrupt enable.  Bit 8 – RxTxStart_ IntStatus RX/TX start compare timer interrupt.  Bit 7 – TxPktComplete_IntStatus TX packet completion interrupt.  Bit 6 – RxCorrelTrig_ IntStatus Correlator trigger interrupt.  Bit 5 – RxHecFail_IntStatus HEC fail interrupt.  Bit 4 – RxCrcFail_ IntStatus CRC fail interrupt.  Bit 3 – RxFecFail_ IntStatus FEC fail interrupt.  Bit 2 – RxPktHeaderRdy_IntStatus RX packet header arrival interrupt.  Bit 1 – RxPayHeaderRdy_IntStatus RX payload header arrival interrupt.  Bit 0 – RxPayloadRdy_IntStatus RX payload completion interrupt. Note: Default Value: 00000000 hex IntMask addr: 600058 hex R/W 32 bits  Bits 31..13 – Reserved  Bit 12 – TxFifoAlmEmpty_IntEnable TX FIFO almost empty interrupt enable.

1612D–08/01  Bit 11 – RxFifoAlmFull_ IntEnable RX FIFO almost full interrupt enable.  Bit 10 – GenPurpTim_IntEnable General purpose compare timer interrupt enable.  Bit 9 – TxAcCodeComplete_IntEnable TX of Access Code has been completed.  Bit 8 – RxTxStart_ IntEnable RX/TX start compare timer interrupt enable.  Bit 7 – TxPktComplete_IntEnable TX packet completion interrupt enable.  Bit 6 – RxCorrelTrig_IntEnable Correlator trigger interrupt enable.  Bit 5 – RxHecFail_IntEnable HEC fail interrupt enable.  Bit 4 – RxCrcFail_IntEnable CRC fail interrupt enable.  Bit 3 – RxFecFail_IntEnable FEC fail interrupt enable.  Bit 2 – RxPktHeaderRdy_IntEnable RX packet header arrival interrupt enable.  Bit 1 – RxPayHeaderRdy_IntEnable RX payload header arrival interrupt enable.  Bit 0 – RxPayloadRdy_IntEnable RX payload completion interrupt enable. Note: Default Value: 00000000 hex IntClear addr: 60005C hex W 32 bits  Bits 31..11 – Reserved  Bit 10 – GenPurpTim_IntClear Clears general purpose compare timer interrupt  Bit 9 – TxAcCodeComplete_IntClear Clears access Code Tx completed interrupt  Bit 8 – RxTxStart_IntClear Clears RX/TX start compare timer interrupt  Bit 7 – TxPktComplete_IntClear Clears TX packet completion interrupt  Bit 6 – RxCorrelTrig_IntClear Clears correlator trigger interrupt  Bit 5 – RxHecFail_IntClear

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1612D–08/01 Clears HEC fail interrupt  Bit 4 – RxCrcFail_IntClear Clears CRC fail interrupt  Bit 3 – RxFecFail_IntClear Clears FEC fail interrupt  Bit 2 – RxPktHeaderRdy_IntClear Clears RX packet header arrival interrupt  Bit 1 – RxPayHeaderRdy_IntClear Clears RX payload header arrival interrupt  Bit 0 – RxPayloadRdy_IntClear Clears RX payload completion interrupt All events related to packet RX/TX as well as events generated by compare timers can acti- vate the “Bluetooth Baseband ” system interrupt. Conditions related to Bluetooth Baseband FIFOs can activate “Bluetooth Baseband FIFOs” system interrupt. Each event related to packet RX/TX, or generated by a compare timer, is always latched on the corresponding bit of IntStatus register. The bit is set when the event occurs. The bit is reset when the corresponding bit of IntClear register is set by the firmware to acknowledge the event. However, an event related to packet RX/TX or generated by a compare timer will produce an interrupt only if the corresponding bit of IntMask register has been set by firmware. Conditions related to Bluetooth Baseband FIFOs are “TX FIFO almost full ” and “RX FIFO almost empty”. These conditions are not latched, but just reflected on the corresponding bits of IntStatus register. Bluetooth Baseband FIFO conditions have no corresponding bits in IntClear register, because they will be automatically reset after proper FIFO service by firmware. Bluetooth Baseband FIFO conditions will produce an interrupt only if the corresponding bit of IntMask register has been set by firmware. RxFifoCtrlStatus addr: 600060 hex R/W 32 bits  Bits 31..15 – Reserved  Bit 14 R – Empty Set by hardware while FIFO is empty  Bit 13 R Full – Set by hardware while FIFO is full  Bit 12 W – Reset Set by firmware to discard any possible FIFO contents. Auto-clear. Set by firmware to define the minimum level at which FIFO is considered “almost full” Current FIFO level, i.e. number of received bytes into FIFO waiting to be read Note: Default Value: 00000000 hex RxFifoReadPort addr: 600064 hex R 32 bits

1612D–08/01  Bits 31..8 – Reserved  Bits 7..0 – RX_byte[7:0] Least recent received byte not yet read Note: Please note that reading RxFifoReadPort register is meaningful only if RX FIFO level is at least one, i.e. at least one byte exists in RX FIFO. If RX FIFO is not serviced before it is full it will overflow and subsequent bytes received will be lost. RX FIFO capacity is 64 bytes. TxFifoCtrlStatus addr: 600068 hex R/W 32 bits  Bits 31..15 – Reserved  Bit 14 R – Empty Set by hardware while FIFO is empty  Bit 13 R – Full Set by hardware while FIFO is full  Bit 12 W – Reset Set by firmware to discard any possible FIFO contents. Auto-clear Set by firmware to define the maximum level at which FIFO is considered “almost empty”. Current FIFO level, i.e. number of bytes written into FIFO, waiting to be transmitted. Note: Default Value: 00000000 hex TxFifoWritePort addr: 60006C hex W 32 bits  Bits 31..8 – Reserved  Bits 7..0 – TX_byte[7:0] Next byte to transmit Note: Writing TxFifoWritePort register is not permitted if TX FIFO is full. If TX FIFO is not serviced before it is empty it will underflow and transmitted bytes will be lost. TX FIFO capacity is 64 bytes. hopSelCtrlStatus addr: 600070 hex RW 32 bits Bits 31..4 – Reserved  Bit 4..3 – Hop_Type Indicates frequency hop type (page, inquiry, etc.).  Bit 2 – Hop_Kernel_Direct 0: Hop selection calculation parameters (A,B,.X,Y1,.) are estimated by hardware. 1: Hop selection calculation parameters are provided directly by firmware.  Bit 1 – Mode_79_23 0: 79 Frequency Hop System

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1612D–08/01 1: 23 Frequency Hop System  Bit0 – HopSelEnable_Busy Set by firmware and enables hardware frequency pointer calculation. Cleared by hardware when calculation is finished Note: Default Value: 00000000 hex hopSel_ABCDE addr: 600074 hex RW 32 bits  Bits 31..30 – Reserved Hop kernel register A Hop kernel register B Hop kernel register C Hop kernel register D  Bits 6..0 – E[4:0] Hop kernel register E Note: Default Value: 00000000 hex hopSel_FXY1Y2 addr: 600078 hex RW 32 bits  Bits 31..30 – Reserved Hop kernel register F Hop kernel register X Hop kernel register Y1 Hop kernel register Y2 Note: Default Value: 00000000 hex RxFrontReg addr: 60007C hex W 32 bits Bits 31..24 – Reserved  Bits 22..20 – RxFront_n_C[3:0]  Bits 18..16 – RxFront_n_A[3:0]  Bits 15..8 – RxFrontThresh_A[7:0]  Bits 7..0 – RxFrontThreshB[7:0] Note: Default Value: 00000000 hex

1612D–08/01 Kc0 addr: 600080 hex W 32 bits  Bits 31..0 – Kc0[31:0] Key used for encryption Note: Default Value: 00000000 hex Kc1 addr: 600084 hex W 32 bits  Bits 31..0 – Kc1[31:0] Key used for encryption Note: Default Value: 00000000 hex Kc2 addr: 600088 hex W 32 bits  Bits 31..0 – Kc2[31:0] Key used for encryption Note: Default Value: 00000000 hex Kc3 addr: 60008C hex W 32 bits  Bits 31..0 – Kc3[31:0] Key used for encryption Note: Default Value: 00000000 hex ArReg0 addr: 600090 hex RW 32 bits  Bits 31..0 – ArReg0[31:0] Used in E_functions.Initialized by firmware and is set by hardware with E_function result. Note: Default Value: 00000000 hex ArReg1 addr: 600094 hex RW 32 bits  Bits 31..0 – ArReg1[31:0] Used in E_functions. Initialized by firmware and is set by hardware with E_function result. Note: Default Value: 00000000 hex

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1612D–08/01 ArReg2 addr: 600098 hex RW 32 bits  Bits 31..0 – ArReg2[31:0] Used in E_functions. Initialized by firmware and is set by hardware with E_function result. Note: Default Value: 00000000 hex ArReg3 addr: 60009C hex RW 32 bits  Bits 31..0 – ArReg3[31:0] Used in E_functions. Initialized by firmware and is set by hardware with E_function result. Note: Default Value: 00000000 hex KeyReg0 addr: 60000 hex RW 32 bits  Bits 31..0 – KeyReg0[31:0] Key used in E_functions Note: Default Value: 00000000 hex KeyReg1 addr: 6000A4 hex RW 32 bits  Bits 31..0 – KeyReg1[31:0] Key used in E_functions Note: Default Value: 00000000 hex KeyReg2 addr: 6000A8 hex RW 32 bits  Bits 31..0 – KeyReg2[31:0] Key used in E_functions Note: Default Value: 00000000 hex KeyReg3 addr: 6000AC hex RW 32 bits  Bits 31..0 – KeyReg3[31:0] Key used in E_functions Note: Default Value: 00000000 hex KeyReg4 addr: 6000B0 hex RW 32 bits

1612D–08/01 Voice CODEC Register Set The Voice CODEC has four modes: CVSD, A-law, U-law and pass through where data is transferred out through the digital interface. The module has independent receive and transmit paths – each having a dedicated 32-byte FIFO. VC_CTRL: Voice CODEC Analog Control addr: 500000 hex R/W 13 bits  Bits 15..13 – Reserved  Bit 12 – Rate 1= 64 kHz sampling rate 0= 8 kHz sampling rate  Bits 11..10 – ADC_TC[1:0] Type of AD conversion: 00 = Reserved 01 = Reserved 10 = Reserved 11 = Conversion initiated by 64/8 kHz clock  Bit 9 – ADC_SC Start conversion  Bit 8 – ADC_EN: Enables ADC Converter  Bit 7 – DAC_EN: Enables DAC Converter  Bit 6 – DIG_INT: Enables Digital Interface  Bit 5 – AL_DEC: Enables A-law Decoder  Bit 4 – UL_DEC: Enables U-law Decoder  Bit 3 – CV_DEC: Enables CVSD Decoder  Bit 2 – AL_ENC: Enables A-law Encoder  Bit 1 – UL_ENC: Enables U-law Encoder  Bit 0 – CV_ENC: Enables CVSD encoder Note: Default Value: 0000 hex Before conversions can take place the ADC and the DAC must be powered up. The ADC requires 10 µs power-up time while the DAC 20 µs power-up time. During this time, the coding modules must not be enabled. After powering up, the ADC/DAC conversion rate and the required coding mode can be programmed. VCDI_MODE: Voice CODEC Digital Interface Control addr: 500004 hex R/W 16 bits Bits 15..6 – Reserved  Bit 5 – ENA: Enables Serial Transmission 1= Enabled 0= Not enabled  Bit 4 – OSF: Output Sample Format 1 = 16 bits 0 = 8 bits

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1612D–08/01  Bit 3 – DIR: Audio Clock Direction 1= Digital interface is slave 0= Digital interface is master  Bit 2 – BDIV: Divides Audio Clock Divides Audio Clock (depending on mode[4] bit) in order to drive the bit clock. {mode[2], mode[4]} = 00, abclk = aclk/32 {mode[2], mode[4]} = 01, abclk = aclk/16 {mode[2], mode[4]} = 10, abclk = aclk/24 {mode[2], mode[4]} = 11, abclk = aclk/12  Bits 1..0 – M_CDC[1:0]: Master Audio Clock Divider Control 00 = aclk is driven by mclock 01 = aclk = mclock/2 10 = aclk = mclock/4 11 = aclk = mclock/8 Note: Default Value: 0000 hex The digital interface is able to operate either as a master or a slave. When operating as a mas- ter, a 6.144 MHz clock is used, while in slave mode, the clock available at the ABCLK_IN pin is used to drive the digital interface. VC_INT_CTRL_STATUS: Voice CODEC Interrupt Control Status addr: 500008 hex R/W 16 bits  Bits 15..4 – Reserved  Bit 3 – EN_RC_I:Enable Voice CODEC Transmit FIFO Interrupt  Bit 2 – EN_TR_I: Enable Voice CODEC Receive FIFO Interrupt  Bit 1 – VCRC_S: Transmit FIFO Interrupt Status  Bit 0 – VCTR_S: Receive FIFO Interrupt Status Note: Default Value: 0000 hex VC_RxFifoCtrl: Voice CODEC Receive FIFO Control Status Register () addr: 50000C hex R/W 16 bits  Bit 15 – EMPTY  Bit 14 – ALEMPTY 1 byte left to be transmitted.  Bit 13 – FULL  Bit 12 – RESFF: Reset Receive FIFO  Bits 11..10 – Reserved  Bits 8..5 – RCFTR[4:0]: Receive FIFO Threshold  Bits 1..0 – LEVEL[4:0]: Receive FIFO Level Note: Default Value: 0000 hex

1612D–08/01 VC_RxReadPort: Voice CODEC Receive FIFO Read Port addr: 500010 hex R 8 bits  Bits 7..0 – VC_RXD[7:0]: Receive Data Note: Default Value: 00 hex VC_TxFifoCtrl: Voice CODEC Transmit FIFO Control Status Register addr: 500014 hex R/W 16 bits  Bit 15 – EMPTY  Bit 14 – ALEMPTY 1 byte left to be transmitted.  Bit 13 – FULL  Bit 12 – RESFF: Reset Transmit FIFO  Bits 11..10 – Reserved  Bits 9..5 – TXFTR[4:0]: Transmit FIFO threshold  Bits 4..0 – LEVEL[4:0]: Transmit FIFO Level Note: Default Value: 0000 hex VC_TxWritePort: Voice CODEC Transmit FIFO Write Port addr: 500018 hex W 8 bits  Bits 7..0 – VC_RXD[7:0]: Transmit Data Note: Default Value: 00 hex

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The following registers are found in the USB wrapper block and control the overall performance of the USB hardware block. Table 4. Summary of the USB Cell Specific Registers

Table 4. Summary of the USB Cell Specific Registers (Continued)

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1612D–08/01 SLP_MD_EN: Sleep Mode Control addr 5000000h R/W 8 bits  Bits 7..6 – Reserved  Bit 5 – SLP Put the USB module in sleep mode  Bits 4..0 – Reserved Note: Default: 00h GLB_IRQ_MSK: Global Interrupt Master Register addr 5000004h R/W 16 bits  Bits 15..11 – Reserved  Bit 10 – TDMA_IEN:Transmit DMA Interrupt Enable  Bit 9 – RDMA_IEN: Receive DMA Interrupt Enable  Bit 8 – URES_INT When this bit is high, the USB reset interrupts are enabled  Bit 7 – Reserved  Bit 6 – INT_EN When this bit is high, it allows the INTERRUPT line from the USB protocol handler to cause interrupts  Bits 5..2 – Reserved  Bit 1 – SUSP_INT If this bit is high, an interrupt is generated when the USB enters suspend mode.  Bit 0 – RSM_INT If this bit is high, an interrupt is generated when the USB enters resume mode. Note: Default: 00h These registers allow interrupt masking for the following interrupt sources: 1. INTERRUPT line from USB protocol handler. 2. USB reset (USB_RES). A USB reset signal is asserted from USB protocol handler when the USB host requests it by forcing both the differential USB network signals to low level. 3. Suspend: A USB device enters in suspend only when requested by the USB host through bus inactivity for at least 3 ms. 4. Resume: a J to K state change on the USB port signals resume. IRQ_STAT: Master Interrupt Status addr 5000008h R 16 bits  Bits 15..11 – Reserved  Bit 10 – TDMA_TC: Transmit DMA Complete  Bit 9 – RDMA_TC: Receive DMA Complete  Bit 8 – SUS_RES_ST Indicates the current status of the USB block. When this bit is high, the USB is in Suspend mode while, when low, the USB has resumed.  Bit 7 – Reserved

1612D–08/01  Bit 6 – INTER_LINE The INTERRUPT line from the USB protocol handler is asserted.  Bits 5..2 – Reserved  Bit 1 – SUSP When this bit is high, the USB has entered the suspend state.  Bit 0 – RSM When this bit is high, the USB has entered the resume state. Note: Default: 00h RES_STAT: Reset Status addr 500000Ch R/W 8 bits  Bits 7..5 – Reserved  Bit 4 – USB_RES Set when USB module enters reset state.  Bits 3..0 – Reserved Note: Default: 00h DEF_EP_PAIRS: Endpoint Pairs Definition addr 5000010h R/W 8 bits  Bits 7...4 – Reserved  Bit 3 – EP3_EN_PAIR When this bit is high, the EP3 supports an OUT and an IN endpoint. In this case the EP6 is used as the IN endpoint.  Bit 2 – EP2_EN_PAIR When this bit is high, the EP2 supports an OUT and an IN endpoint. In this case the EP5 is used as the IN endpoint.  Bit 1 – EP1_EN_PAIR When this bit is high, the EP1 supports an OUT and an IN endpoint. In this case the EP4 is used as the IN endpoint  Bit 0 – Reserved Note: Default: 00h This 3-bit register defines which endpoints support both IN and OUT connections. Only the endpoints 1 - 3 support endpoint pair addressing. There is a correspondence between end- points 1 to 3 and endpoints 4 to 6, e.g. endpoint 1 pair addressing is enabled, endpoint 4 becomes the pair endpoint. In this case, the endpoint 1 should be configured as an OUT end- point, while endpoint 4 is an IN endpoint. This correspondence is transparent to the USB host which considers that there are two end- points at address 0x01, an OUT. USB_RDMA_LEN: Receive DMA Packet Length Requested addr 500001Ch R/W 16 bits  Bits 15..9 – Reserved  Bits 8..0 – URDL[8:0]: USB Receive DMA Length Note: Default: 00h ARM programs this register with the number of bytes to be transferred during the next DMA.

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supported by the USB block are listed in Table 5. Target address in SRAM for DMA transfers. Table 5. DMA Target Endpoint Addresses

1612D–08/01  Bits 15..9 – Reserved  Bits 8..0 – UTDL[8:0]: USB Transmit DMA Length Note: Default: 00h The ARM programs this register with the number of bytes to be transferred during the next DMA. USB_TDMA_LENR: Transmit DMA Packet Length Transferred addr 5000048h R 8 bits  Bits 7..0 UTDL[7:0]: Transmit DMA Transferred Length Note: Default: 00h After the end of a DMA, the contents of this register reflect the number of bytes that have been transferred from main system memory to the transmit FIFO. USB_TDMA_EN: Transmit DMA Enable addr 500004Ch R/W 8 bits Bits 7..2 – Reserved  Bit 1 – Reserved  Bit 0 – TDMAEN Activates transmit DMA (DMA for an IN endpoint) Note: Default: 00h This bit is reset after the completion of the DMA. FRM_NUM_H: Frame Number High Register addr 50003F4h W 8 bits Bits 7..3 – Reserved  Bits 2..0 – FCH[10:8] This is the upper 3 bits of the 11-bit frame number of SOF packet. Note: Default: 00h FRM_NUM_L: Frame Number Low Register addr 50003F0h W 8 bits Bits 7..3 – Reserved  Bits 2..0 FCL[7:0] This is the lower 8 bits of the 11-bit frame number of SOF packet. Note: Default: 00h GLB_STATE: Global State Register addr 50003ECh 8 bits  Bits 7..4 – Reserved  Bit 3 W – RSMINPR Set by the hardware when a Resume is send in the USB bus during Remote Wake-up feature (13 ms).

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1612D–08/01  Bit 2 R – RMWUPE Remote Wake-up Enable. This bit is set if the Host enables the function ’s remote wake-up feature.  Bit 1 R – CONFG Configured. This bit is set by the firmware after a valid SET_CONFIGURATION request is received. It is cleared by a reset or by a SET_CONFIGURATION with a value of 0.  Bit 0 R – FADD Enable: Function Address Enable This bit is set by firmware after the status phase of a SET_ADRESS request transaction. The Host will use the new address starting at the next transaction. Note: Default: 00h SPRSR: Suspend/Resume Register addr 50003E8h W 8 bits  Bits 7..4 – Reserved  Bit 3 – SOF INT: Start Of Frame Interrupt  Bit 2 – EXT RSM: Received External Resume The USB hardware sets this bit to denote an External Resume Interrupt. If RMWUPE = 1, a RESUME signal is send in USB BUS.  Bit 1 – RCVD RSM: Received Resume The USB hardware sets this bit when a USB resume signaling is detected at its port.  Bit 0 – SUSP: Suspend The USB hardware sets this bit when it detects no SOF for 3 ms. The USB macro enters in SUSPEND MODE, the processor has to go in SLEEP mode. Note: Default: x0h SPRSIE: Suspend/Resume Interrupt Enable Register addr 50003E4h R 8 bits Bits 7..4 – Reserved  Bit 3 – SOF IE: Enable SOF Interrupt  Bit 2 – EXTRSM IE: Enable External Resume Signaling Interrupt 1 = Enable 0 = Disable  Bit 1 – RCVDRSM IE: Enable BUS Resume Signaling Interrupt 1 = Enable 0 = Disable  Bit 0 – SUSP IE: Enable Suspend Signaling Interrupt 1 = Enable 0 = Disable Note: Default: x0h UISR: USB Interrupt Status Register addr 50003DChW8 bits

1612D–08/01  Bit 7 – Reserved  Bit 6 – EP6 INT: Endpoint 6 Interrupt  Bit 5 – EP5 INT: Endpoint 5 Interrupt  Bit 4 – EP4 INT: Endpoint 4 Interrupt  Bit 3 – EP3 INT: Endpoint 3 Interrupt  Bit 2 – EP2 INT: Endpoint 2 Interrupt  Bit 1 – EP1 INT: Endpoint 1 Interrupt  Bit 0 – EP0 INT: Endpoint 0 Interrupt Note: Default: 00h The function interrupt bits will be set by the hardware whenever the following bits in the corre- sponding Endpoint’s Control and Status Register are modified by the USB hardware: 1. RX OUT Packet is set (Control and OUT Endpoint). 2. TX Packet Ready is cleared (Control and IN Endpoint). 3. RX SETUP is set (Control Endpoints only). 4. TX Complete is set (Control Endpoints only). UIAR: USB Interrupt Acknowledge Register addr 50003D4h W 8 bits  Bit 7 – Reserved  Bit 6 – EP6 INTA: Endpoint 6 Interrupt Acknowledge  Bit 5 – EP5 INTA: Endpoint 5 Interrupt Acknowledge  Bit 4 – EP4 INTA: Endpoint 4 Interrupt Acknowledge  Bit 3 – EP3 INTA: Endpoint 3 Interrupt Acknowledge  Bit 2 – EP2 INTA: Endpoint 2 Interrupt Acknowledge  Bit 1 – EP1 INTA Endpoint 1 Interrupt Acknowledge  Bit 0 – EP0 INTA: Endpoint 0 Interrupt Acknowledge Note: Default: 00h The bits in this register are used to indirectly clear the bits of the UISR. A bit in the UISR is cleared if a 1 is written in the corresponding bit of UIAR. UIER: USB Interrupt Enable Register addr 50003CCh R/W 8 bits  Bit 7 – SOFIE: Enable SOF Interrupt  Bit 6 – EP6 IE: Enable Endpoint 6 Interrupt  Bit 5 – EP5 IE: Enable Endpoint 5 Interrupt  Bit 4 – EP4 IE: Enable Endpoint 4 Interrupt  Bit 3 – EP3 IE: Enable Endpoint 3 Interrupt  Bit 2 – EP2 IE: Enable Endpoint 2 Interrupt  Bit 1 – EP1 IE: Enable Endpoint 1 Interrupt  Bit 0 – EP0 IE:Enable Endpoint 0 Interrupt Note: Default: 00h The bits in this register has the following meaning: 1 = Enable interrupt

58 AT76C551

1612D–08/01 0 = Disable interrupt FADDR: Function Address Register addr 50003C8h R 8 bits  Bit 7 – FEN: Function Enable  Bits 6..0 – FADD[6:0]: Function Address Note: Default: 00h The FIU address register contains the function address assigned by the Host. This Function Address Register must be programmed by the processor once it has: 1. Received a SET_ADDRESS command from the Host. 2. Completed the status phase of the transaction. After power up or reset this register will contain the value of 0x00. The Function Enable bit (FEN) allows the firmware to enable or disable the function Endpoints. The firmware will set this bit after receipt of a reset through the USB hardware. Once this bit is set the USB hardware passes packets to and from the Host. ENDPPGPG: Endpoint Ping-pong Enable Register addr 50003C4h R 8 bits Bit 7 – Reserved  Bit 6 – PG_EP6_EN:Enable Endpoint 6 Ping-pong  Bit 5 – PG_EP5_EN: Enable Endpoint 5 Ping-pong  Bit 4 – PG_EP4_EN: Enable Endpoint 4 Ping-pong  Bit 3 – PG_EP3_EN: Enable Endpoint 3 Ping-pong  Bit 2 – PG_EP2_EN: Enable Endpoint 2 Ping-pong  Bit 1 – PG_EP1_EN: Enable Endpoint 1 Ping-pong  Bit 0 – PG_EP0_EN: Enable Endpoint 0 Ping-pong Endpoint Control Registers addr: see below 8 bits Endpoint Control Registers addr: see below 8 bits  Bit 7 R – EPEDS: Endpoint Enable/Disable 0 = Disable Endpoint 1 = Enable Endpoint  Bit 6 – Reserved  Bits 5..4 – Reserved and set to 0  Bit 3 W – DTGLE: Data Toggle Identifies DATA0 or DATA1 packets.  Bit 2 R – EPDIR: Endpoint Direction Only applicable for non-control Endpoints (0 = Out, 1 = In).  Bits 1..0 R – EPTYPE: Endpoint Type These bits represent the type of the Endpoint (see Tables 6, 7, 8 and 9).

Table 6. Endpoint Type

10 B u l k

Table 7. Endpoint Control Registers’ Address

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Table 8. Endpoint Control and Status Register This bit is used by Control Endpoints only. determine the status phase of a control transfer. packet it expects from the Host. currently residing in the FIFO is transmitted. will interrupt the processor without clearing this bit. should be set before Data_End. unconditionally after the data is sent. Control read transactions by a Control Endpoint. is "0”, but bit Data End (bit 4) is "1”. By a BULK IN or ISO IN or INT IN Endpoint. FIFO only while bit 6 (TX Packet Requested) is set. The hardware clears this bit after it receives an ACK. hardware, it causes an interrupt to the processor. responding to a USB GetStatus Request.

firmware should clear this bit. status phase of a control Endpoint. ACK handshake from the Host. Table 8. Endpoint Control and Status Register (Continued) Table 9. Endpoint Control and Status Register’s Address

62 AT76C551

Table 10. UART Register File and Register Fields

700004 US_IER Transmitter

700008 US_FCR RCVR

00 D M A

0 RCVR

700010 US_MR Channel

700014 US_CSR Transmitter

700018 US_CR Rx

700020 US_BM MSB LSB

700024 US_RTO MSB LSB

700028 US_TTG MSB LSB

700030 US_MCC 0 LB RI

1612D–08/01 US_RHR: Receive Holding Register addr: 700000 hex R 8 bits  Bits 7..0 – US_RHR[7:0] Received data Note: Default Value: 00 hex US_THR: Transmit Holding Register addr: 700000 hex W 8 bits  Bits 7..0 – US_THR[7:0] Transmit data Note: Default Value: 00 hex US_IER: Interrupt Enable Register addr: 700004 hex R/W 8 bits  Bit 7 – TXEI: Transmitter Empty Interrupt When set the interrupt is enabled. When both the Transmit Holding Register US_THR and the Transmit Shift Register are empty and the I bit in Status Register SREG of the MCU is set, an interrupt will occur.  Bit 6 – RXTOI: Receive Time-out Interrupt When set, the time-out interrupt is enabled. When the time-out period for the receiver has passed and the I bit in the Status Register SREG of the MCU is set, an interrupt will occur.  Bit 5 – PEI: Parity Error Interrupt This bit when set enables the Parity Error interrupt. If the Parity Error bit of Control Status Reg- ister US_CSR is set, an interrupt will occur.  Bit 4 – FEI: Framing Error Interrupt This bit when set enables the Framing Error interrupt. If the Parity Error bit of Control Status Register US_CSR is set, an interrupt will occur.  Bit 3 – OEI: Overrun Error Interrupt This bit when set enables the Overrun Error interrupt. If the Parity Error bit of Control Status Register US_CSR is set, an interrupt will occur.  Bit 2 – RBRI: Receive Break Interrupt When set enables receive break interrupt. If a receive break condition is detected and both this and the I bit of SREG of the MCU is set, an interrupt will occur.  Bit 1 – THRI: Transmit Register Interrupt When set indicates that the transmit ready interrupt is enabled. When the contents of the Transmit Holding Register are transferred to the Transmit Shift Register and both this and the I bit of SREG of the MCU are set, an interrupt occurs.  Bit 0 – RHRI: Receive Holding Register Interrupt When set, indicates that the Receive Holding Register interrupt is enabled. If the data loaded in the Receive Holding Register (US_RHR) are not read or the trigger level has been reached, an interrupt occurs, if this bit and the I bit of SREG of the MCU are set. Note: Default Value: 00 hex – The Modem Control Interrupts are controlled only from the US_MCC register.

64 AT76C551

 Bit 3 – RDMA: DMA Mode Select. characters are read one byte each time. When set, resets the receive FIFO. When set, enables the 16 byte receive FIFO. The trigger level is shown in Table 11. Table 11. Trigger Level

1612D–08/01 10: No parity 11: Multi drop  Bit 1 – RES: Parity Type In normal parity mode this bit is used for the determination of parity. In force parity mode this bit is forced to be the parity bit.  Bit 0 – LSB: Reserved Note: Default Value: 00 hex US_MR: Mode Register addr: 700010 hex R/W 8 bits  Bits 7..6 – CHM[1:0] Channel Mode 00: Normal 01: Automatic echo 10: Local loop-back 11: Remote loop-back  Bits 5..0 – Reserved Note: Default Value: 00 hex US_CSR: Control Status Register addr: 700014 hex R/W 8 bits  Bit 7 – TXE: Transmitter Empty When set, this indicates that both the Transmit Holding Register US_THR and Transmit Shift Register are empty.  Bit 6 – RXTO: Receive Time-out When set, this indicates that a receive time-out condition has occurred.  Bit 5 – PE: Parity Error When set, this indicates that a parity error has occurred.  Bit 4 – FE: Framing Error When set, this indicates that a framing error has occurred (start or stop bits has been received with errors).  Bit 3 – OE: Overrun Error When set indicates that an overrun error has occurred. This means that the Receive Holding Register is being written with a new value, while the previous one has not been read.  Bit 2 – RBR: Receive Break Receive Break. When set indicates that a break condition has occurred during reception  Bit 1 – THR: Transmit Holding Register Ready When set, this indicates that the contents of the Transmit Holding Register have been trans- ferred to the Transmit Shift Register.

66 AT76C551

1612D–08/01  Bit 0 – RHR: Receive Holding Register Ready When set indicates that the Receive Holding Register is full. In order to clear this bit you must empty the RHR (or the FIFO if it is enabled) by reading the US_RHR register. Note: Default Value: 00 hex US_CR: Control Register addr: 700018 hex R/W 8 bits  Bit 7 – RXEN: Enable When set, this enables the receiver block of UART.  Bit 6 – RLES: Reset Line Error Status bits When set, this resets the PE, FE, OE bits of US_CSR register.  Bit 5 – TXEN: Tx Enable When set, this enables the transmitter block of UART.  Bit 4 – RSTO: Restart Time-out When set, this resets the time-out counter for a new time-out period.  Bit 3 – TXRS: Tx Reset  When set, this resets the transmit logic.  Bit 2 – RXRS: Rx Reset When set, this resets the receive logic.  Bit 1 – SPB: Stop Break Break command to the transmit logic. When set, this stops break condition.  Bit 0 – STB: Start Break Break command to the transmit logic. When set, this starts break condition. Note: Default Value: 00 hex US_BL: Low Byte, Baud Rate Register addr: 70001C hex R/W 8 bits  Bits 7..0 – US_BL[7:0] Baud rate generator division ratio low. The main system clock is divided by the number con- tained in US_BL and US_BM, to provide the USART clock (which is 16 times the actual serial data rate). Note: Default Value: 00 hex US_BM: High Byte, Baud Rate Register addr: 700020 hex R/W 8 bits  Bits 7..0 – US_BM[7:0] Baud rate generator division ratio high. Note: Default Value: 00 hex

interpose between two consecutive character transmissions. Active high. This bit is the compliment of the DSR input pin. Active high. This bit is the compliment of the RI input pin. Table 12. Baud Rate Generation Example (Internal UART Clock = 14,76923 MHz)

68 AT76C551

1612D–08/01  Bit 5 – CD: Carrier Detect Active high. This bit is the compliment of the CD input pin.  Bit 4 – CTS: Clear To Send Active high. This bit is the compliment of the CTS input pin.  Bit 3 – DSR Change Active high Logic 0: No DSR change Logic 1: The DSR input pin has changed state since the last time it was read. An interrupt will be generated.  Bit 2 – RI: Ring Indicator Change Active high Logic 0: No RI change Logic 1: The RI input pin has changed state since the last time it was read. An interrupt will be generated.  Bit 1 – CD: Change Active high Logic 0: No CD change Logic 1: The CD input pin has changed state since the last time it was read. An interrupt will be generated.  Bit 0 – CTS Change Active high Logic 0: No CTS change Logic 1: The CTS input pin has changed state since the last time it was read. An interrupt will be generated. Note: Default Value: 00 hex US_MCO: Modem Control Outputs addr: 70002C hex W 8 bits  Bits 7..5 – Reserved  Bit 1 – RTS Control RTS output pin: Logic 1: Force RTS output pin to a logic Logic 0: Force RTS output pin to a logic 0  Bit 0 – DTR Control DTR output pin: Logic 1: Force DTR output pin to a logic 1 Logic 0: Force DTR output pin to a logic 0 Note: Default Value: 00 hex

1612D–08/01 US_MCC: Modem Control Register addr: 700030 hex R/W 8 bits  Bit 7 – Reserved  Bit 6 – LB RI Value The compliment of the value of RI input, when Modem Control Loop Back mode is enabled.  Bit 5 – LB CD Value The compliment of the value of CD input, when Modem Control Loop Back mode is enabled.  Bit 4 – MC LB EN: Modem Control Loop Back Mode Enable  Bit 3 – DSR Change Mask This bit when set enables the DSR change interrupt. If the DSR change bit of Modem Control Input Register US_MCI is set, then an interrupt will occur.  Bit 2 – RI Change Mask This bit when set enables the RI change interrupt. If the RI change bit of Modem Control Input Register US_MCI is set, then an interrupt will occur.  Bit 1 – CD Change Mask This bit when set enables the CD change interrupt. If the CD change bit of Modem Control Input Register US_MCI is set, then an interrupt will occur.  Bit 0 – CTS Change Mask This bit when set enables the CTS change interrupt. If the CTS change bit of Modem Control Input Register US_MCI is set, then an interrupt will occur. Note: Default Value: 00 hex The low nibble of the Modem-control register is the Modem Control interrupt mask register (see US_MCI). Note: US_IER cannot control the interrupts from modem control logic. The high nibble is used to control the Modem Control Loop-back mode. If MC Loop Back enable bit is set, then the US_MCC bits 5 - 6 control the values of CD and RI inputs (see and US_MCI bits 5 - 6 and 1 - 2). When MC Loop-back mode is enabled, then input pins RI, CD, DSR, CTS are assigned the following values: RI bit 6 of register US_MCC (inverted) CD bit 5 of register US_MCC (inverted) DSR pin DTR CTS pin RTS

70 AT76C551

1612D–08/01 General Purpose Registers Power Down addr: D00000 hex R/W 6 bits  Bit 5 – VCPU: VC Power Up  Bit 4 – UARTPU: UART Power Up  Bit 3 – USBPU: USB Power Up  Bit 2 – BDPRPD: BT Baseband Power Down  Bit 1 – Reserved  Bit 0 – ARMSPD: ARM Speed Note: Default Value: 00 hex Module Reset addr: D00004 hex R/W 5 bits  Bit 4 – PCMCIARES: PCMCIA Core Reset  Bit 3 – USBRES: USB Reset  Bit 2 – VCRES: VC Reset  Bit 1 – UARTRES: UART Reset  Bit 0 – BTRES: BT Baseband Reset Note: Default Value: 00 hex USB Pad Enable addr: D00008 hex R/W 1 bit  Bit 2 – USBPDEN: USB Pad Enable Note: Default Value: 0 DEBUG Port addr: D0000C hex R/W 1 bit  Bit 9 – BTRXDB When enabled, the output of the BT clock recovery circuit is transferred to the Debug pins.  Bit 8 DBEN: Debug TX Enable  Bit 7..0 – DBDATA: Debug Data Interrupt Controller Registers Interrupt Status Register addr: F00000 hex R 8 bits  Bit 7 – VC: Voice Codec Interrupt  Bit 6 – PCMCIA:PCMCIA Interrupt  Bit 5 – UART: UART Interrupt  Bit 4 – USB: USB Interrupt  Bit 3 – BDPR: Baseband DPRAM Interrupt  Bit 2 – BT: Baseband and Timers Interrupt  Bit 1 – TM1: Timer 1 Interrupt  Bit 0 – TM2: Timer 2 Interrupt Note: Default Value: 00 hex

1612D–08/01 Interrupt Mask Register addr: F00004 hex R/W 8 bits  Bit 7 – VC Mask Enables the Voice Codec interrupt  Bit 6 – PCMCIA Mask Enables the PCMCIA interrupt  Bit 5 – UART Mask Enables the UART interrupt  Bit 4 – USB Mask Enables the USB interrupt  Bit 3 – BDPR Mask Enables the Baseband DPRAM interrupt  Bit 2 – BT Mask Enables the Baseband and Timers interrupt  Bit 1 – TM1 Mask Enables the Timer 1 Interrupt  Bit 0 – TM2 Mask Enables the Timer 2 Interrupt Note: Default Value: 00 hex Interrupt Masked Status Register addr: F00008 hex R 8 bits  Bits 7..0 – US_ISM[7:0] Each bit of this register is the boolean and of the corresponding bits of Interrupt Status register and the Interrupt Mask Register. Note: Default Value: 00 hex Interrupt Priority Register addr: F0000C hex R/W 8 bits  Bit 7 – VC_PR Enables FIQ priority for the Voice Codec interrupt line  Bit 6 – PCMCIA_PR Enables FIQ priority for PCMCIA interrupt line  Bit 5 – UART_PR Enables FIQ priority for UART interrupt line  Bit 4 – USB _PR Enables FIQ priority for USB interrupt line  Bit 3 – BDPR_PR Enables FIQ priority for DPRAM interrupt line  Bit 2 – BT_PR Enables FIQ priority for Baseband interrupt line

72 AT76C551

Timer Device 1 and Timer Device 2. AMBA memory space and thus accessible by the ARM core. (See Table 13). Timer Preload Low Register and Timer Preload High Register contain the 32-bit preload value. Timer Device and must be ensured by software means. Table 13. Timer Device Registers

1612D–08/01 Timer Prescale Register R/W 16 bits Timer Prescale Register sets the divisor for the prescale circuit. If Timer Prescale Register contains p and PAI clock frequency is f (MHz) then countdown rate for the Timer Device counter will be r = f/p Note: The Timer Prescale Register must contain a non-zero value for proper Timer Device operation. Timer Control Register R/W 16 bits  Bits 15..2 – Reserved Returns 0 when read  Bit 1 – Enable Logic 1: The counter is allowed to run. Logic 0: The counter is stopped. The Timer Device may be configured via Timer Preload Low Register, Timer Preload High Register and Timer Prescale Register.  Bit 0 – Periodic Logic 1: Periodic mode operation is selected. Logic 0: One-shot mode operation is selected. Timer Interrupt Clear Register W1 6 b i t s Writing Timer Interrupt Clear Register with any value clears an interrupt generated by the Timer Device. AT76C551 firmware is expected to write to Timer Interrupt Clear Register each time a Timer Device interrupt is processed or else, interrupt request to the ARM core will persist.

74 AT76C551

may result in the device failing to meet some of its specification. Table 14. Recommended Operating Conditions Table 15. Absolute Maximum Ratings

The values shown in this table are valid for TA = 0°C to 85°C, VCC = 3.3V unless otherwise noted. Note: 1. XTAL2 must not be used to drive other circuitry. Table 16. Power Supply Table 17. USB Signals: DP, DM Table 18. Oscillator Signals: XTAL1, XTAL2(1)

76 AT76C551

Table 19. DP, DM Driver Characteristics Table 20. DP, DM Data Source Timings

© Atmel Corporation 2001. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company ’s standard warranty which is detailed in Atmel ’s Terms and Conditions located on the Company ’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without n otice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of At mel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel ’s products are not authorized for use as critical components in life support devices or systems. Atmel Headquarters Atmel Product Operations Corporate Headquarters

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TEL (33) 4-4253-6000 FAX (33) 4-4253-6001 Atmel Smart Card ICs Scottish Enterprise Technology Park East Kilbride, Scotland G75 0QR TEL (44) 1355-357-000 FAX (44) 1355-242-743 e-mail literature@atmel.com Web Site http://www.atmel.com BBS 1-(408) 436-4309 Printed on recycled paper. ATMEL® is the registered trademarks of Atmel. Bluetooth ™ is a trademark owned by the Bluetooth SIG, Inc.; ARM7TDMI ®, ARM ®, Thumb ® are the registered trademarks of ARM Limited; AMBA ™ is the trademark of ARM Limited. Other terms and product names may be the trademarks of others. 1612D–08/01/xM