AT75C220

AT75C220 ATMEL | Alldatasheet

Document overview

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Technical content

Features

• ARM7TDMI™ ARM® Thumb™ Processor Core  One 16-bit Fixed-point OakDSPCore®  Dual Ethernet 10/100 Mbps MAC Interface with Voice Priority  Multi-layer AMBA™ Architecture  256 x 32-bit Boot ROM  88K bytes of Integrated Fast RAM  Flexible External Bus Interface with Programmable Chip Selects  Codec Interface  Multi-level Priority, Individually-maskable, Vectored Interrupt Controller  Three 16-bit Timer/Counters  Additional Watchdog Timer  Two USARTs with FIFO and Modem Control Lines  Industry-standard Serial Peripheral Interface (SPI)  Up to 24 General-purpose I/O Pins  On-chip SDRAM Controller for Embedded ARM7TDMI and OakDSPCore  JTAG Debug Interface  Software Development Tools Available for ARM7TDMI and OakDSPCore  Supported by a Wide Range of Ready-to-use Application Software, including Multi-tasking Operating System, Networking and Voice-processing Functions  Available in a 208-lead PQFP Package

Description

The AT75C220, Atmel’s latest device in the family of smart internet appliance proces- sors (SIAP), is a high-performance processor designed for professional internet appliance applications such as the Ethernet IP phone. The AT75C220 is built around an ARM7TDMI microcontroller core running at 40 MIPS with an OakDSPCore co-pro- cessor running at 60 MIPS and a dual Ethernet 10/100 Mbps MAC interface. In a typical standalone IP phone, the DSP handles the voice processing functions (voice compression, acoustic echo cancellation, etc.) while the dual-port Ethernet 10/100 Mbps MAC interface establishes the connection to the Ethernet physical layer (PHY) that links the network and the PC. In such an application, the power of the ARM7TDMI allows it to run a VoIP protocol stack as well as all the system control tasks. Atmel provides the AT75C220 with three levels of software modules:  a special port of the Linux kernel as the proposed operating system  a comprehensive set of tunable DSP algorithms for voice processing, tailored to be run by the DSP subsystem  a broad range of application-level software modules such as H323 telephony or POP-3/SMTP E-mail services Smart Internet Appliance Processor (SIAP™ ) AT75C220 – CPU Peripherals Rev. 1396A–05/01

Figure 1. AT75C220 Pinout in 208-lead PQFP Package

Table 1. AT75C220 Pin Description List

Table 1. AT75C220 Pin Description List (Continued)

Figure 2. AT75C220 Block Diagram

The AT75C220 integrates an embedded ARM7TDMI pro- cessor. External SDRAM and SRAM/Flash interfaces are provided so that processor code and data may be stored off-chip. The AT75C220 architecture consists of two main buses, the Advanced System Bus (ASB) and the Advanced Peripheral Bus (APB). The ASB is designed for maximum performance. It inter- faces the processor with the on-chip DSP subsystem and the external memories and devices by the means of the external bus interface (EBI). The APB is designed for access to on-chip peripherals and is optimized for low power consumption. The AMBA bridge provides an interface between the ASB and APB. The AT75C220 uses a multi-layer AMBA bus:  It integrates two independent AMBA ASB buses. The two buses are connected by a bridge that is not visible to the other devices on the bus.  The primary bus (ARM bus) is the main processor bus to which most peripherals are connected.  The secondary bus (MAC bus) is used exclusively for Ethernet traffic. The ARM7TDMI, USART DMA and ASB-ASB bridge devices are masters on the ARM ASB bus, the MAC DMA and ASB-ASB Bridge are masters on the MAC ASB bus and the Flash/SRAM and SDRAM interfaces are ASB slaves. For more details on bus arbitration, see “Arbitration Using Multi-layer AMBA” on page 31. All the peripherals are accessed by means of the APB bus. An on-chip peripheral data controller (PDC) transfers data between the on-chip USARTs and the memories without processor intervention. Most importantly, the PDC removes the processor input-handling overhead and significantly reduces the number of clocks required for data transfer. It can transfer up to 64K contiguous bytes without reprogram- ming the starting address. As a result, the performance of the microcontroller is increased and power consumption reduced. The AT75C220 peripherals are designed to be pro- grammed with a minimum number of instructions. Each peripheral has 16K bytes of address space allocated in the upper part of the address space. The peripheral register set is composed of control, mode, data, status and interrupt registers. To maximize the efficiency of bit manipulation, frequently- written registers are mapped into three memory locations. The first address is used to set the individual register bits, the second resets the bit and the third address reads the value stored in the register. A bit can be set or reset by writ- ing a one to the corresponding position at the appropriate address. Writing a zero has no effect. Individual bits can thus be modified without having to use costly read-modify- write and complex bit-manipulation instructions and without having to store-disable-restore the interrupt state. All of the external signals of the on-chip peripherals are under the control of the parallel I/O controllers. The PIO controllers can be programmed to insert an input filter on each pin or generate an interrupt on a signal change. After reset, the user must carefully program the PIO controllers in order to define which peripherals are connected with off- chip logic. The ARM7TDMI processor operates in little-endian mode in the AT75C220. The processor's internal architecture and the ARM and Thumb instruction sets are described in the ARM7TDMI datasheet, literature number 0673. The mem- ory map and the on-chip peripherals are described in this datasheet. Peripheral Data Controller The AT75C220 has a four-channel peripheral data control- ler (PDC) dedicated to the two on-chip USARTs. One PDC channel is connected to the receiving channel and one to the transmitting channel of each USART. The user interface of a PDC channel is integrated in the memory space of each USART channel. It contains a 32-bit address pointer register and a 16-bit count register. When the programmed number of bytes is transferred, an end-of- transfer interrupt is generated by the corresponding USART. For more details on PDC operation and program- ming, see the section describing the USART on page 74 .

The memory map is divided into regions of 256 megabytes. controller and SDRAM memory controller. See Table 2. The memory map is divided between the two ASB buses. and 0xFBFF_FFFF are routed to the MAC ASB bus.

1. Note that the internal memory regions have fixed loca-

tions that cannot be reprogrammed. have the same base address results in undefined behavior. programming SMC_CS0 or DMC_MR0. Table 2. AT75C220 Memory Map

map has 16K bytes reserved for each peripheral. must be held at valid logic levels.

1. Hardware reset. Caused by asserting the RESET
2. Watchdog timer reset. The WD timer can be pro-
3. Software reset. There are two software resets which

are only released from reset by the ARM program control. specific reset sequence should be followed. Table 3. AT75C220 Peripheral Memory Map

The AT75C220 mode register controls clock generation. duce the ARM clock and Oak clock. The ARM subsystem runs at 40 MHz. The Oak subsystem runs at 60MHz. The USARTs and timers operate from divided ARM clocks. Figure 5. AT75C220 Clocking Flash download sequence from the USART. normally, i.e., from external memory at 0x00000000. Table 4. Clock Source and Frequency

16 MHz

40 MHz

240 MHz

60 MHz

of the SIAP-E mode controller. eral that sits on the APB bus. Note: 1. If the PKG flag is set, the reset value is 0x00010220 since the AT75C220 is bonded in large bond-out mode. abled and another memory controller region (e.g. FLASH) is mapped to location 0x00000000. Table 5. AT75C220 Register Map

 SA: Slow ARM Mode On reset this field is low. In normal operating mode, if bit SA is set. The ARM clock is 34Mhz (i.e. the PLL value is divided by 7). IF SA is not set the ARM clock is 40MHz (i..e the PLL divisor is 6). SA can be switched during low power mode but should not be changed when LP is low.  LPCS: Low Power Clock Select This field is used to select a slower clock frequency for the ARM system clock as per the table below.  SW1: Software Reset 1 Writing a 1 to this bit forces the SIAP into reset with RM set to 0.  SW2: Software Reset 2 Writing a 1 to this bit forces the SIAP into reset with RM set to 1.  DBA: OAKA Debug Mode This flag resets low. To enter OAKA debug mode (specific pins are multiplexed out on functional pins), this bit should be set.  CRA: CODECA Reset This flag resets to active low so that the CODECA is held in reset. The CODECA is released from reset by asserting this flag high.  IPOLTST: PLL Bias Adjustment This can be used to tune the PLL if the bias current is not correct after manufacture.  ICP: PLL Charge Pump Current This can be used to tune the PLL if it does not function with the default current of 2.5 µA.  INDIV Input frequency range of PLL. LPCS Oscillator Clock Divisor ARM and Oak System Clock 00 1 8 M H z 0 1 16 1 MHz 1 0 64 250 kHz 1 1 512 32 kHz Bias Factor 15 IPOLTST–() 4⁄= II C P( 1 )+ 2.5µA×= INDIV PLL Input Frequency Range 0 0 5 kHz to 40 MHz 0 1 40 MHz to 80 MHz 1 0 80 MHz to 160 MHz 1 1 160 MHz to 250 MHz

 OUTDIV Output frequency range of PLL.  JCIDBG This field controls the mode of the JCI. The Oak subsystem has its own JTAG port. This port is used to communicate serially with the Oak OCEM module. SIAP-E ID Register Register Name: SIAP_ID Access: Read-only Reset Value: 0x00000220 in small bond-out mode 0x0001220 in large bond-out mode  IDENT: Identifier This field indicates the device identifier 0x0220.  PKG: Package This bit reflects the state of the data bus width signal DBW and indicates the SIAP package size. OUTDIV PLL Output Frequency Range 0 0 40 MHz to 250 MHz 0 1 20 MHz to 40 MHz 1 0 10 MHz to 20 MHz 1 1 5 MHz to 10 MHz 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 IDENT 76543210 IDENT

SIAP-E Reset Status Register Register Name: SIAP_RST Access: Read/write Reset Value: 0x00000001  RST[2:0]: Reset These bits indicate the cause of the last reset. SIAP-E Clock Status Register Register Name: SIAP_CLKF Access: Read-only Reset Value: 0x00000001  CLK: Clock Status This bit indicates which clock is in use by the system. When set, the low power clock is in use. When cleared, the PLL is locked and the high power clock is in use. This can be used by software to determine when the power mode has changed after the LP bit has been written. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 RST Reset Event 0 0 1 Hardware 0 1 0 Watchdog Timer

100 S o f t w a r e

AT75C220 to access external static memory devices. valid access to the memory device within the page. the exception handling routine used in case of an abort. the internal ROM is mapped to address zero.

1. Byte-write mode supports four (32-bit bus) or two

(16-bit bus) byte writes and a single read signal.

1. Byte-select mode selects the appropriate byte(s)

lines and separate read and write signals. the corresponding chip select. Table 6. Signal Interface

For a 32-bit bus:  The signal NWE0 is used as the write enable signal for byte 0.  The signal NWE1 is used as the write enable signal for byte 1.  The signal NWE2 is used as the write enable signal for byte 2.  The signal NWE3 is used as the write enable signal for byte 3.  The signal NSOE enables memory reads to all memory blocks. For a 16-bit bus:  The signal NWE0 is used as the write enable signal for byte 0.  The signal NWE1 is used as the write enable signal for byte 1.  The signal NSOE enables memory reads to all memory blocks. Byte-select mode can be used to connect one 32-bit device or two 16-bit devices in a 32-bit memory page or one 16-bit device in a 16-bit memory page. For a 32-bit bus:  The signal NWE0 is used to select byte 0 for read and write operations.  The signal NWE1 is used to select byte 1 for read and write operations.  The signal NWE2 is used to select byte 2 for read and write operations.  The signal NWE3 is used to select byte 3 for read and write operations.  The signal NWR is used as the write enable signal for the memory block.  The signal NSOE enables memory reads to the memory block. For a 16-bit bus:  The signal NWE0 is used to select byte 0 for read and write operations.  The signal NWE1 is used to select byte 1 for read and write operations.  The signal NWR is used as the write enable signal for the memory block.  The signal NSOE enables memory reads to the memory block. During boot, the number of external devices (number of active chip selects) and their configurations must be pro- grammed as required. The chip select addresses that are programmed take effect immediately. Wait states also take effect immediately when they are programmed to optimize boot program execution. Read Protocols The SMC provides two alternative protocols for external memory read access: standard and early read. The differ- ence between the two protocols lies in the timing of the NSOE (read cycle) waveform. The protocol is selected by the DRP field in the Memory Control Register (SMC_MCR) and is valid for all memory devices. Standard read protocol is the default protocol after reset.  Standard Read Protocol Standard read protocol implements a read cycle in which NSOE and the write strobes are similar. Both are active during the second half of the clock cycle. The first half of the clock cycle allows time to ensure completion of the pre- vious access, as well as the output of address and NCE before the read cycle begins. During a standard read protocol external memory access, NCE is set low and ADDR is valid at the beginning of the access, whereas NSOE goes low only in the second half of the master clock cycle to avoid bus conflict. The write strobes are the same in both protocols. The write strobes always go low in the second half of the master clock cycle.  Early Read Protocol Early read protocol provides more time for a read access from the memory by asserting NSOE at the beginning of the clock cycle. In the case of successive read cycles in the same memory, NSOE remains active continuously. Since a read cycle normally limits the speed of operation of the external memory system, early read protocol allows a faster clock frequency to be used. However, an extra wait state is required in some cases to avoid contention on the external bus. In early read protocol, an early read wait state is automati- cally inserted when an external write cycle is followed by a read cycle to allow time for the write cycle to end before the subsequent read cycle begins. This wait state is generated in addition to any other programmed wait states (i.e., data float wait). No wait state is added when a read cycle is fol- lowed by a write cycle, between consecutive accesses of the same type or between external and internal memory accesses. Early read wait states affect the external bus only. They do not affect internal bus timing. Write Protocol During a write cycle, the data becomes valid after the fall- ing edge of the write strobe signal and remains valid after the rising edge of the write strobe. The external write strobe waveform on the appropriate write strobe pin is used to control the output data timing to guarantee this operation. Thus, it is necessary to avoid excessive loading of the write strobe pins, which could delay the write signal too long and cause a contention with a subsequent read cycle in stan- dard protocol. In early read protocol, the data can remain

tional wait cycle that follows a write access. wait states during an access on the corresponding device. wait state programmed, an additional cycle is added. access or a read access to a different external memory. troller by setting the LCD bit in the SMC_CSR3 register. SMC as NCE3 is raised at the end of the access. Table 7. Correspondence Wait States/Number of Cycles

Table 8. The memory control register (SMC_MCR) is used SMC_CSR0 is configured as having a 16-bit data bus. Table 8. SMC Register Map

00 R e s e r v e d

11 R e s e r v e d

This field is valid only if WSE is set. Table 9. NWS, WSE Values

11 R e s e r v e d –

 CSEN: Chip Select Enable Active high.  LCD: LCD Mode Enable Active high. SMC_CSR3 only.  BA: Base Address This field contains the high-order bits of the base address. If the page size is larger than 1M byte, then the unused bits of the base address are ignored by the SMC decoder. SMC Memory Control Register Register Name:SMC_MCR  DRP: Data Read Protocol 0 = Standard Read Mode 1 = Early Read Mode 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210

The AT75C220 integrates an SDRAM controller (SDMC). static memory controller but has separate control signals. The SDMC interface is a memory-mapped APB slave. SDRAM should be refreshed frequently. functions similar to those of a conventional DRAM. not bonded out since it is always active high. The SDMC interface is a memory-mapped APB slave. ory region in the ASB memory map. the resultant read data is ignored. Table 10. External Memory Interface

Figure 10. Read Showing a Single Access for a Non-sequential Read to a New Row

1. The following access is a read.
2. The following access is to a new row.
3. The following access is non-sequential.

not a requirement to maintain data in the SDRAM. Table 11. SDRAM Refresh Rates

Table 12. SDMC Register Map 000 Normal mode. Any access to the SDRAM will be decoded normally.

010 The all banks precharge command is issued to the SDRAM when the host accesses the SDRAM memory area,

011 The load mode register command is issued to the SDRAM when the host accesses the SDRAM memory area,

mode register command with the value offset written to the mode register of the SDRAM. 100 A refresh command is issued to the SDRAM. An all banks precharge command must precede.

SDRAM_TIMER Register Register Name: SDRAM_TIMER Access Type: Read/write Reset Value: 0x0  CNT This 12-bit field is loaded into a timer which generates the refresh pulse. Each time the refresh pulse is generated, a refresh burst is initiated. The length of this refresh burst (number of rows refreshed) can be adjusted at compile time by modifying the value RFSH_LEN. The refresh commands will begin when the timer is loaded for the first time. The value to be loaded depends on the clock frequency used in the SDMC configuration module, the refresh rate of the SDRAM and the refresh burst length where 15.6 microseconds is a typical value for a burst of length one. SDRAM_CFG Register Register Name: SDRAM_CFG Access Type: Read/write Reset Value: 0x0  NC Sets the number of column bits. Default is eight column bits. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 –––– CNT 76543210 CNT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TRCD TRP 15 14 13 12 11 10 9 8 TRP TRC TWR 76543210 TWR CAS NB NR NC NC Column Bits 00 8 01 9 10 10 11 11

 NR Sets the number of row bits. Default is 11 row bits.  NB Sets the number of banks. Default is two banks.  CAS Sets the CAS latency. The SDMC has been modified so that it only supports a CAS latency of two. Writing to this reg- ister will have no effect.  TWR Sets the value of TWR expressed in number of cycles. Default is two cycles.  TRC Sets the value of TRC expressed in number of cycles. Default is eight cycles.  TRP Sets the value of TRP expressed in number of cycles. Default is three cycles.  TRCD Sets the value of TRCD expressed in number of cycles. Default is three cycles.  TRAS Sets the value of TRAS expressed in number of cycles. Default is five cycles. SDRAM_16bit Register Register Name: SDRAM_16BIT Access Type: Read/write Reset Value: 0x1  16BIT This bit is used to set the width of the external memory. If this field is set, the address is assumed to be 16 bits wide. If not set, the memory bus is assumed to be 32 bits wide. NR Row Bits 00 11 01 12 10 13

11 Reserved

SDRAM_CS0_ADDR Register Register Name: SDRAM_CS0_ADDR Access Type: Read/write Reset Value: 0x40  CS0_ADDR This bit is used to set the eight most significant bits of the address of CS0. SDRAM_CS1_ADDR Register Register Name: SDRAM_CS1_ADDR Access Type: Read/write Reset Value: 0x50  CS1_ADDR This bit is used to set the eight most significant bits of the address of CS1. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 CS0_ADDR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 CS1_ADDR

The MAC bus is used exclusively for Ethernet traffic. the connection between the two buses. Figure 11. ASB - ASB Bridge request from another master. drop frames due to FIFO overflow or underflow. already have access to the bus. corresponding to a slave on the remote bus. requests the remote bus from the remote bus arbiter. buses are coupled and the transfer completes.

Figure 12. ASB-to-ASB Bridge Write Timing

be single accesses or bursts of two, three or four words. Burst accesses do not cross 16-byte boundaries. DMA read and receive data DMA write. memory locations and need not be word-aligned. words have been loaded into the FIFO. Table 13. External Interface from memory during frame transmission.

another buffer can be safely queued. An interrupt is gener- ated whenever this bit is set. Frame assembly starts by adding preamble and the start frame delimiter. Data is taken from the transmit FIFO word- by-word. If necessary, padding is added to make the frame length 60 bytes. The CRC is calculated as a 32-bit polyno- mial. This is inverted and appended to the end of the frame, making the frame length a minimum of 64 bytes. The CRC is not appended if the NCRC bit is set in the transmit con- trol register. In full duplex mode frames are transmitted immediately. Back-to-back frames are transmitted at least 96 bit times apart to guarantee the interframe gap. In half-duplex mode the transmitter checks carrier sense. If asserted, it waits for it to de-assert and then starts trans- mission after the interframe gap of 96 bit times. If the collision signal is asserted during transmission, the transmitter will transmit a jam sequence of 32 bits taken from the data register and then retry transmission after the backoff time has elapsed. An error is indicated and any fur- ther attempts aborted if 16 attempts cause collisions. If transmit DMA underruns, bad CRC is automatically appended using the same mechanism as jam insertion. Underrun also causes TXER to be asserted. Receiver Mode When a packet is received, it is checked for valid preamble, CRC, alignment, length and address. If all these criteria are met, the packet is stored successfully in a receive buffer. If at the end of reception the CRC is bad, then the received buffer is recovered. Each received frame including CRC is written to a single receive buffer. Receive buffers are word-aligned and are capable of con- taining 1518 bytes of data (the maximum length of an Ethernet frame). The start location for each received frame is stored in memory in a list of receive buffer descriptors at a location pointed to by the receive buffer queue pointer register. Each entry in the list consists of two words. The first word is the address of the received buffer; the second is the receive status. Table 14 defines an entry in the received buffer descriptor list. To receive frames, the buffer queue must be initialized by writing an appropriate address to bits [31:2] in the first word of each list entry. Bit zero must be written with zero. After a frame is received, bit zero becomes set and the second word indicates what caused the frame to be copied to memory. The start location of the received buffer descriptor list should be written to the received buffer queue pointer reg- ister before receive is enabled (by setting the receive enable bit in the network control register). As soon as the received block starts writing received frame data to the receive FIFO, the received buffer manager reads the first receive buffer location pointed to by the received buffer queue pointer register. If the filter block is active, the frame should be copied to memory; the receive data DMA opera- tion starts writing data into the receive buffer. If an error occurs, the buffer is recovered. If the frame is received without error, the queue entry is updated. The buffer pointer is rewritten to memory with its low-order bit set to indicate successful frame reception and a used buffer. The next word is written with the length of the frame and how the destination address was recognized. The next receive buffer location is then read from the fol- lowing word or, if the current buffer pointer had its wrap bit set, the beginning of the table. The maximum number of buffer pointers before a wrap bit is seen is 1024. If a wrap bit is not seen by then, a wrap bit is assumed in that entry. The received buffer queue pointer register must be written with zero in its lower-order bit positions to enable the wrap function to work correctly. If bit zero is set when the receive buffer manager reads the location of the receive buffer, then the buffer has already been used and cannot be used again until software has processed the frame and cleared bit zero. In this case, the DMA block will set the buffer ’s unavailable bit in the received status register and trigger an interrupt. The frame will be discarded and the queue entry will be reread on reception of the next frame to see if the buffer is now avail- able. Each discarded frame increments a statistics register that is cleared on being read. When there is network congestion, it is possible for the MAC to be programmed to apply backpressure. This is when half-duplex mode collisions are forced on all received frames by transmitting 64 bits of data (a default pattern). Reading the received buffer queue register returns the location of the queue entry currently being accessed. The queue wraps around to the start after either 1024 entries (i.e., 2048 words) or when the wrap bit is found to be set in bit 1 of the first word of an entry.

frame’s source address is not checked. Ethernet frames are transmitted a byte at a time, LSB first. to bit 24 of the first word of the specific address register. sponds to bit 31 of the specific address register. Table 14. Received Buffer Descriptor List pointer to entries in this table will be cleared after the buffer is used.

31 Global all ones broadcast address detected

30 Multicast hash match

29 Unicast hash match

28 External address (optional)

27 Unknown source address (reserved for future use)

26 Local address match (Specific address 4 match)

25 Local address match (Specific address 3 match)

24 Local address match (Specific address 2 match)

23 Local address match (Specific address 1 match)

22:11 Reserved written to 0.

received by setting all bits in the hash register. DMA block as soon as any destination address is received. Table 15. Ethernet MAC Register Map

Receive enable. When set, enables the Ethernet MAC to receive data. Transmit enable. When set, enables the Ethernet transmitter to send data. Table 15. Ethernet MAC Register Map (Continued)

 MPE Management port enable. Set to one to enable the management port. When zero forces MDIO to high impedance state.  CSR Clear statistics registers. This bit is write-only. Writing a one clears the statistics registers.  ISR Increment statistics registers. This bit is write-only. Writing a one increments all the statistics registers by one for test purposes.  WES Write enable for statistics registers. Setting this bit to one makes the statistics registers writable for functional test purposes.  BP Back pressure. If this field is set, then in half-duplex mode collisions are forced on all received frames by transmitting 64 bits of data (default pattern). MAC Network Configuration Register Register Name: ETH_CFG Access Type: Read/write Reset Value: 0x8  SPD Speed. Set to 1 to indicate 100Mbit/sec. operation, 0 for 10Mbit/sec. Has no other functional effect.  FD Full duplex. If set to 1, the transmit block ignores the state of collision and carrier sense and allows receive while transmitting.  BR Bit rate. Optional.  CAF Copy all frames. When set to 1, all valid frames will be received.  NBC No broadcast. When set to 1, frames addressed to the broadcast address of all ones will not be received.  MTI Multicast hash enable, when set multicast frames will be received when six bits of the CRC of the destination address point to a bit that is set in the hash register.  UNI Unicast hash enable. When set, unicast frames will be received when six bits of the CRC of the destination address point to a bit that is set in the hash register. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 ––– RTY CLK EAE BIG 76543210 UNI MTI NBC CAF – BR FD SPD

 BIG Receive 1522 bytes. When set, the MAC will receive up to 1522 bytes. Normally the MAC will receive frames up to 1518 bytes in length.  EAE External address match enable. Optional.  CLK The system clock (HCLK) is divided down to generate MDC (the clock for the MDIO). For conformance with IEEE 802.3 MDC must not exceed 2.5 MHz. At reset this field is set to 10 so that HCLK is divided by 32.  RTY Retry test. When set, the time between frames will always be one time slot. For test purposes only. Must be cleared for normal operation. MAC Network Status Register Register Name: ETH_SR Access Type: Read-only Reset Value: 0x4  LINK The status of the LINK pin. Optional.  MDIO Returns status of the MDIO pin.  IDLE The PHY management logic is idle (i.e., has completed). CLK MDC

00 HCLK divided by 8

01 HCLK divided by 16

10 HCLK divided by 32

11 HCLK divided by 6431 30 29 28 27 26 25 24

MAC Transmit Address Register Register Name: ETH_TAR Access Type: Read/write Reset Value: 0x0  ADDRESS Transmit address register. Written with the address of the frame to be transmitted, read as the base address of the buffer being accessed by the transmit FIFO. Note if the two least significant bits are not zero, transmit will start at the byte indicated. MAC Transmit Control Register Register Name: ETH_TCR Access Type: Read/write Reset Value: 0x0  LEN Transmit frame length. This register is written to the number of bytes to be transmitted excluding the four CRC bytes unless the no CRC bit is asserted. Writing these bits to any non-zero value will initiate transmit. If the value is greater than 1514 (1518 if no CRC is being generated), an oversize frame will be transmitted. This field is buffered so that a new frame can be queued while the previous frame is still being transmitted. Must always be written in address-then- length order. Reads as the total number of bytes to be transmitted (i.e., this value does not change as the frame is transmitted.) Frame transmission will not start until two 32-bit words have been loaded into the transmit FIFO. The length must be great enough to ensure two words are loaded.  NCRC No CRC. If this bit is set, it is assumed that the CRC is included in the length being written in the low-order bits and the MAC will not append CRC to the transmitted frame. If the buffer is not at least 64 bytes long, a short frame will be sent. This field is buffered so that a new frame can be queued while the previous frame is still being transmitted. Reads as the value of the frame currently being transmitted. 31 30 29 28 27 26 25 24 ADDRESS 23 22 21 20 19 18 17 16 ADDRESS 15 14 13 12 11 10 9 8 ADDRESS 76543210 ADDRESS 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 NCRC –––– LEN 76543210 LEN

MAC Transmit Status Register Register Name: ETH_TSR Access Type: Read/write Reset Value: 0x18  OVR Ethernet transmit buffer overrun. Software wrote to the address register or length register when bit 4 was not set. Cleared by writing a one to this bit.  COL Collision occurred. Set by the assertion of collision. Cleared by writing a one to this bit.  RLE Retry limit exceeded. Cleared by writing a one to this bit.  IDLE Transmitter Idle. Asserted when the transmitter has no frame to transmit. Will be cleared when a length is written to transmit frame length portion of the Transmit Control register. This bit is read-only.  BNQ Ethernet transmit buffer not queued. Software may write a new buffer address and length to the transmit DMA control- ler. Cleared by having one frame ready to transmit and another in the process of being transmitted. This bit is read- only.  COMP Transmit complete. Set when a frame has been transmitted. Cleared by writing a one to this bit.  UND Transmit underrun. Set when transmit DMA was not able to read data from memory in time. If this happens, the trans- mitter will force bad CRC. Cleared by writing a one to this bit. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 – UND COMP BNQ IDLE RLE COL OVR

MAC Receive Buffer Queue Pointer Register Name: ETH_RBQP Access Type: Read/write Reset Value: 0x0  ADDRESS Receive buffer queue pointer. Written with the address of the start of the receive queue, reads as a pointer to the cur- rent buffer being used. The receive buffer is forced to word alignment. MAC Receive Status Register Register Name: ETH_RSR Access Type: Read/write Reset Value: 0x0  BNA Buffer not available. An attempt was made to get a new buffer and the pointer indicated that it was owned by the pro- cessor. The DMA will reread the pointer each time a new frame starts until a valid pointer is found. This bit will be set at each attempt that fails even if it has not had a successful pointer read since it has been cleared. Cleared by writing a one to this bit.  REC Frame received. One or more frames have been received and placed in memory. Cleared by writing a one to this bit.  OVR RX overrun. The DMA block was unable to store the receive frame to memory, either because the ASB bus was not granted in time or because a not OK HRESP was returned. The buffer will be recovered if this happens. Cleared by writing a one to this bit. 31 30 29 28 27 26 25 24 ADDRESS 23 22 21 20 19 18 17 16 ADDRESS 15 14 13 12 11 10 9 8 ADDRESS 76543210 ADDRESS 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210

MAC Interrupt Status Register Register Name: ETH_ISR Access Type: Read/write Reset Value: 0x0  DONE Management done. The PHY maintenance register has completed its operation. Cleared on read.  RCOM Receive complete. A frame has been stored in memory. Cleared on read.  RBNA Receive buffer not available. Cleared on read.  TOVR Transmit buffer overrun. Software wrote to the address register or length register when bit 4 of the transmit status reg- ister was not set. Cleared on read.  TUND Transmit error. Ethernet transmit buffer underrun. The transmit DMA did not complete fetch frame data in time for it to be transmitted. Cleared on read.  TRLE Transmit error. Retry limit exceeded. Cleared on read.  TBRE Transmit buffer register empty. Software may write a new buffer address and length to the transmit DMA controller. Cleared by having one frame ready to transmit and another in the process of being transmitted. Cleared on read.  TCOM Transmit complete. Set when a frame has been transmitted. Cleared on read.  LINK Set when LINK pin changes value. Optional.  TIDLE Transmit idle. Set when all frames have been transmitted. Cleared on read.  ROVR RX overrun. Set when the RX overrun status bit is set. Cleared on read.  HRESP HRESP not OK. Set when the DMA block sees HRESP not OK. Cleared on read. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 –––– HRESP ROVR LINK TIDLE 76543210 TCOM TBRE RTRY TUND TOVR RBNA RCOM DONE

MAC Interrupt Enable Register Register Name: ETH_IER Access Type: Write-only Reset Value: –  DONE Enable management done interrupt.  RCOM Enable receive complete interrupt.  RBNA Enable receive buffer not available interrupt.  TOVR Enable Ethernet transmit buffer overrun interrupt  TUND Enable transmit buffer underrun interrupt  RTRY Enable retry limit exceeded interrupt.  TBRE Enable transmit buffer register empty interrupt.  TCOM Enable transmit complete interrupt.  LINK Enable LINK interrupt. Optional.  TIDLE Enable transmit idle interrupt.  ROVR Enable RX overrun interrupt.  HRESP Enable HRESP not OK interrupt. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 –––– HRESP ROVR LINK TIDLE 76543210 TCOM TBRE RTRY TUND TOVR RBNA RCOM DONE

MAC Interrupt Disable Register Register Name: ETH_IDR Access Type: Write-only Reset Value: –  DONE Disable management done interrupt.  RCOM Disable receive complete interrupt.  RBNA Disable receive buffer not available interrupt.  TOVR Disable Ethernet Transmit buffer overrun interrupt.  TUND Disable transmit buffer underrun interrupt.  RTRY Disable retry limit exceeded interrupt.  TBRE Disable transmit buffer register empty interrupt.  TCOM Disable transmit complete interrupt.  LINK Disable LINK interrupt. Optional.  TIDLE Disable transmit idle interrupt.  ROVR Disable Rx overrun interrupt.  HRESP Disable HRESP not OK interrupt. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 –––– HRESP ROVR LINK TIDLE 76543210 TCOM TBRE RTRY TUND TOVR RBNA RCOM DONE

MAC Interrupt Mask Register Register Name: ETH_IMR Access Type: Read-only Reset Value: 0xFFFF  DONE Management done interrupt masked.  RCOM Receive complete interrupt masked.  RBNA Receive buffer not available interrupt masked.  TOVR Ethernet Transmit buffer overrun interrupt masked  TUND Transmit buffer underrun interrupt masked  RTRY Retry limit exceeded interrupt masked.  TBRE Transmit buffer register empty interrupt masked.  TCOM Transmit complete interrupt masked.  LINK LINK interrupt masked.  TIDLE Transmit idle interrupt masked.  ROVR Receive overrun interrupt masked.  HRESP HRESP not OK interrupt masked. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 –––– HRESP ROVR LINK TIDLE 76543210 TCOM TBRE RTRY TUND TOVR RBNA RCOM DONE

MAC PHY Maintenance Register Register Name: ETH_MAN Access Type: Read/write Reset Value: 0x0 Writing to this register starts the shift register that controls the serial connection to the PHY. On each shift cycle the MDIO pin becomes equal to the MSB of the shift register and LSB of the shift register becomes equal to the value of the MDIO pin. When the shifting is complete an interrupt is generated and the IDLE field is set in the Network Status register. When read will give current shifted value.  DATA For a write operation this is written with the data to be written to the PHY. After a read operation this contains the data read from the PHY.  CODE Must be written to 10. Will read as written.  REGA Register address. Specifies the register in the PHY to access.  PHYA PHY address. Normally will be 0.  RW Read/write Operation. 10 is read. 01 is write. Any other value is an invalid PHY management frame.  HIGH Must be written with 1 to make a valid PHY management frame.  LOW Must be written with 0 to make a valid PHY management frame. 31 30 29 28 27 26 25 24 LOW HIGH RW PHYA 23 22 21 20 19 18 17 16 PHYA REGA CODE 15 14 13 12 11 10 9 8 DATA 76543210 DATA

Register Name: ETH_HSH Access Type: Read/write Reset Value: 0x0  ADDR Hash Address bits 63 to 32. MAC Hash Address Low Register Name: ETH_HSL Access Type: Read/write Reset Value: 0x0  ADDR Hash Address bits 31 to 0. 31 30 29 28 27 26 25 24 ADDR 23 22 21 20 19 18 17 16 ADDR 15 14 13 12 11 10 9 8 ADDR 76543210 ADDR 31 30 29 28 27 26 25 24 ADDR 23 22 21 20 19 18 17 16 ADDR 15 14 13 12 11 10 9 8 ADDR 76543210 ADDR

MAC Specific Address (1, 2, 3 and 4) High Register Name: ETH_SA1H,...ETH_SA4H Access Type: Read/write Reset Value: 0x0  ADDR Unicast Addresses (1, 2, 3 and 4), Bits 47:32. MAC Specific Address (1, 2, 3 and 4) Low Register Name: ETH_SA1L,...ETH_SA4L Access Type: Read/write Reset Value: 0x0  ADDR Unicast Addresses (1, 2, 3 and 4), Bits 31:0. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 ADDR 76543210 ADDR 31 30 29 28 27 26 25 24 ADDR 23 22 21 20 19 18 17 16 ADDR 15 14 13 12 11 10 9 8 ADDR 76543210 ADDR

read frequently enough to prevent loss of data. Table 16. Statistics Register Block ETH_FRA Frames transmitted OK. A 24-bit register counting the number of frames successfully transmitted. before being transmitted and experiencing no carrier loss nor underrun. fifteen collisions prior to being transmitted (62 - 1518 bytes, no carrier loss, no underrun). recognized. A good frame is of length 64 to 1518 bytes and has no FCS, alignment or code errors. number of bytes long and that have bad CRC and 64 to 1518 bytes long.

• between 64 and 1518 bytes in length.

carrier sense active on their first attempt at transmission (no underrun or collision). collision and a late collision. underrun. If this register is incremented, then no other register is incremented. asserted during reception. If this counter is incremented, then no other counters are incremented. in length but that do not have either a CRC error, an alignment error or a code error. and having either a CRC error, an alignment error or a code error. but that do not have either a CRC error, an alignment error or a code error. slot time of TXEN being deasserted. frame is received but cannot be copied to memory because the receive buffer is available.

datasheet, literature number 1246. external interrupt request lines, IRQ0 to IRQ1. or negative-edge triggered or high- or low-level sensitive. Figure 13. Advanced Interrupt Controller Block Diagram Table 17. Interrupt Sources

0 FIQ Fast Interrupt (LOWP)

1 WDT Watchdog Interrupt

2 SWI Software Interrupt

3 UARTA USART A Interrupt

4 TC0 Timer Channel 0 Interrupt

5 TC1 Timer Channel 1 Interrupt

6 TC2 Timer Channel 2 Interrupt

7 PIOA PIO A Interrupt

8 MACA MAC A Interrupt

9 SPI Serial Peripheral Interface

10 IRQ0 External Interrupt

11 IRQ1 External Interrupt

12 OAKA OAK Semaphore Interrupt

13 MACB MAC B Interrupt

The NIRQ line is controlled by an 8-level priority encoder. Each source has a programmable priority level of 7 to 0. Level 7 is the highest priority and level 0 the lowest. the lowest interrupt source number is serviced first. depending on whether the AIC_IVR has been read.

1. If the NIRQ line has been asserted but the AIC_IVR
2. If the processor has already read the AIC_IVR, then

ceding lower priority interrupt which had been interrupted. rupt Command Register (AIC_EOICR) must be written. This allows pending interrupts to be serviced. servicing of other interrupts. able for auto-test or software debug purposes.

1. The CPSR is stored in SPSR_irq, the current value

R14_IRQ, decrementing it by 4.

1. The ARM core enters IRQ mode if it is not already.
2. When the instruction at 0x18 is executed, the Pro-

grammed to be edge-triggered. Pushes the current level on to the stack.

14 UARTB USART B Interrupt

15 PIOB PIO B Interrupt

Table 17. Interrupt Sources (Continued)

1. The previous step establishes a connection to the corresponding ISR. This begins by saving the link register (R14_IRQ) and the SPSR (SPSR_IRQ). Note that the link register must be decrermented by 4 when it is saved if it is to be restored directly into the Program Counter at the end of the interrupt. 5. Further interrupts can then be unmasked by clear- ing the I bit in the CPSR, allowing re-assertion of the NIRQ to be taken into account by the core. This can occur if an interrupt with a higher priority than the current one occurs. 6. The interrupt handler then proceeds as required, saving the registers which are used and restoring them at the end. During this phase, an interrupt of priority higher than the current level will restart the sequence from step 1. Note that if the interrupt is programmed to be level-sensitive, the source of the interrupt must be cleared during this phase. 7. The I bit in the CPSR must be set in order to mask interrupts before exiting to ensure that the interrupt is completed in an orderly manner. 8. The service routine should then connect to the com- mon exit routine. 9. The End Of Interrupt Command Register (AIC_EOICR) must be written in order to indicate to the AIC that the current interrupt is finished. This causes the current level to be popped from the stack, restoring the previous current level if one exists. If another interrupt with lower or equal prior- ity than the old current level is pending, the nIRQ line is re-asserted but the interrupt sequence does not immediately start because the I bit is set in the core. 10. The SPSR (SPSR_IRQ) is restored. Finally, the saved value of the Link Register is restored directly into the PC. This has the effect of returning from the interrupt to the step previously executed, of loading the CPSR with the stored SPSR and of masking or unmasking the interrupts depending on the state saved in the SPSR (the previous state of the ARM core). Note: The I bit in the SPSR is significant. If it is set, it indicates that the ARM core was just about to mask IRQ interrupts when the mask instruction was interrupted. Hence, when the SPSR is restored, the mask instruction is completed (IRQ is masked). Fast Interrupt The external FIQ line is the only source which can raise a fast interrupt request to the processor. Therefore it has no priority controller. It can be programmed to be positive- or negative-edge triggered or high- or low-level sensitive in the AIC_SMR0 register. The fast interrupt handler address can be stored in the AIC_SVR0 register. The value written into this register is available by reading the AIC_FVR register when an FIQ interrupt is raised. By storing the following instruction at address 0x0000001C, the processor will load the program counter with the interrupt handler address stored in the AIC_FVR register. LDR PC, [PC, #-&F20] Alternatively, the interrupt handler can be stored starting from address 0x0000001C as described in the ARM7TDMI datasheet. Fast Interrupt Sequence It is assumed that:  The advanced interrupt controller has been programmed, AIC_SVR[0] is loaded with the fast interrupt service routine address and the fast interrupt is enabled.  Nested fast interrupts are not needed by the user. When NFIQ is asserted, if the bit F of CPSR is 0, the sequence is: 1. The CPSR is stored in SPSR_fiq, the current value of the Program Counter is loaded in the FIQ link register (R14_FIQ) and the Program Counter (R15) is loaded with 0x1C. In the following cycle, during fetch at address 0x20, the ARM core adjusts R14_FIQ, decrementing it by 4. 2. The ARM core enters FIQ mode. 3. When the instruction loaded at address 0x1C is executed, the Program Counter is loaded with the value read in AIC_FVR. Reading the AIC_FVR has the effect of clearing the fast interrupt (source 0 connected to the FIQ line) if it has been pro- grammed to be edge-triggered. In this case only, it de-asserts the nFIQ line on the processor. 4. The previous step establishes a connection to the corresponding interrupt service routine. It is not necessary to save the Link Register (R14_FIQ) and the SPSR (SPSR_FIQ) if nested fast interrupts are not needed. 5. The interrupt handler can then proceed as required. It is not necessary to save registers R8 to R13 because FIQ mode has its own dedicated registers and the user R8 to R13 are banked. The other reg- isters, R0 to R7, must be saved before being used and restored at the end (before the next step). Note that if the fast interrupt is programmed to be level- sensitive, the source of the interrupt must be

cleared during this phase in order to de-assert the NFIQ line. 6. Finally, the Link Register (R14_FIQ) is restored into the PC after decrementing it by 4 (e.g., with instruc- tion SUB PC, LR, #4). This has the effect of returning from the interrupt to the step previously executed, of loading the CPSR with the SPSR and of masking or unmasking the fast interrupt depend- ing on the state saved in the SPSR. Note: The F bit in the SPSR is significant. If it is set, it indicates that the ARM core was just about to mask FIQ interrupts when the mask instruction was interrupted. Hence, when the SPSR is restored, the interrupted instruction is com- pleted (FIQ is masked). Software Interrupt Any interrupt source of the AIC can be a software interrupt. It must be programmed to be edge-triggered in order to set or clear it by writing to the AIC_ISCR and AIC_ICCR. This is totally independent of the SWI instruction of the ARM7TDMI processor. Spurious Interrupt A spurious interrupt is a signal of very short duration on one of the interrupt input lines. A spurious interrupt also arises when an interrupt is triggered and masked in the same cycle. Spurious Interrupt Sequence A spurious interrupt is handled by the following sequence of actions. 1. When an interrupt is active, the AIC asserts the nIRQ (or nFIQ) line and the ARM7TDMI enters IRQ (or FIQ) mode. At this moment, if the interrupt source disappears, the nIRQ (or nFIQ) line is de- asserted but the ARM7TDMI continues with the interrupt handler. 2. If the IRQ Vector Register (AIC_IVR) is read when the nIRQ is not asserted, the AIC_IVR is read with the contents of the Spurious Interrupt Vector Register. 3. If the FIQ Vector Register (AIC_FVR) is read when the nFIQ is not asserted, the AIC_FVR is read with the contents of the Spurious Interrupt Vector Register. 4. The Spurious ISR must write an End of Interrupt command as a minimum, however, it is sufficient to write to the End of Interrupt Command Register (AIC_EOICR). Until the AIC_EOICR write is received by the interrupt controller, the nIRQ (or nFIQ) line is not re-asserted. 5. This causes the ARM7TDMI to jump into the Spuri- ous Interrupt Routine. 6. During a spurious ISR, the AIC_ISR reads 0.

Note: 1. The reset value of this register depends on the level of the external IRQ lines. All other sources are cleared at reset. Programs the priority level for all sources except source 0 (FIQ). The priority level can be between 0 (lowest) and 7 (highest). The priority level is not used for the FIQ in the SMR0. Table 18. AIC Memory Map

 SRCTYPE: Interrupt Source Type Programs the input to be positive- or negative-edge triggered or positive- or negative-level sensitive. The active level or edge is not programmable for the internal sources. AIC Source Vector Registers Register Name: AIC_SVR0...AIC_SVR31 Access Type:Read/write Reset Value: 0  Vector In these registers, the user may store the addresses of the corresponding handler for each interrupt source. AIC Interrupt Vector Registers Register Name: AIC_IVR Access Type:Read-only Reset Value: 0  IRQV The IRQ Vector Register contains the vector programmed by the user in the Source Vector Register corresponding to the current interrupt. The SVR Register (1 to 31) is indexed by the current interrupt number when the IVR register is read. When there is no interrupt, the IRQ register reads 0. SRCTYPE Internal Sources External Sources

00 Level-sensitive Low-level sensitive

01 Edge-triggered Negative-edge triggered

10 Level-sensitive High-level sensitive

11 Edge-triggered Positive-edge triggered

Register Name: AIC_FVR Access Type:Read-only Reset Value: 0  FIQ The vector register contains the vector programmed by the user in SVR Register 0 which corresponds to FIQ. AIC Interrupt Status Register Register Name: AIC_ISR Access Type:Read-only Reset Value: 0  IRQID The interrupt status register returns the current interrupt source register. 31 30 29 28 27 26 25 24 FIQV 23 22 21 20 19 18 17 16 FIQV 15 14 13 12 11 10 9 8 FIQV 76543210 FIQV 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 ––– IRQID

AIC Interrupt Pending Register Register Name: AIC_IPR Access Type:Read-only Reset Value: Undefined Note: 1. IRQ1 is available only in 256-lead PQFP package.  Interrupt Pending 0 = Corresponding interrupt is inactive 1 = Corresponding interrupt is pending AIC Interrupt Mask Register Register Name: AIC_IMR Access Type:Read-only Reset Value: 0 Note: 1. IRQ1 is available only in 256-lead PQFP package.  Interrupt Pending 0 = Corresponding interrupt is inactive 1 = Corresponding interrupt is pending 31 30 29 28 27 26 25 24 00000000 23 22 21 20 19 18 17 16 00000000 15 14 13 12 11 10 9 8 PIOB USARTB MACB OAKA IRQ1 (1) INT0 SPI MACA 76543210 PIOA TC2 TC1 TC0 USARTA SWI WDT FIQ 31 30 29 28 27 26 25 24 00000000 23 22 21 20 19 18 17 16 00000000 15 14 13 12 11 10 9 8 PIOB USARTB MACB OAKA IRQ1 (1) INT0 SPI MACA 76543210 PIOA TC2 TC1 TC0 USARTA SWI WDT FIQ

AIC Core Interrupt Status Register Register Name: AIC_CISR Access Type:Read-only Reset Value:0  NFIQ: NFIQ Status 0 = NFIQ line inactive. 1 = NFIQ line active.  NIRQ: NIRQ Status 0 = NIRQ line inactive. 1 = NIRQ line active. AIC Interrupt Enable Command Register Register Name: AIC_IECR Access Type:Write-only Reset Value:Undefined  NFIQ: NFIQ Status 0 = NFIQ line inactive. 1 = NFIQ line active.  NIRQ: NIRQ Status 0 = NIRQ line inactive. 1 = NIRQ line active. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210

AIC Interrupt Disable Command Register Register Name: AIC_IDCR Access Type:Write-only Reset Value: Undefined  NFIQ: NFIQ Status 0 = NFIQ line inactive. 1 = NFIQ line active.  NIRQ: NIRQ Status 0 = NIRQ line inactive. 1 = NIRQ line active. AIC Interrupt Clear Command Register Register Name: AIC_ICCR Access Type:Write-only Reset Value: Undefined  NFIQ: NFIQ Status 0 = NFIQ line inactive. 1 = NFIQ line active.  NIRQ: NIRQ Status 0 = NIRQ line inactive. 1 = NIRQ line active. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210

AIC Interrupt Set Command Register Register Name: AIC_ISCR Access Type:Write only Reset Value: Undefined  NFIQ: NFIQ Status 0 = NFIQ line inactive. 1 = NFIQ line active.  NIRQ: NIRQ Status 0 = NIRQ line inactive. 1 = NIRQ line active. AIC End of Interrupt Command Register Register Name: AIC_EOICR Access Type:Write-only The End of Interrupt Command Register is used by the interrupt routine to indicate that the interrupt treatment is complete. Any value can be written because it is only necessary to make a write to this register location to signal the end of interrupt treatment. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210

AIC Spurious Interrupt Vector Register Register Name: AIC_SPU Access Type:Read/write Reset Value: 0  SIQV This register contains the 32-bit address of an interrupt routine which is used to treat cases of spurious interrupts. The programmed address is read in the AIC_IVR if it is read when the nIRQ line is not asserted. The programmed address is read in the AIC_FVR if it read when the nFIQ line is not asserted. 31 30 29 28 27 26 25 24 SIQV 23 22 21 20 19 18 17 16 SIQV 15 14 13 12 11 10 9 8 SIQV 76543210 SIQV

PIO: Programmable I/O Controller The AT75C220 integrates 24 programmable I/O pins (PIO). Each pin can be programmed as an input or an output. Each pin can also generate an interrupt. The programma- ble I/O is implemented as two blocks, called PIO A and PIO B, 14 and 10 pins each, respectively. These pins are used for several functions:  external I/O for internal peripherals  keypad controller function  general-purpose I/O  visibility in test/debug mode, e.g., multiplex CBUS for the Oak The keypad controller is implemented by using up to ten PIO B pins as row drivers and column sensors for an off- chip switch matrix. This block is identical to the PIOA except that only 14 pins are controlled. The PIO B register map defines an set of registers identical to the PIO A register map. Every PIO B register allocates the same bit position to the corresponding PIO B pin. These registers are otherwise identical to the PIO A registers. Multiplexed I/O Lines Output Selection The user can enable each individual I/O signal as an output with the registers PIO_OER and PIO_ODR. The output sta- tus of the I/O signals can be read in the register PIO_OSR. The direction defined has an effect only if the pin is config- ured to be controlled by the PIO controller. I/O Levels Each pin can be configured to be driven high or low. The level is defined in four different ways, according to the fol- lowing conditions: If a pin is controlled by the PIO controller and is defined as an output (see “Output Selection”), the level is programmed using the registers PIO_SODR and PIO_CODR. In this case, the programmed value can be read in the register PIO_ODSR. If a pin is controlled by the PIO controller and is not defined as an output, the level is determined by the external circuit. If a pin is not controlled by the PIO controller, the state of the pin is defined by the peripheral (see peripheral datasheets). In all cases, the level on the pin can be read in the register PIO_PDSR. Interrupts Each parallel I/O can be programmed to generate an inter- rupt when a level change occurs. This is controlled by the PIO_IER and PIO_IDR registers which enable/disable the I/O interrupt by setting/clearing the corresponding bit in the PIO_IMR. When a change in level occurs, the correspond- ing bit in the PIO_ISR is set depending on whether the pin is used as a PIO or a peripheral, and whether it is defined as input or output. If the corresponding interrupt in PIO_IMR is enabled, the PIO interrupt is asserted. When PIO_ISR is read, the register is automatically cleared. User Interface Each individual I/O is associated with a bit position in the parallel I/O user interface registers. Each of these registers is 32 bits wide. If a parallel I/O line is not defined, writing to the corresponding bits has no effect. Undefined bits read as zero.

Figure 14. Parallel I/O Multiplexed with a Bid-directional Signal

Note: 1. Used if TST pin is active. Table 19. PIO Controller A Connection Table Table 20. PIO Controller B Connection Table

Notes: 1. The reset value of this register depends on the level of the external pins at reset.

1. This register is cleared at reset. However, the first read of the register can give a value not equal to zero if any changes have

occurred on any pins between the reset and the read. Table 21. PIO Controller Memory Map

Register Name:PIO_PER Access Type:Write-only This register is used to enable individual pins to be controlled by the PIO controller instead of the associated peripheral. When the PIO is enabled, the associated peripheral (if any) is held at logic zero. 1 = Enables the PIO to control the corresponding pin (disables peripheral control of the pin). 0 = No effect. PIO Disable Register Register Name: PIO_PDR Access Type:Write-only This register is used to disable PIO control of individual pins. When the PIO control is disabled, the normal peripheral func- tion is enabled on the corresponding pin. 1 = Disables PIO control (enables peripheral control) on the corresponding pin. 0 = No effect. 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0

Register Name:PIO_PSR Access Type:Read-only This register indicates which pins are enabled for PIO control. This register is updated when PIO lines are enabled or dis- abled. 1 = PIO is active on the corresponding line (peripheral is inactive). 0 = PIO is inactive on the corresponding line (peripheral is active). PIO Output Enable Register Register Name:PIO_OER Access Type:Write-only This register is used to enable PIO output drivers. If the pin is driven by a peripheral, there is no effect on the pin but the information is stored. The register is programmed as follows: 1 = Enables the PIO output on the corresponding pin. 0 = No effect. 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0

PIO Output Disable Register Register Name:PIO_ODR Access Type:Write-only This register is used to disable PIO output drivers. If the pin is driven by the peripheral, there is no effect on the pin, but the information is stored. The register is programmed as follows: 1 = Disables the PIO output on the corresponding pin. 0 = No effect. PIO Output Status Register Register Name:PIO_OSR Access Type:Read-only Reset Value:0 This register shows the PIO pin control (output enable) status which is programmed in PIO_OER and PIO ODR. The defined value is effective only if the pin is controlled by the PIO. The register reads as follows: 1 = The corresponding PIO is output on this line. 0 = The corresponding PIO is input on this line. 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0

PIO Set Output Data Register Register Name:PIO_SODR Access Type:Write-only This register is used to set PIO output data. It affects the pin only if the corresponding PIO output line is enabled and if th e pin is controlled by the PIO. Otherwise, the information is stored. 1 = PIO output data on the corresponding pin is set. 0 = No effect. PIO Clear Output Data Register Register Name:PIO_CODR Access Type:Write-only This register is used to clear PIO output data. It affects the pin only if the corresponding PIO output line is enabled and if the pin is controlled by the PIO. Otherwise, the information is stored. 1 = PIO output data on the corresponding pin is cleared. 0 = No effect. 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0

PIO Output Data Status Register Register Name:PIO_ODSR Access Type:Read-only Reset Value:0 This register shows the output data status which is programmed in PIO_SODR or PIO_CODR. The defined value is effec- tive only if the pin is controlled by the PIO Controller and only if the pin is defined as an output. 1 = The output data for the corresponding line is programmed to 1. 0 = The output data for the corresponding line is programmed to 0. PIO Pin Data Status Register Register Name:PIO_PDSR Access Type:Read-only Reset Value:Undefined This register shows the state of the physical pin of the chip. The pin values are always valid, regardless of whether the pins are enabled as PIO, peripheral, input or output. The register reads as follows: 1 = The corresponding pin is at logic 1. 0 = The corresponding pin is at logic 0. 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0

PIO Interrupt Enable Register Register Name:PIO_IER Access Type:Write-only This register is used to enable PIO interrupts on the corresponding pin. It has an effect whether PIO is enabled or not. 1 = Enables an interrupt when a change of logic level is detected on the corresponding pin. 0 = No effect. PIO Interrupt Disable Register Register Name:PIO_IDR Access Type:Write-only This register is used to disable PIO interrupts on the corresponding pin. It has an effect whether the PIO is enabled or not. 1 = Disables the interrupt on the corresponding pin. Logic level changes are still detected. 0 = No effect. 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0

PIO Interrupt Mask Register Register Name:PIO_IMR Access Type:Read-only Reset Value:0 This register shows which pins have interrupts enabled. It is updated when interrupts are enabled or disabled by writing to PIO_IER or PIO_IDR. 1 = Interrupt is enabled on the corresponding pin. 0 = Interrupt is not enabled on the corresponding pin. PIO Interrupt Status Register Register Name:PIO_ISR Access Type:Read-only Reset Value:0 This register indicates for each pin when a logic value change has been detected (rising or falling edge). This is valid whether the PIO is selected for the pin or not and whether the pin is an input or an output. The register is reset to zero following a read and at reset. 1 = At least one input change has been detected on the corresponding pin since the register was last read. 0 = No input change has been detected on the corresponding pin since the register was last read. 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0

external memory) via a dedicated DMA. Figure 15. USART Block Diagram Each USART channel has external signals as defined in Table 22.

baud rate clock) to both the receiver and the transmitter. internal clock sources. The external clock source is SCK. ACLK or the master clock divided by 8 (ACLK/8). least 2.5 times lower than the system clock. US_BRGR is set to 0, the baud rate clock is disabled. Table 22. USART External Signals Table 23. Clock Generator Table

1. For information on obtaining exact baud rates using the value of CD given above, the selected clock frequency must be

Figure 16. Baud Rate Generator

1 Baud Rate

Figure 19. Synchronous Mode: Character Transmission The parity bit is set according to the PAR field in US_MR. duration of the idle state is programmed in US_TTGR. is detected with a parity bit set to identify an address byte. fying a data byte, PARE is not set. a Send Address Command (SENDA) is written to US_CR. have the parity bit cleared.

Figure 20. Synchronous and Asynchronous Mode: Character Transmission before the line is held low. detected. Then the transmitter resumes normal operation. previous character is fully transmitted). (high level for at least 12 bit periods). existing break has ended (TXEMPTY = 1 in US_CSR).

1. Wait for the transmitter ready
2. Wait for the transmitter ready
3. Wait for the transmitter ready

rupt if the bit TXRDY in US_IMR is set. enabled before sending a break. asserted when an end-of-break is detected. by interrupt if the bit RXBRK in register US_IMR is set.

US_IMR, the interrupt line is asserted. ent test modes using the field CHMODE in US_MR. Automatic echo mode allows bit-by-bit re-transmission. line. Programming the transmitter has no effect. pin is held high, as in idle state. Figure 21. Channel Modes

Peripheral Data Controller Each USART channel is closely connected to a corre- sponding peripheral data controller channel. One is dedi- cated to the receiver, the other is dedicated to the transmit- ter. Note: The PDC is disabled if 9-bit character length is selected (MODE9 = 1) in US_MR. The PDC channel is programmed using US_TPR and US_TCR for the transmitter and US_RPR and US_RCR for the receiver. The status of the PDC is given in US_CSR by the ENDTX bit for the transmitter and by the ENDRX bit for the receiver. The pointer registers US_TPR and US_RPR are used to store the address of the transmit or receive buffers. The counter registers US_TCR and US_RCR are used to store the size of these buffers. The receiver data transfer is triggered by the RXRDY bit and the transmitter data transfer is triggered by TXRDY. When a transfer is performed, the counter is decremented and the pointer is incremented. When the counter reaches 0, the status bit is set (ENDRX for the receiver, ENDTX for the transmitter in US_CSR) and can be programmed to generate an interrupt. Transfers are then disabled until a new non-zero counter value is programmed. Modem Control and Status Signals NCTS: Clear to Send When low, this indicates that the modem or data set is ready to exchange data. The NCTS signal is a modem sta- tus input whose conditions can be tested by the CPU reading bit 4 (CTS) of the Modem Status Register. Bit 4 is the complement of the NCTS signal. Bit 0 (DCTS) of the Modem Status Register indicates whether the NCTS input has changed state since the previous reading of the Modem Status Register. NCTS has no effect on the transmitter. In FCM mode when the NCTS signal becomes inactive high, the transmission of the current character will be com- pleted then transmission stops. Note: Whenever the CTS bit of the Modem Status Register changes state, an interrupt is generated if the Modem Status Interrupt is enabled. NDCD: Data Carrier Detect When low, this indicates that the data carrier has been detected by the modem or data set. The NDCD signal is a modem status input whose condition can be tested by the CPU reading bit 7 (DCD) of the Modem Status Register. Bit 7 is the complement of the NDCD signal. Bit 3 (DDCD) of the Modem Status Register indicates whether the NDCD input pin has changed since the previous reading of the Modem Status Register. NDCD has no effect on the receiver. Note: Whenever the DCD bit of the Modem Status Register changes state, an interrupt is generated if the Modem Status Interrupt is enabled. NDSR: Data Set Ready When low, this informs the modem or data set the USART is ready to communicate. The NDSR signal is a modem status input whose condition can be tested by the CPU reading bit 5 (DSR) of the Modem Status Register. Bit 5 is the complement of the NDSR signal. Bit 1 (DDSR of the Modem Status Register) indicates whether the NDSR input has changed state since the previous reading of the Modem Status Register. Note: Whenever the DSSR bit of the Modem Status Register changes state, an interrupt is generated if the Modem Status Interrupt is enabled. NDTR: Data Terminal Ready When low, this informs the modem or data set that the USART is ready to communicate. The NDTR output signal can be set to active low by programming bit 0 (DTR) of the Modem Control Register to a high level. A master reset operation sets this signal to its inactive (high) state. Loop mode operation holds this signal in its inactive state. NRI: Ring Indicator When low, this indicates that a telephone ringing signal has been received by the modem or data set. The NRI signal is a modem status input whose condition can be tested by the CPU reading bit 6 (RI) of the Modem Status Register. Bit 6 is the complement of the NRI signal. Bit 2 (TERI) of the Modem Status Register indicates whether the NRI input signal has changed from a low to a high state since the pre- vious reading of the Modem Status Register. Note: Whenever the RI bit of the Modem Status Register changes from a high to a low state, an interrupt is gener- ated if the Modem Status Interrupt is enabled. NRTS: Request to Send When low, this informs the modem or data set that the USART is ready to exchange data. The NRTS output signal can be set to an active low by programming bit 1 (RTS) of the Modem Control Register. A master reset operation sets this signal to its inactive (high) state. In FCM mode when the last stop bit of a character is transmitted and the Trans- mit Holding Register is empty, the hardware sets NRTS inactive high. Note: Modem control pins must be left high when not used.

Base Address USART A: 0xFF018000 Base Address USART B: 0xFF01C000 Notes: 1. This is either 0x18 or 0x418 depending on the value of bootn and modem control inputs. 2. This depends on the value of modem control input signals, as these are reflected in this register. Offset Register Name Description Access Reset Value 0x00 US_CR Control Register Write-only – 0x04 US_MR Mode Register Read/write 0 0x08 US_IER Interrupt Enable Register Write-only – 0x0C US_IDR Interrupt Disable Register Write-only – 0x10 US_IMR Interrupt Mask Register Read-only 0 0x14 US_CSR Channel Status Register Read-only 0x18 (1) 0x18 US_RHR Receiver Holding Register Read-only 0 0x1C US_THR Transmitter Holding Register Write-only – 0x20 US_BRGR Baud Rate Generator Register Read/write 0 0x24 US_RTOR Receiver Time-out Register Read/write 0 0x28 US_TTGR Transmitter Time-guard Register Read/write 0 0x2C – Reserved – – 0x30 US_RPR Receive Pointer Register Read/write 0 0x34 US_RCR Receive Counter Register Read/write 0 0x38 US_TPR Transmit Pointer Register Read/write 0 0x3C US_TCR Transmit Counter Register Read/write 0 0x40 US_MC Modem Control Register Write-only – 0x44 US_MS Modem Status Register Read-only (See Note 2)

Name: US_CR Access Type:Write-only Reset Value:Undefined  RSTRX: Reset Receiver 0 = No effect. 1 = The receiver logic is reset.  RSTTX: Reset Transmitter 0 = No effect. 1 = The transmitter logic is reset.  RXEN: Receiver Enable 0 = No effect. 1 = The receiver is enabled if RXDIS is 0.  RXDIS: Receiver Disable 0 = No effect. 1 = The receiver is disabled.  TXEN: Transmitter Enable 0 = No effect. 1 = The transmitter is enabled if TXDIS is 0.  TXDIS: Transmitter Disable 0 = No effect. 1 = The transmitter is disabled.  RSTSTA: Reset Status Bits 0 = No effect. 1 = Resets the status bits PARE, FRAME, OVRE and RXBRK in the US_CSR.  STTBRK: Start Break 0 = No effect. 1 = If break is not being transmitted, starts transmission of a break after the characters present in US_THR and the Transmit Shift Register have been transmitted.  STPBRK: Stop Break 0 = No effect. 1 = If a break is being transmitted, stops transmission of the break after a minimum of one character length and trans- mits a high level during 12 bit periods.  STTTO: Start Time-out 0 = No effect. 1 = Starts waiting for a character before clocking the time-out counter.  SENDA: Send Address 0 = No effect. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 ––– SENDA STTTO STPBRK STTBRK RSTSTA 76543210 TXDIS TXEN RXDIS RXEN RSTTX RSTRX ––

1 = In multi-drop mode only, the next character written to the US_THR is sent with the address bit set.

Name: US_MR Access Type:Read/write Reset Value:0x0  USCLKS: Clock Selection (Baud Rate Generator Input Clock)  CHRL: Character Length Start, stop and parity bits are added to the character length.  SYNC: Synchronous Mode Select 0 = USART operates in asynchronous mode. 1 = USART operates in synchronous mode.  PAR: Parity Type 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 CHMODE NBSTOP PAR SYNC 76543210 CHRL USCLKS –––– USCLKS Selected Clock

00 ACLK

01 ACLK/8

1X External (SCK) CHRL Character Length

00 Five bits

01 Six bits

10 Seven bits

11 Eight bits

000 Even parity

001 Odd parity

010 Parity forced to 0 (space)

011 Parity forced to 1 (mark)

 NBSTOP: Number of Stop Bits The interpretation of the number of stop bits depends on SYNC.  CHMODE: Channel Mode  MODE9: 9-bit Character Length 0 = CHRL defines character length. 1 = 9-bit character length.  CKLO: Clock Output Select 0 = The USART does not drive the SCK pin. 1 = The USART drives the SCK pin if USCLKS[1] is 0. NBSTOP Asynchronous (SYNC = 0) Synchronous (SYNC = 1) 0 0 1 stop bit 1 stop bit 0 1 1.5 stop bits Reserved 1 0 2 stop bits 2 stop bits 1 1 Reserved Reserved CHMODE Mode Description 0 0 Normal Mode The USART channel operates as an Rx/Tx USART. 0 1 Automatic Echo Receiver data input is connected to TXD pin. 1 0 Local Loopback Transmitter output signal is connected to receiver input signal. 1 1 Remote Loopback RXD pin is internally connected to TXD pin.

USART Interrupt Enable Register Name: US_IER Access Type:Write-only Reset Value: Undefined  RXRDY: Enable RXRDY Interrupt 0 = No effect. 1 = Enables RXRDY interrupt.  TXRDY: Enable TXRDY Interrupt 0 = No effect. 1 = Enables TXRDY interrupt.  RXBRK: Enable Receiver Break Interrupt 0 = No effect. 1 = Enables receiver break interrupt.  ENDRX: Enable End of Receive Transfer Interrupt 0 = No effect. 1 = Enables end of receive transfer interrupt.  ENDTX: Enable End of Transmit Transfer Interrupt 0 = No effect. 1 = Enables end of transmit transfer interrupt.  OVRE: Enable Overrun Error Interrupt 0 = No effect. 1 = Enables overrun error interrupt.  FRAME: Enable Framing Error Interrupt 0 = No effect. 1 = Enables framing error interrupt.  PARE: Enable Parity Error Interrupt 0 = No effect. 1 = Enables parity error interrupt.  TIMEOUT: Enable Time-out Interrupt 0 = No effect. 1 = Enables reception time-out interrupt.  TXEMPTY: Enable TXEMPTY Interrupt 0 = No effect. 1 = Enables TXEMPTY interrupt.  DMSI: Delta Modem Status Indication Interrupt 0 = No effect. 1 = Enables DMSI interrupt. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 ––––– DMSI TXEMPTY TIMEOUT 76543210 PARE FRAME OVRE ENDTX ENDRX RXBRK TXRDY RXRDY

USART Interrupt Disable Register Name: US_IDR Access Type:Write-only Reset Value: Undefined  RXRDY: Disable RXRDY Interrupt 0 = No effect. 1 = Disables RXRDY interrupt.  TXRDY: Disable TXRDY Interrupt 0 = No effect. 1 = Disables TXRDY interrupt.  RXBRK: Disable Receiver Break Interrupt 0 = No effect. 1 = Disables receiver break interrupt.  ENDRX: Disable End of Receive Transfer Interrupt 0 = No effect. 1 = Disables end of receive transfer interrupt.  ENDTX: Disable End of Transmit Transfer Interrupt 0 = No effect. 1 = Disables end of transmit transfer interrupt.  OVRE: Disable Overrun Error Interrupt 0 = No effect. 1 = Disables overrun error interrupt.  FRAME: Disable Framing Error Interrupt 0 = No effect. 1 = Disables framing error interrupt.  PARE: Disable Parity Error Interrupt 0 = No effect. 1 = Disables Parity Error Interrupt.  TIMEOUT: Disable Time-out Interrupt 0 = No effect. 1 = Disables receiver time-out interrupt.  TXEMPTY: Disable TXEMPTY Interrupt 0 = No effect. 1 = Disables TXEMPTY interrupt.  DMSI: Delta Modem Status Indication Interrupt 0 = No effect. 1 = Disables DMSI interrupt. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 ––––– DMSI TXEMPTY TIMEOUT 76543210 PARE FRAME OVRE ENDTX ENDRX RXBRK TXRDY RXRDY

USART Interrupt Mask Register Name: US_IMR Access Type:Read-only Reset Value: 0x0  RXRDY: RXRDY Interrupt Mask 0 = RXRDY interrupt is disabled. 1 = RXRDY interrupt is enabled.  TXRDY: TXRDY Interrupt Mask 0 = TXRDY interrupt is disabled. 1 = TXRDY interrupt is enabled.  RXBRK: Receiver Break Interrupt Mask 0 = Receiver break interrupt is disabled. 1 = Receiver break interrupt is enabled.  ENDRX: End of Receive Transfer Interrupt Mask 0 = End of Receive Transfer Interrupt is disabled. 1 = End of Receive Transfer Interrupt is enabled.  ENDTX: End of Transmit Transfer Interrupt Mask 0 = End of transmit transfer interrupt is disabled. 1 = End of transmit transfer interrupt is enabled.  OVRE: Overrun Error Interrupt Mask 0 = Overrun error interrupt is disabled. 1 = Overrun error interrupt is enabled.  FRAME: Framing Error Interrupt Mask 0 = Framing error interrupt is disabled. 1 = Framing error interrupt is enabled.  PARE: Parity Error Interrupt Mask 0 = Parity error interrupt is disabled. 1 = Parity error interrupt is enabled.  TIMEOUT: Time-out Interrupt Mask 0 = Receive time-out interrupt is disabled. 1 = Receive time-out interrupt is enabled.  TXEMPTY: TXEMPTY Interrupt Mask 0 = TXEMPTY interrupt is disabled. 1 = TXEMPTY interrupt is enabled.  DMSI: Delta Modem Status Indication Interrupt 0 = DMSI interrupt is disabled. 1 = DMSI interrupt is enabled. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 ––––– DMSI TXEMPTY TIMEOUT 76543210 PARE FRAME OVRE ENDTX ENDRX RXBRK TXRDY RXRDY

USART Channel Status Register Name: US_CSR Access Type:Read-only Reset Value: 0x18  RXRDY: Receiver Ready 0 = No complete character has been received since the last read of the US_RHR or the receiver is disabled. 1 = At least one complete character has been received and the US_RHR has not yet been read.  TXRDY: Transmitter Ready 0 = US_THR contains a character waiting to be transferred to the Transmit Shift Register. 1 = US_THR is empty and there is no break request pending TSR availability. Equal to zero when the USART is disabled or at reset. Transmitter enable command (in US_CR) sets this bit to one.  RXBRK: Break Received/End of Break 0 = No break received or end of break detected since the last reset status bits command in the Control Register. 1 = Break received or end of break detected since the last reset status bits command in the Control Register.  ENDRX: End-of-receive Transfer 0 = The end-of-transfer signal from the PDC channel dedicated to the receiver is inactive. 1 = The end-of-transfer signal from the PDC channel dedicated to the receiver is active.  ENDTX: End-of-transmit Transfer 0 = The end-of-transfer signal from the PDC channel dedicated to the transmitter is inactive. 1 = The end-of-transfer signal from the PDC channel dedicated to the transmitter is active.  OVRE: Overrun Error 0 = No byte has been transferred from the Receive Shift Register to the US_RHR when RxRDY was asserted since the last reset status bits command. 1 = At least one byte has been transferred from the Receive Shift Register to the US_RHR when RxRDY was asserted since the last reset status bits command.  FRAME: Framing Error 0 = No stop bit has been detected low since the last reset status bits command. 1 = At least one stop bit has been detected low since the last reset status bits command.  PARE: Parity Error 1 = At least one parity bit has been detected false (or a parity bit high in multi-drop mode) since the last reset status bit” command. 0 = No parity bit has been detected false (or a parity bit high in multi-drop mode) since the last reset status bits command.  TIMEOUT: Receiver Time-out 0 = There has not been a time-out since the last start time-out command or the Time-out Register is 0. 1 = There has been a time-out since the last start time-out command. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 ––––– DMSI TXEMPTY TIMEOUT 76543210 PARE FRAME OVRE ENDTX ENDRX RXBRK TXRDY RXRDY

 TXEMPTY: Transmitter Empty 0 = There are characters in either US_THR or the Transmit Shift Register or a break is being transmitted. 1 = There are no characters in US_THR and the Transmit Shift Register and break is not active. Equal to zero when the USART is disabled or at reset. Transmitter enable command (in US_CR) sets this bit to one.  DMSI: Delta Modem Status Indication Interrupt 0 = No effect. 1 = There has been a change in the modem status delta bits since the last reset status bits command. USART Receiver Holding Register Name: US_RHR Access Type:Read-only Reset Value: 0x0  RXCHR: Received Character Last character received if RXRDY is set. When number of data bits is less than eight, the bits are right-aligned. All unused bits read as zero. USART Transmitter Holding Register Name: US_THR Access Type:Write-only Reset Value: Undefined  TXCHR: Character to be Transmitted Next character to be transmitted after the current character if TXRDY is not set. When number of data bits is less than eight, the bits are right-aligned. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 RXCHR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 TXCHR

USART Baud Rate Generator Register Name: US_BRGR Access Type:Read/write Reset Value: 0x0  CD: Clock Divisor This register has no effect if synchronous mode is selected with an external clock. Note: In synchronous mode, the value programmed must be even to ensure a 50:50 mark-to-space ratio. Note: Clock divisor bypass (CD = 1) must not be used when internal clock ACLK is selected (USCLKS = 0). 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 CD 76543210 CD CD Effect

0 Disables clock

1 Clock divisor bypass

2 to 65535 Baud rate (asynchronous mode) = Selected clock/(16 x CD) Baud rate (synchronous mode) = Selected clock/CD

USART Receiver Time-out Register Name: US_RTOR Access Type:Read/write Reset Value: 0x0  TO: Time-out Value When a value is written to this register, a start time-out command is automatically performed. Time-out duration = TO x 4 x Bit period 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 TO TO Effect 0 Disables the RX time-out function. 1 - 255 The time-out counter is loaded with TO when the start time-out command is given or when each new data character is received (after reception has started).

USART Transmitter Time-guard Register Name: US_TTGR Access Type:Read/write Reset Value: 0x0  TG: Time-guard Value Time-guard duration = TG x Bit period USART Receive Pointer Register Name: US_RPR Access Type:Read/write Reset Value: 0x0  RXPTR: Receive Pointer RXPTR must be loaded with the address of the receive buffer. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 TG TG Effect 0 Disables the TX time-guard function. 1 - 255 TXD is inactive high after the transmission of each character for the time-guard duration. 31 30 29 28 27 26 25 24 RXPTR 23 22 21 20 19 18 17 16 RXPTR 15 14 13 12 11 10 9 8 RXPTR 76543210 RXPTR

USART Receive Counter Register Name: US_RCR Access Type:Read/write Reset Value: 0x0  RXCTR: Receive Counter RXCTR must be loaded with the size of the receive buffer. 0: Stop peripheral data transfer dedicated to the receiver. 1 - 65535: Start peripheral data transfer if RXRDY is active. USART Transmit Pointer Register Name: US_TPR Access Type:Read/write Reset Value: 0x0  TXPTR: Transmit Pointer TXPTR must be loaded with the address of the transmit buffer. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 RXCTR 76543210 RXCTR 31 30 29 28 27 26 25 24 TXPTR 23 22 21 20 19 18 17 16 TXPTR 15 14 13 12 11 10 9 8 TXPTR 76543210 TXPTR

USART Transmit Counter Register Name: US_TCR Access Type:Read/write Reset Value: 0x0  TXCTR: Transmit Counter TXCTR must be loaded with the size of the transmit buffer. 0: Stop peripheral data transfer dedicated to the transmitter. 1 - 65535: Start peripheral data transfer if TXRDY is active. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 TXCTR 76543210 TXCTR

Register Name:US_MC Access Type:Write-only Reset Value: Undefined This register controls the interface with the modem or data set (or a peripheral device emulating a modem). The contents of the Control Register are indicated below.  DTR: Data Terminal Ready This bit controls the NDTR output. When bit 0 is set to a logic 1, the NDTR output is forced to a logic 0. When bit 0 is reset to a logic 0, the NDTR output is forced to a logic 1. Note: The NDTR output of the UART can be applied to an EIA inverting line driver to obtain proper polarity input at the succeedi ng modem or data set.  RTS: Request to Send This bit controls the NRTS output. Bit 1 affects the NRTS output in a manner identical to that described above for bit 0.  FCM: Flow Control Mode When FCM is set high, the hardware can perform operations automatically depending on the state of NCTS and char- acter transmission logic. Such changes take place immediately and are reflected in the values read in the Modem Status Register. This flag is set low at reset. In flow control mode, transmission should occur only if NCTS is active. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210

Register Name:US_MS Access Type:Read-only Reset Value:Undefined This register provides the current state of the control lines from the modem (or peripheral device) to the CPU. In addition to this current-state information, four bits of the Modem Status Register provide change information. These bits are set to a logic 1 whenever a control input from the modem changes state. They are reset to logic 0 whenever the CPU reads the Modem Status Register.  DCTS: Delta Clear to Send Bit 0 indicates that the NCTS input to the chip has changed state since the last time it was read by the CPU.  DDSR: Delta Data Set Ready Bit 1 indicates that the NDSR input to the chip has changed state since the last time it was read by the CPU.  TERI: Trailing Edge Ring Indicator Bit 2 indicates that the NRI input to the chip has changed from a low to a high state.  DDCD: Delta Data Carrier Detect Bit 3 indicates that the NDCD input has changed state. Note that whenever bit 0, 1, 2, or 3 is set to logic 1, a modem status interrupt is generated. This is reflected in the modem status register.  CTS: Clear to Send This bit is the complement of the Clear to Send (NCTS) input.  DSR: Data Set Ready This bit is the complement of the Data Set Ready (NDSR) input.  RI: Ring Indicator This bit is the complement of the Ring Indicator (NRI) input.  DCD: Data Carrier Detect This bit is the complement of the Data Carrier Detect (NDCD) input.  FCMS: Flow Control Status This bit indicates the value of the FCM in the US_MC. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 DCD RI DSR CTS DDCD TERI DDSR DCTS

delay timing and pulse-width modulation. grammed to generate processor interrupts via the AIC. Figure 22. Timer/Counter Block Diagram

Note: After a hardware reset, the timer/counter block pins are controlled by the PIO controller. They must be configured to be c on- trolled by the peripheral before being used. Timer/Counter Description The three timer/counter channels are independent and identical in operation. The registers for channel program- ming are listed in Table 25 on page 106. Counter Each timer/counter channel is organized around a 16-bit counter. The value of the counter is incremented at each positive edge of the selected clock. When the counter has reached the value 0xFFFF and passes to 0x0000, an over- flow occurs and the bit COVFS in TC_SR (Status Register) is set. The current value of the counter is accessible in real time by reading TC_CV. The counter can be reset by a trigger. In this case, the counter value passes to 0x0000 on the next valid edge of the selected clock. Clock Selection At block level, input clock signals of each channel can either be connected to the external inputs TCLK0, TCLK1 or TCLK2, or be connected to the configurable I/O signals TIOA0, TIOA1 or TIOA2 for chaining by programming the TC_BMR (Block Mode). Each channel can independently select an internal or exter- nal clock source for its counter:  Internal clock signals: ACLK/2, ACLK/8, ACLK/32, ACLK/128, ACLK/1024  External clock signals: XC0, XC1 or XC2 The selected clock can be inverted with the CLKI bit in TC_CMR (Channel Mode). This allows counting on the opposite edges of the clock. The burst function allows the clock to be validated when an external signal is high. The BURST parameter in the Mode Register defines this signal (none, XC0, XC1, XC2). Note: In all cases, if an external clock is used, the duration of each of its levels must be longer than the system clock (ACLK) period. The external clock frequency must be at least 2.5 times lower than the system clock (ACLK). Channel Signal Description Type XC0, XC1, XC2 External clock inputs I TIOA Capture mode: General-purpose input Waveform mode: General-purpose output I O TIOB Capture mode: General-purpose input Waveform mode: General-purpose input/output I O INT Interrupt signal output O SYNC Synchronization input signal I Block Signal TCLK0, TCLK1, TCLK2 External clock inputs I TIOA0 TIOA signal for Channel 0 I/O TIOB0 TIOB signal for Channel 0 I/O TIOA1 TIOA signal for Channel 1 I/O TIOB1 TIOB signal for Channel 1 I/O TIOA2 TIOA signal for Channel 2 I/O TIOB2 TIOB signal for Channel 2 I/O

This mode is entered by clearing the WAVE parameter in TC_CMR (Channel Mode Register). Capture mode allows the TC Channel to perform measurements such as pulse timing, frequency, period, duty cycle and phase on TIOA and TIOB signals which are inputs. Figure 25 shows the configuration of the TC Channel when programmed in capture mode. Capture Registers A and B (RA and RB) Registers A and B are used as capture registers. This means that they can be loaded with the counter value when a programmable event occurs on the signal TIOA. The parameter LDRA in TC_CMR defines the TIOA edge for the loading of register A, and the parameter LDRB defines the TIOA edge for the loading of Register B. RA is loaded only if it has not been loaded since the last trigger or if RB has been loaded since the last loading of RA. RB is loaded only if RA has been loaded since the last trig- ger or the last loading of RB. Loading RA or RB before the read of the last value loaded sets the Overrun Error Flag (LOVRS) in TC_SR (Status Register). In this case, the old value is overwritten. Trigger Conditions In addition to the SYNC signal, the software trigger and the RC compare trigger, an external trigger can be defined. Bit ABETRG in TC_CMR selects input signal TIOA or TIOB as an external trigger. Parameter ETRGEDG defines the edge (rising, falling or both) detected to generate an exter- nal trigger. If ETRGEDG = 0 (none), the external trigger is disabled. Status Register The following bits in the status register are significant in capture operating mode.  CPCS: RC Compare Status There has been an RC Compare match at least once since the last read of the status.  COVFS: Counter Overflow Status The counter has attempted to count past $FFFF since the last read of the status.  LOVRS: Load Overrun Status RA or RB has been loaded at least twice without any read of the corresponding register since the last read of the status.  LDRAS: Load RA Status RA has been loaded at least once without any read since the last read of the status.  LDRBS: Load RB Status RB has been loaded at least once without any read since the last read of the status.  ETRGS: External Trigger Status An external trigger on TIOA or TIOB has been detected since the last read of the status.

Figure 25. Capture Mode

This mode is entered by setting the WAVE parameter in TC_CMR (Channel Mode Register). Waveform operating mode allows the TC channel to gener- ate 1 or 2 PWM signals with the same frequency and inde- pendently programmable duty cycles or to generate differ- ent types of one-shot or repetitive pulses. In this mode, TIOA is configured as output and TIOB is defined as output if it is not used as an external event (EEVT parameter in TC_CMR). Figure 26 shows the configuration of the TC channel when programmed in waveform operating mode. Compare Register A, B and C (RA, RB, and RC) In waveform operating mode, RA, RB and RC are all used as compare registers. RA Compare is used to control the TIOA output. RB Com- pare is used to control the TIOB (if configured as output). RC Compare can be programmed to control TIOA and/or TIOB outputs. RC Compare can also stop the counter clock (CPCSTOP = 1 in TC_CMR) and/or disable the counter clock (CPCDIS = 1 in TC_CMR). As in capture mode, RC Compare can also generate a trig- ger if CPCTRG = 1. A trigger resets the counter so RC can control the period of PWM waveforms. External Event/Trigger Conditions An external event can be programmed to be detected on one of the clock sources (XC0, XC1, XC2) or TIOB. The external event selected can then be used as a trigger. The parameter EEVT in TC_CMR selects the external trig- ger. The parameter EEVTEDG defines the trigger edge for each of the possible external triggers (rising, falling or both). If EEVTEDG is cleared (none), no external event is defined. If TIOB is defined as an external event signal (EEVT = 0), TIOB is no longer used as output and the TC channel can only generate a waveform on TIOA. When an external event is defined, it can be used as a trig- ger by setting bit ENETRG in TC_CMR. As in capture mode, the SYNC signal, the software trigger and the RC compare trigger are also available as triggers. Output Controller The output controller defines the output level changes on TIOA and TIOB following an event. TIOB control is used only if TIOB is defined as output (not as an external event). The following events control TIOA and TIOB: software trig- ger, external event and RC compare. RA compare controls TIOA and RB compare controls TIOB. Each of these events can be programmed to set, clear or toggle the out- put as defined in the corresponding parameter in TC_CMR. The tables below show which parameter in TC_CMR is used to define the effect of each event. If two or more events occur at the same time, the priority level is defined as follows: 1. Software trigger 2. External event 3. RC compare 4. RA or RB compare Status The following bits in the status register are significant in waveform mode:  CPAS: RA Compare Status There has been a RA Compare match at least once since the last read of the status  CPBS: RB Compare Status There has been a RB Compare match at least once since the last read of the status  CPCS: RC Compare Status There has been a RC Compare match at least once since the last read of the status  COVFS: Counter Overflow Counter has attempted to count past $FFFF since the last read of the status  ETRGS: External Trigger External trigger has been detected since the last read of the status Parameter TIOA Event ASWTRG Software trigger AEEVT External event ACPC RC compare ACPA RA compare Parameter TIOB Event BSWTRG Software trigger BEEVT External event BCPC RC compare BCPB RB compare

Figure 26. Waveform Mode

each of the channel registers in Table 25 is in relation to the offset of the corresponding channel as stated in Table 24. Table 24. TC Global Memory Map Table 25. TC Channel Memory Map

Register Name:TC_BCR Access Type:Write-only  SYNC: Synchro Command 0 = No effect. 1 = Asserts the SYNC signal which generates a software trigger simultaneously for each of the channels. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210

Register Name:TC_BMR Access Type:Read/write Reset Value: 0x0  TC0XC0S: External Clock Signal 0 Selection  TC1XC1S: External Clock Signal 1 Selection  TC2XC2S: External Clock Signal 2 Selection 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 –– TC2XC2S TC1XC1S TC0XC0S TC0XC0S Signal Connected to XC0

00 T C L K 0

01 N o n e

10 T I O A 1

11 T I O A 2

TC1XC1S Signal Connected to XC1

00 T C L K 1

10 T I O A 0

TC2XC2S Signal Connected to XC2

00 T C L K 2

11 T I O A 1

TC Channel Control Register Register Name:TC_CCR Access Type:Write-only  CLKEN: Counter Clock Enable Command 0 = No effect. 1 = Enables the clock if CLKDIS is not 1.  CLKDIS: Counter Clock Disable Command 0 = No effect. 1 = Disables the clock.  SWTRG: Software Trigger Command 0 = No effect. 1 = A software trigger is performed: the counter is reset and clock is started. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210

TC Channel Mode Register: Capture Mode Register Name:TC_CMR Access Type:Read/write Reset Value: 0x0  TCCLKS: Clock Selection  CLKI: Clock Invert 0 = Counter is incremented on rising edge of the clock. 1 = Counter is incremented on falling edge of the clock.  BURST: Burst Signal Selection  LDBSTOP: Counter Clock Stopped with RB Loading 0 = Counter clock is not stopped when RB loading occurs. 1 = Counter clock is stopped when RB loading occurs.  LDBDIS: Counter Clock Disable with RB Loading 0 = Counter clock is not disabled when RB loading occurs. 1 = Counter clock is disabled when RB loading occurs. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 –––– LDRB LDRA 15 14 13 12 11 10 9 8 WAVE CPCTRG ––– ABETRG ETRGEDG 76543210 LDBDIS LDBSTOP BURST CLKI TCCLKS TCCLKS Clock Selected

000 A C L K / 2

001 A C L K / 8

010 A C L K / 3 2

101 X C 0

110 X C 1

111 X C 2

0 0 The clock is not gated by an external signal. 0 1 XC0 is ANDed with the selected clock. 1 0 XC1 is ANDed with the selected clock. 1 1 XC2 is ANDed with the selected clock.

 ETRGEDG: External Trigger Edge Selection  ABETRG: TIOA or TIOB External Trigger Selection 0 = TIOB is used as an external trigger. 1 = TIOA is used as an external trigger.  CPCTRG: RC Compare Trigger Enable 0 = RC Compare has no effect on the counter and its clock. 1 = RC Compare resets the counter and starts the counter clock.  WAVE 0 = Capture mode is enabled. 1 = Capture mode is disabled (waveform mode is enabled).  LDRA: RA Loading Selection  LDRB: RB Loading Selection ETRGEDG Edge 0 0 None 0 1 Rising edge 1 0 Falling edge 1 1 Each edge LDRA Edge 0 0 None 0 1 Rising edge of TIOA 1 0 Falling edge of TIOA 1 1 Each edge of TIOA LDRB Edge

00 N o n e

TC Channel Mode Register: Waveform Mode Register Name:TC_CMR Access Type:Read/write Reset Value: 0x0  TCCLKS: Clock Selection  CLKI: Clock Invert 0 = Counter is incremented on rising edge of the clock. 1 = Counter is incremented on falling edge of the clock.  BURST: Burst Signal Selection  CPCSTOP: Counter Clock Stopped with RC Compare 0 = Counter clock is not stopped when counter reaches RC. 1 = Counter clock is stopped when counter reaches RC.  CPCDIS: Counter Clock Disable with RC Compare 0 = Counter clock is not disabled when counter reaches RC. 1 = Counter clock is disabled when counter reaches RC. 31 30 29 28 27 26 25 24 BSWTRG BEEVT BCPC BCPB 23 22 21 20 19 18 17 16 ASWTRG AEEVT ACPC ACPA 15 14 13 12 11 10 9 8 WAVE CPCTRG – ENETRG EEVT EEVTEDG 76543210 CPCDIS CPCSTOP BURST CLKI TCCLKS TCCLKS Clock Selected 0 0 The clock is not gated by an external signal. 0 1 XC0 is ANDed with the selected clock. 1 0 XC1 is ANDed with the selected clock. 1 1 XC2 is ANDed with the selected clock.

 EEVTEDG: External Event Edge Selection  EEVT: External Event Selection Note: 1. If TIOB is chosen as the external event signal, it is configured as an input and no longer generates waveforms.  ENETRG: External Event Trigger Enable 0 = The external event has no effect on the counter and its clock. In this case, the selected external event only controls the TIOA output. 1 = The external event resets the counter and starts the counter clock.  CPCTRG: RC Compare Trigger Enable 0 = RC Compare has no effect on the counter and its clock. 1 = RC Compare resets the counter and starts the counter clock.  WAVE 0 = Waveform mode is disabled (Capture mode is enabled). 1 = Waveform mode is enabled.  ACPA: RA Compare Effect on TIOA  ACPC: RC Compare Effect on TIOA EEVTEDG Edge (1) 0 1 XC0 Output 1 0 XC1 Output 1 1 XC2 Output ACPA Effect 0 0 None

01 S e t

10 C l e a r

11 T o g g l e

 AEEVT: External Event Effect on TIOA  ASWTRG: Software Trigger Effect on TIOA  BCPB: RB Compare Effect on TIOB  BCPC: RC Compare Effect on TIOB  BEEVT: External Event Effect on TIOB AEEVT Effect

 BSWTRG: Software Trigger Effect on TIOB TC Counter Value Register Register Name:TC_CVR Access Type:Read-only  CV: Counter Value CV contains the counter value in real-time. BSWTRG Effect

Register Name:TC_RA Access Type:Read-only if WAVE = 0, Read/write if WAVE = 1 Reset Value: 0x0  RA: Register A RA contains the Register A value in real-time. TC Register B Register Name:TC_RB Access Type:Read-only if WAVE = 0, Read/write if WAVE = 1 Reset Value: 0x0  RB: Register B RB contains the Register B value in real-time. TC Register C Register Name:TC_RC Access Type:Read/write Reset Value: 0x0  RC: Register C RC contains the Register C value in real-time. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 RA 76543210 RA 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 RB 76543210 RB 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 RC 76543210 RC

Register Name:TC_SR Access Type:Read-only  COVFS: Counter Overflow Status 0 = No counter overflow has occurred since the last read of the Status Register. 1 = A counter overflow has occurred since the last read of the Status Register.  LOVRS: Load Overrun Status 0 = Load overrun has not occurred since the last read of the Status Register or WAVE = 1. 1 = RA or RB have been loaded at least twice without any read of the corresponding register since the last read of the Status Register if WAVE = 0.  CPAS: RA Compare Status 0 = RA compare has not occurred since the last read of the Status Register or WAVE = 0. 1 = RA compare has occurred since the last read of the Status Register if WAVE = 1.  CPBS: RB Compare Status 0 = RB compare has not occurred since the last read of the Status Register or WAVE = 0. 1 = RB compare has occurred since the last read of the Status Register if WAVE = 1.  CPCS: RC Compare Status 0 = RC compare has not occurred since the last read of the Status Register. 1 = RC compare has occurred since the last read of the Status Register.  LDRAS: RA Loading Status 0 = RA Load has not occurred since the last read of the Status Register or WAVE = 1. 1 = RA Load has occurred since the last read of the Status Register, if WAVE = 0.  LDRBS: RB Loading Status 0 = RB load has not occurred since the last read of the Status Register or WAVE = 1. 1 = RB load has occurred since the last read of the Status Register if WAVE = 0.  ETRGS: External Trigger Status 0 = External trigger has not occurred since the last read of the Status Register. 1 = External trigger has occurred since the last read of the Status Register.  CLKSTA: Clock Enabling Status 0 = Clock is disabled. 1 = Clock is enabled.  MTIOA: TIOA Mirror 0 = TIOA is low. If WAVE = 0, then TIOA pin is low. If WAVE = 1, then TIOA is driven low. 1 = TIOA is high. If WAVE = 0, then TIOA pin is high. If WAVE = 1, then TIOA is driven high.  MTIOB: TIOB Mirror 0 = TIOB is low. If WAVE = 0, then TIOB pin is low. If WAVE = 1, then TIOB is driven low. 1 = TIOB is high. If WAVE = 0, then TIOB pin is high. If WAVE = 1, then TIOB is driven high. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS

TC Interrupt Enable Register Register Name:TC_IER Access Type:Write-only  COVFS: Counter Overflow 0 = No effect. 1 = Enables the counter overflow interrupt.  LOVRS: Load Overrun 0 = No effect. 1: Enables the load overrun interrupt.  CPAS: RA Compare 0 = No effect. 1 = Enables the RA compare interrupt.  CPBS: RB Compare 0 = No effect. 1 = Enables the RB compare interrupt.  CPCS: RC Compare 0 = No effect. 1 = Enables the RC compare interrupt.  LDRAS: RA Loading 0 = No effect. 1 = Enables the RA load interrupt.  LDRBS: RB Loading 0 = No effect. 1 = Enables the RB load interrupt.  ETRGS: External Trigger 0 = No effect. 1 = Enables the external trigger interrupt. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS

TC Interrupt Disable Register Register Name:TC_IDR Access Type:Write-only  COVFS: Counter Overflow 0 = No effect. 1 = Disables the counter overflow interrupt.  LOVRS: Load Overrun 0 = No effect. 1 = Disables the load overrun interrupt if WAVE = 0.  CPAS: RA Compare 0 = No effect. 1 = Disables the RA compare interrupt if WAVE = 1.  CPBS: RB Compare 0 = No effect. 1 = Disables the RB compare interrupt if WAVE = 1.  CPCS: RC Compare 0 = No effect. 1 = Disables the RC compare interrupt.  LDRAS: RA Loading 0 = No effect. 1 = Disables the RA load interrupt if WAVE = 0.  LDRBS: RB Loading 0 = No effect. 1 = Disables the RB load interrupt if WAVE = 0.  ETRGS: External Trigger 0 = No effect. 1 = Disables the external trigger interrupt. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS

TC Interrupt Mask Register Register Name:TC_IMR Access Type:Read-only Reset Value: 0x0  COVFS: Counter Overflow 0 = The counter overflow interrupt is disabled. 1 = The counter overflow interrupt is enabled.  LOVRS: Load Overrun 0 = The load overrun interrupt is disabled. 1 = The load overrun interrupt is enabled.  CPAS: RA Compare 0 = The RA compare interrupt is disabled. 1 = The RA compare interrupt is enabled.  CPBS: RB Compare 0 = The RB compare interrupt is disabled. 1 = The RB compare interrupt is enabled.  CPCS: RC Compare 0 = The RC compare interrupt is disabled. 1 = The RC compare interrupt is enabled.  LDRAS: RA Loading 0 = The load RA interrupt is disabled. 1 = The load RA interrupt is enabled.  LDRBS: RB Loading 0 = The load RB interrupt is disabled. 1 = The load RB interrupt is enabled.  ETRGS: External Trigger 0 = The external trigger interrupt is disabled. 1 = The external trigger interrupt is enabled. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS

external processors or serial Flash. Figure 27. Serial Peripheral Interface Block Diagram Note: After a hardware reset, the SPI pins NPCS[3:1] are not enabled by default and must be programmed via the PIOA controller. Table 26. SPI Interface Pins

In master mode, the SPI controls data transfers to and from the slave(s) connected to the SPI bus. The SPI drives the chip select(s) to the slave(s) and the serial clock (SPCK). After enabling the SPI, a data transfer begins when the ARM core writes to the SP_TDR. For details on the SPI memory map, refer to Table 27 on page 127. Transmit and receive buffers maintain the data flow at a constant rate with a reduced requirement for high-priority interrupt servicing. When new data is available in the SP_TDR, the SPI continues to transfer data. If the SP_RDR has not been read before new data is received, the Overrun Error (OVRES) flag is set. The delay between the activation of the chip select and the start of the data transfer (DLYBS) as well as the delay between each data transfer (DLYBCT) can be programmed for each of the four external chip selects. All data transfer characteristics including the two timing values are pro- grammed in registers SP_CSR0 to SP_CSR. In master mode, the peripheral selection can be defined in two different ways: 1. Fixed peripheral select: The SPI exchanges data with only one peripheral. 2. Variable peripheral select: Data can be exchanged with more than one peripheral. Figure 28 and Figure 29 show the operation of the SPI in master mode. For details concerning the flag and control bits in these diagrams, see Table 27. Fixed Peripheral Select This mode is ideal for transferring memory blocks without the extra overhead in the transmit data register to deter- mine the peripheral. Fixed peripheral select is activated by setting bit PS to zero in SP_MR. The peripheral is defined by the PCS field, also in SP_MR. This option is only available when the SPI is programmed in master mode. Variable Peripheral Select Variable peripheral select is activated by setting bit PS to one. The PCS field in SP_TDR is used to select the desti- nation peripheral. The data transfer characteristics are changed when the selected peripheral changes according to the associated chip select register. The PCS field in the SP_MR has no effect. This option is only available when the SPI is programmed in master mode. Chip Selects The chip select lines are driven by the SPI only if it is pro- grammed in master mode. These lines are used to select the destination peripheral. The PCSDEC field in SP_MR selects only one peripheral. If variable peripheral select is active, the chip select signals are defined for each transfer in the PCS field in SP_TDR. Chip select signals can thus be defined independently for each transfer. If fixed peripheral select is active, chip select signals are defined for all transfers by the field PCS in SP_MR. If a transfer with a new peripheral is necessary, the software must wait until the current transfer is completed, then change the value of PCS in SP_MR before writing new data in SP_TDR. The value on the NPCS pins at the end of each transfer can be read in the SP_RDR. By default, all NPCS signals are high (equal to one) before and after each transfer. Mode Fault Detection A mode fault is detected when the SPI is programmed in master mode and a low level is driven by an external mas- ter on the NPCS0/NSS signal. When a mode fault is detected, the MODF bit in the SP_SR is set until the SP_SR is read and the SPI is disabled until re-enabled by bit SPIEN in the SP_CR.

Figure 28. Functional Flow Diagram in Master Mode

Figure 29. SPI in Master Mode

before receiving the serial clock from an external master. registers are not used in slave mode. Figure 30. SPI in Slave Mode

Figure 33. Programmable Delays (DLYBCS, DLYBS and DLTBCT) clock/data relationship between master and slave devices. SPI Base Address: 0xFF020000. Table 27. SPI Memory Map

1 = Enables the SPI to transfer and receive data. All pins are set in input mode and no data is received or transmitted. If a transfer is in progress, the transfer is finished before the SPI is disabled. If both SPIEN and SPIDIS are equal to one when the control register is written, the SPI is disabled. A software-triggered hardware reset of the SPI interface is performed. Table 27. SPI Memory Map (Continued)

Register Name:SP_MR Access Type:Read/write Reset Value:0x0  MSTR: Master/Slave Mode 0 = SPI is in slave mode. 1 = SPI is in master mode. MSTR configures the SPI interface for either master or slave mode operation.  PS: Peripheral Select 0 = Fixed peripheral select 1 = Variable peripheral select  PCSDEC: Chip Select Decode 0 = The chip selects are directly connected to a peripheral device. 1 = The four chip select lines are connected to a 4-to-16-bit decoder. When PCSDEC equals one, up to one chip select signal can be generated with the four lines using an external 4-to-16-bit decoder. The Chip Select Register defines the characteristics of the 16 chips selected according to the following rules: SP_CSR0 defines peripheral chip select signals 0 to 3. SP_CSR1 defines peripheral chip select signals 4 to 7. SP_CSR2 defines peripheral chip select signals 8 to 11. SP_CSR3 defines peripheral chip select signals 12 to 15.  MCK32: Clock Selection 0 = SPI master clock equals ACLK. 1 = SPI master clock equals ACLK/32.  LLB: Local Loopback Enable 0 = Local loopback path disabled. 1 = Local loopback path enabled. LLB controls the local loopback on the data serializer for testing in master mode only. 31 30 29 28 27 26 25 24 DL YBCS 23 22 21 20 19 18 17 16 –––– PCS 15 14 13 12 11 10 9 8 76543210 LLB ––– MCK32 PCSDEC PS MSTR

 PCS: Peripheral Chip Select This field is only used if fixed peripheral select is active (PS=0). If PCSDEC=0: PCS = xxx0 NPCS[3:0] = 1110 PCS = xx01 NPCS[3:0] = 1101 PCS = x011 NPCS[3:0] = 1011 PCS = 0111 NPCS[3:0] = 0111 PCS = 1111 forbidden (no peripheral is selected) (x = don’t care) If PCSDEC=1: NPCS[3:0] output signals = PCS  DLYBCS: Delay Between Chip Selects This field defines the delay from NPCS inactive to the activation of another NPCS. The DLYBCS time guarantees non- overlapping chip selects and solves bus contentions in case of peripherals with long data float times. If DLYBCS equals zero, one SPI Master Clock period will be inserted by default. Otherwise, the following equation determines the delay: SPI Receive Data Register Register Name:SP_RDR Access Type:Read-only Reset Value:0x0  RD: Receive Data Data received by the SPI interface is stored in this register right-justified. Unused bits read zero.  PCS: Peripheral Chip Select Status In master mode only, these bits indicate the value on the NPCS pins at the end of a transfer. Otherwise, these bits read as zero. NPCS_to_SPCK_Delay DLYBCS SPI_Master_Clock_Period×= 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 –––– PCS 15 14 13 12 11 10 9 8 RD 76543210 RD

SPI Transmit Data Register Register Name:SP_TDR Access Type:Write-only Reset Value:–  TD: Transmit Data Data that is to be transmitted by the SPI interface is stored in this register. Information to be transmitted must be written to the transmit data register in a right-justified format.  PCS: Peripheral Chip Select This field is only used if variable peripheral select is active (PS = 1). If PCSDEC = 0: PCS = xxx0 NPCS[3:0] = 1110 PCS = xx01 NPCS[3:0] = 1101 PCS = x011 NPCS[3:0] = 1011 PCS = 0111 NPCS[3:0] = 0111 PCS = 1111 forbidden (no peripheral is selected) (x = don’t care) If PCSDEC = 1: NPCS[3:0] output signals = PCS 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 –––– PCS 15 14 13 12 11 10 9 8 TD 76543210 TD

Register Name: SP_SR Access Type: Read-only Reset Value: 0x0  RDRF: Receive Data Register Full 0 = No data has been received since the last read of SP_RDR. 1 = Data has been received and the received data has been transferred from the serializer to SP_RDR since the last read of SP_RDR.  TDRE: Transmit Data Register Empty 0 = Data has been written to SP_TDR and not yet transferred to the serializer. 1 = The last data written in the Transmit Data Register has been transferred to the serializer. TDRE equals zero when the SPI is disabled or at reset. The SPI enable command sets this bit to one.  MODF: Mode Fault Error 0 = No mode fault has been detected since the last read of SP_SR. 1 = A mode fault occurred since the last read of the SP_SR.  OVRES: Overrun Error Status 0 = No overrun has been detected since the last read of SP_SR. 1 = An overrun has occurred since the last read of SP_SR. An overrun occurs when SP_RDR is loaded at least twice from the serializer since the last read of the SP_RDR.  SPENDTX: SPI End of Transmission 0 = No end of data transmission detected. 1 = End of data transmission detected.  SPENDRX: SPI End of Reception 0 = No end of data reception detected. 1 = End of data reception detected.  SPIENS: SPI Enable Status 0 = SPI is disabled. 1 = SPI is enabled. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 –– SPENDRX SPENDTX OVRES MODF TDRE RDRF

SPI Interrupt Enable Register Register Name:SP_IER Access Type:Write-only  RDRF: Receive Data Register Full Interrupt Enable 0 = No effect. 1 = Enables the receiver data register full interrupt.  TDRE: SPI Transmit Data Register Empty Interrupt Enable 0 = No effect. 1 = Enables the transmit data register empty interrupt.  MODF: Mode Fault Error Interrupt Enable 0 = No effect. 1 = Enables the mode fault interrupt.  OVRES: Overrun Error Interrupt Enable 0 = No effect. 1 = Enables the overrun error interrupt. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 –––– OVRES MODF TDRE RDRF

SPI Interrupt Disable Register Register Name:SP_IDR Access Type:Write-only  RDRF: Receive Data Register Full Interrupt Disable 0 = No effect. 1 = Disables the receiver data register full interrupt.  TDRE: Transmit Data Register Empty Interrupt Disable 0 = No effect. 1 = Disables the transmit data register empty interrupt.  MODF: Mode Fault Error Interrupt Disable 0 = No effect. 1 = Disables the mode fault error interrupt.  OVRES: Overrun Error Interrupt Disable 0 = No effect. 1 = Disables the overrun error interrupt. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 –––– OVRES MODF TDRE RDRF

SPI Interrupt Mask Register Register Name:SP_IMR Access Type:Read-only Reset Value: 0x0  RDRF: Receive Data Register Full Interrupt Mask 0 = Receive data register full interrupt is disabled. 1 = Receive data register full interrupt is enabled.  TDRE: Transmit Data Register Empty Interrupt Mask 0 = Transmit data register empty interrupt is disabled. 1 = Transmit data register empty interrupt is enabled.  MODF: Mode Fault Error Interrupt Mask 0 = Mode fault error interrupt is disabled. 1 = Mode fault error interrupt is enabled.  OVRES: Overrun Error Interrupt Mask 0 = Overrun error interrupt is disabled. 1 = Overrun error interrupt is enabled. A one in any of the bits unmasks the relative interrupt. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 –––– OVRES MODF TDRE RDRF

SPI Receive Pointer Register Register Name:SP_RPR Access Type:Read/write Reset Value:0x0  RXPTR: Receive Pointer RXPTR must be loaded with the address of the receive buffer. SPI Receive Counter Register Register Name:SP_CPR Access Type:Read/write Reset Value:0x0  RXCTR: Receive Counter Register RXCTR must be loaded with the size of the receive buffer. 0 = Stop peripheral data transfer 1 - 4294967295 = Start peripheral data transfer if RDRF is active. 31 30 29 28 27 26 25 24 RXPTR 23 22 21 20 19 18 17 16 RXPTR 15 14 13 12 11 10 9 8 RXPTR 76543210 RXPTR 31 30 29 28 27 26 25 24 RXCTR 23 22 21 20 19 18 17 16 RXCTR 15 14 13 12 11 10 9 8 RXCTR 76543210 RXCTR

SPI Transmit Pointer Register Register Name:SP_TPR Access Type:Read/write Reset Value:0x0  TXPTR: Transmit Pointer Register TXPTR must be loaded with the address of the transmit buffer. SPI Transmit Counter Register Register Name:SP_TCR Access Type:Read/write Reset Value:0x0  TXCTR: Transmit Counter Register TXCTR must be loaded with the size of the receive buffer. 0 = Stop peripheral data transfer 1 - 4294967295 = Start peripheral data transfer if TDRE is active. 31 30 29 28 27 26 25 24 TXPTR 23 22 21 20 19 18 17 16 TXPTR 15 14 13 12 11 10 9 8 TXPTR 76543210 TXPTR 31 30 29 28 27 26 25 24 TXCTR 23 22 21 20 19 18 17 16 TXCTR 15 14 13 12 11 10 9 8 TXCTR 76543210 TXCTR

Register Name:SP_CSR0 Access Type:Read/write Reset Value:0x0  CPOL: Clock Polarity 0 = The inactive state value of SPCK is logic level zero. 1 = The inactive state value of SPCK is logic level one. CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce a desired clock/data relationship between master and slave devices.  NCPHA: Clock Phase 0 = Data is changed on the leading edge of SPCK and captured on the following edge of SPCK. 1 = Data is captured on the leading edge of SPCK and changed on the following edge of SPCK. NCPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. NCPHA is used with CPOL to produce a desired clock/data relationship between master and slave devices.  BITS: Bits Per Transfer The BITS field determines the number of data bits transferred. Reserved values should not be used. 31 30 29 28 27 26 25 24 DL YBCT 23 22 21 20 19 18 17 16 DL YBS 15 14 13 12 11 10 9 8 SCBR 76543210 BITS –– NCPHA CPOL BITS[3:0] Bits per Transfer BITS[3:0] Bits per Transfer 0000 8 1000 16 0001 9 1001 Reserved 0010 10 1010 Reserved 0011 11 1011 Reserved 0100 12 1100 Reserved 0101 13 1101 Reserved 0110 14 1110 Reserved 0111 15 1111 Reserved

 SCBR: Serial Clock Baud Rate In master mode, the SPI interface uses a modulus counter to derive the SPCK baud rate from the SPI master clock (selected between ACLK and ACLK/32). The baud rate is selected by writing a value from 2 to 255 in the field SCBR. The following equation determines the SPCK baud rate: Giving SCBR a value of zero or one disables the baud rate generator. SPCK is disabled and assumes its inactive state value. No serial transfers may occur. At reset, baud rate is disabled.  DLYBS: Delay Before SPCK This field defines the delay from NPCS valid to the first valid SPCK transition. When DLYBS equals zero, the NPCS valid to SPCK transition is 1/2 the SPCK clock period. Otherwise, the following equation determines the delay:  DLYBCT: Delay Between Consecutive Transfers This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select. The delay is always inserted after each transfer and before removing the chip select if needed. When DLYBCT equals zero, a delay of four SPI master clock periods is inserted. Otherwise, the following equation determines the delay: SPCK_Baud_Rate SPI_Master_Clock_Frequency 2S C B R NPCS_to_SPCK_Delay DLYBS SPI_Master_Clock_Period×= Delay_after_Transfer 32 DLYBCT× SPI_Master_Clock_Period×=

(WD_RESET as shown in Figure 34). signal for a duration of eight ACLK cycles. seconds with a 24 MHz system clock. control bits are written (the same write access). Figure 34. Watchdog Timer Block Diagram

Name: WD_OMR Access: Read/write Reset Value:0  WDEN: Watchdog Enable 0 = Watchdog is disabled and does not generate any signals. 1 = Watchdog is enabled and generates enabled signals.  RSTEN: Reset Enable 0 = Generation of an internal reset by the watchdog is disabled. 1 = When overflow occurs, the watchdog generates an internal reset.  IRQEN: Interrupt Enable 0 = Generation of an interrupt by the watchdog is disabled. 1 = When overflow occurs, the watchdog generates an interrupt.  EXTEN: External Signal Enable 0 = Generation of a pulse on the pin NWDOVF by the watchdog is disabled. 1 = When an overflow occurs, a pulse on the pin NWDOVF is generated.  OKEY: Overflow Access Key Used only when writing WD_OMR. OKEY is read as 0. 0x234 = Write access in WD_OMR is allowed. Other value = Write access in WD_OMR is prohibited. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 OKEY 76543210 OKEY EXTEN IRQEN RSTEN WDEN

Name: WD_CMR Access: Read/write Reset Value:0  WDCLKS: Clock Selection  HPCV: High Preload Counter Value Counter is preloaded when watchdog counter is restarted with bits 0 to 11 set (FFF) and bits 12 to 15 equaling HPCV.  CKEY: Clock Access Key Used only when writing WD_CMR. CKEY is read as 0. 0x06E: Write access in WD_CMR is allowed. Other value: Write access in WD_CMR is prohibited. WD Control Register Name: WD_CR Access: Write-only  RSTKEY: Restart Key 0xC071 = Watchdog counter is restarted. Other value = No effect. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 CKEY 76543210 CKEY – HPCV WDCLKS WDCLKS Clock Selected

00 A C L K / 8

01 A C L K / 3 2

Name: WD_SR Access: Read-only  WDOVF: Watchdog Overflow 0 = No watchdog overflow. 1 = A watchdog overflow has occurred since the last restart of the watchdog counter or since internal or external reset. WD Enabling Sequence To enable the Watchdog Timer the sequence is as follows: 1. Disable the Watchdog by clearing the bit WDEN: Write 0x2340 to WD_OMR This step is unnecessary if the WD is already disabled (reset state). 2. Initialize the WD Clock Mode Register: Write 0x373C to WD_CMR (HPCV = 15 and WDCLKS = MCK/8) 3. Restart the timer: Write 0xC071 to WD_CR 4. Enable the watchdog: Write 0x2345 to WD_OMR (interrupt enabled) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210

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