AT697F

AT697F ATMEL | Alldatasheet

Document overview

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Technical content

Features

• SPARC V8 High Performance Low-power 32-bit Architecture – 8 Register Windows
• Advanced Architecture: – On-chip Amba Bus – 5 Stage Pipeline – 16 kbyte Multi-sets Data Cache – 32 kbyte Multi-sets Instruction Cache
• On-chip Peripherals: – Memory Interface PROM Controller SRAM Controller SDRAM Controller –T i m e r s Two32-bit Timers Watchdog 32-bitTimer – Two 8-bit UARTs – Interrupt Controller with 8 External Programmable Inputs – 32 Parallel I/O Interface – 33MHz PCI Interface Compliant with 2.2 PCI Specification
• Integrated 32/64-bit IEEE 754 Floating-point Unit
• Fault Tolerance by Design – Full Triple Modular Redundancy (TMR) – EDAC Protection – Parity Protection
• Debug and Test Facilities – Debug Support Unit (DSU) for Trace and Debug – IEEE 1149.1 JTAG Interface – Four Hardware Watchpoints
• 8 and 40-bit boot-PROM Interface Possibilities
• Operating range –V o l t a g e s 3.3V +/- 0.30V for I/O 1.8V +/- 0.15V for Core – Temperature -55°C to 125°C
• Clock: 0MHz up to 100MHz
• Power consumption: 1W at 100MHz
• Performance: – 86MIPS (Dhrystone 2.1) – 23MFLOPS (Whetstone)
• Radiation Performance – Tested up to a total dose of 300Krads (Si) according to the MIL-STD883 method 1019 – SEU error rate better than 1 E-5 error/device/day – No Single Event Latchup below a LET threshold of 70 MeV.cm²/mg
• Package MCGA349 and MQFPF256
• Mass: 9g
• Development Kit Including – AT697F Evaluation Board –A T 6 9 7 F S a m p l e Rad-Hard 32 bit SPARC V8 Processor AT697F Advance Information 7703C–AERO–6/09

7703C–AERO–6/09 AT697F ADVANCE INFORMATION Description The AT697F is a highly integrated, high-performance 32-bit RISC embedded processor based on the SPARC V8 architecture. The implem entation is based on the European Space Agency (ESA) LEON2 fault tolerant model. By executing powerful instructions in a single clock cycle, the AT697F achieves throughputs approaching 1MIPS pe r MHz, allowing the system designer to optimize power consumption versus processing speed. The AT697F is designed to be used as a building block in computers for on-board embedded real-time applications. It brings up-to-date functionality and performance for space application. The AT697F only requires memory and application specific peripherals to be added to form a complete on-board computer. The AT697F contains an on-chip Integer Unit (IU), a Floating Point Unit (FPU), separate instruc- tion and data caches, hardware multiplier and divi der, interrupt controller, debug support unit with trace buffer, two 32-bit timers, Parallel an d Serial interfaces, a Watchdog, a PCI Interface and a flexible Memory Controller. The design is highly testable with the support of a Debug Sup- port Unit (DSU) and a boundary scan through JTAG interface. An Idle mode holds the processor pipeline and al lows Timer/Counter, Serial ports and Interrupt system to continue functioning. The processor is manufactured using the Atmel 0. 18 µm CMOS process. It has been especially designed for space, by implementing on-chip concurrent transient and permanent error detec - tion and correction. The AT697F is pinout compatible with the AT697E. Refer to section “Differences between AT697F and AT697E”, page 146“ for detailed description of the differences between AT697F and AT697FE.

Figure 1. AT697F Block Diagram

Table 1. AT6 97F MCGA349 pinout

1 VDD18 VSS18 PIO[6] PIO[1] RAMS*[1]

8 CB[6] CB[4] D[2] VCC33 CB[7] CB[2] PIO[8]

10 D[8] D[5] VCC33 VSS33 Reserved D[10] D[4]

13 D[21] D[23] VCC33 VCC33 VSS33 VSS33 A[1]

18 VSS18 VDD18 VCC33 A[0] A[4] A[8]

19 VDD18 VSS18 A[2] VSS33 A[9]

Table 2. AT697F MCGA349 pinout

1 RAMOE*[0] VSS33 READ DSUACT BEXC* VCC33 SDWE*

2 RAMOE*[2] ROMS*[1] TCK DSURX SDCLK VSS33 PCI_CLK

3 VCC33 ROMS*[0] TDI DSUTX DSUBRE SDDQM[1] VSS33

6 RWE*[3] RWE*[2] IOS* VSS33 VSS33 GNT* A/D[24]

8 RAMS*[3] VCC33 OE* BRDY* VCC33 A/D[21] A/D[18]

9 CB[5] PIO[14] VSS33 SDRAS* A/D[22] A/D[16] A/D[17]

12 D[24] A[14] A[26] VDD_PLL AGNT*[3] A/D[1] A/D[8]

14 A[10] VCC33 A[27] LOCK SKEW[1] A/D[0] AGNT*[1]

19 A[15] A[20] A[25] ERROR* SKEW[0] VCC33 AREQ*[1]

Table 3. AT697F MCGA349 pinout - Advanced Information

1 REQ* VSS18 VDD18

3 PCI_RST* A/D[31] VSS18 VDD18 VDD18

7 SYSEN* VSS33 VCC33 C/BE*[3] A/D[23]

8 VSS33 VSS33 FRAME* A/D[20] A/D[19]

10 PCI_LOCK* DEVSEL* STOP* VCC33 VCC33

11 VSS33 VCC33 VSS33 C/BE*[1] SERR*

13 VCC33 A/D[7] A/D[10] VSS33 VSS33

14 VCC33 VSS33 C/BE*[0] A/D[4] A/D[6]

17 VCC33 AGNT*[0] VSS18 VDD18 VDD18

19 AREQ*[0] VSS18 VDD18

1. N.C. refers to unconnected pins

7703C–AERO–6/09 AT697F ADVANCE INFORMATION pin number pin name pin number pin name pin number pin name

1 VCC33 31 TCK 61 PIO[1]

2 PCI_REQ* 32 TMS 62 PIO[2]

3 PCI_GNT* 33 VSS 63 PIO[3]

4 PCI_CLK 34 TDI 64 PIO[4]

5 PCI_RST* 35 TDO 65 PIO[5]

6 SDCS*[0] 36 WRITE* 66 PIO[6]

7 VSS 37 READ 67 VCC33

8 VDD18 38 OE* 68 PIO[7]

9 SDCS*[1] 39 IOS* 69 PIO[8]

10 SDWE* 40 VCC33 70 PIO[9]

11 SDRAS* 41 ROMS*[0] 71 VSS

12 VSS 42 ROMS*[1] 72 VDD18

13 VSS 43 RWE*[0] 73 PIO[10]

14 SDCAS* 44 RWE*[1] 74 PIO[11]

15 VCC33 45 RWE*[2] 75 Reserved

16 SDDQM[0] 46 RWE*[3] 76 PIO[12]

17 SDDQM[1] 47 RAMOE*[0] 77 PIO[13]

18 SDDQM[2] 48 RAMOE*[1] 78 PIO[14]

19 SDDQM[3] 49 RAMOE*[2] 79 PIO[15]

20 SDCLK 50 RAMOE*[3] 80 VCC33

21 BRDY* 51 RAMOE*[4] 81 CB[0]

22 BEXC* 52 RAMS*[0] 82 CB[1]

23 VSS 53 VCC33 83 CB[2]

24 VSS 54 RAMS*[1] 84 CB[3]

25 DSUEN 55 RAMS*[2] 85 VCC33

26 DSUTX 56 RAMS*[3] 86 CB[4]

27 DSURX 57 VSS 87 CB[5]

28 DSUBRE 58 VDD18 88 CB[6]

29 DSUACT 59 RAMS*[4] 89 CB[7]

30 TRST 60 PIO[0] 90 D[0]

Table 5. AT697F QFP256 pinout

91 VCC33 124 D[25] 157 A[19]

92 D[1] 125 D[26] 158 A[20]

93 D[2] 126 D[27] 159 A[21]

94 D[3] 127 D[28] 160 A[22]

95 D[4] 128 D[29] 161 VSS

96 D[5] 129 D[30] 162 VCC33

97 D[6] 130 VCC33 163 A[23]

98 Reserved 131 D[31] 164 A[24]

100 D[7] 133 A[0] 166 A[26]

101 D[8] 134 A[1] 167 A[27]

102 D[9] 135 VSS 168 WDOG*

103 D[10] 136 VDD18 169 ERROR*

104 D[11] 137 A[2] 170 VCC33

105 D[12] 138 A[3] 171 RESET*

106 VCC33 139 A[4] 172 Reserved

107 D[13] 140 VCC33 173 LOCK

108 D[14] 141 A[5] 174 SKEW[1]

109 D[15] 142 A[6] 175 SKEW[0]

110 D[16] 143 A[7] 176 BYPASS

111 D[17] 144 A[8] 177 VSS_PLL

113 D[18] 146 A[10] 179 VDD_PLL

114 VCC33 147 VCC33 180 CLK

115 D[19] 148 A[11] 181 VCC33

116 D[20] 149 A[12] 182 PCI_AREQ*[3]

117 D[21] 150 A[13] 183 PCI_AGNT*[3]

118 D[22] 151 A[14] 184 PCI_AREQ*[2]

119 D[23] 152 A[15] 185 VSS

120 D[24] 153 A[16] 186 VDD18

121 VSS 154 VCC33 187 PCI_AGNT*[2]

122 VDD18 155 A[17] 188 PCI_AREQ*[1]

123 VCC33 156 A[18] 189 VCC33

Table 6. AT697E MQFP256 pinout

190 PCI_AGNT*[1] 213 A/D[12] 236 A/D[19]

191 PCI_AREQ*[0] 214 A/D[13] 237 SYSEN*

192 PCI_AGNT*[0] 215 A/D[14] 238 A/D[20]

193 A/D[0] 216 A/D[15] 239 VCC33

194 VCC33 217 VCC33 240 A/D[21]

196 A/D[2] 219 PAR 242 A/D[23]

197 A/D[3] 220 SERR* 243 IDSEL

198 A/D[4] 221 PERR* 244 C/BE*[3]

199 VSS 222 VCC33 245 VCC33

200 VDD18 223 PCI_LOCK* 246 A/D[24]

201 VCC33 224 STOP* 247 A/D[25]

202 A/D[5] 225 DEVSEL* 248 A/D[26]

203 A/D[6] 226 TRDY* 249 VSS

204 A/D[7] 227 VCC33 250 VDD18

205 C/BE*[0] 228 IRDY* 251 A/D[27]

206 VSS 229 FRAME* 252 VCC33

207 VCC33 230 VSS 253 A/D[28]

210 A/D[10] 233 VCC33 256 A/D[31]

212 VCC33 235 A/D[18]

1. N.C. refers to unconnected pins

7703C–AERO–6/09 AT697F ADVANCE INFORMATION Pin Description ATMEL Convention ‘*’ attached to a signal (e.g OE*) designate an active-low signal. When a bit of a register is writen in C-like style (e.g MCFG2JRAMWWS) it must be read as the RAMWWS bit in the register MCFG2. IU and FPU Signals A[27:0] - Address bus (output) A[27:0] bus carries the addresses during accesses to external memory. When access to cache memory is performed, the addres s of the last external memory access remains driven on the address bus. D[31:0] - Data bus (bi-directional) D[31:0] bus carries the data during accesses to memory. The processor automatically config - ures the bus as output and drive the lines during write transactions. During accesses to 8-bit areas, only D[31:24] are used. CB[7:0] - Check bits (bi-directional) CB[6:0] bus carries the EDAC checkbits during memory accesses. CB[7] (1) takes the value of tcb[7] in the error control register. Processor only drives CB[7:0] during write transactions to areas programmed to be EDAC protected. Note: 1. CB[7] is implemented to enable programming of flash memories. When only 7 bits are useful for EDAC protection, 8 are needed for programming. Memory Interface Signals General management OE* - Output enable (output) This active low output is asserted during read transactions on the memory bus. BRDY* - Bus ready (input) When driven low, this input indicates to the pr ocessor that the current memory access can be terminated on the next rising clock edge. When driven high, this input indicates to the processor that it must wait and not end the current access. READ - Read transaction (output) This active high output is asserted during read transactions on the memory bus. WRITE* - Write enable (output) This active low output provides a write strobe during write transactions on the memory bus. PROM ROMS*[1:0] - PROM chip-select (output) These active low outputs provide the chip-select signal for the PROM area. ROMS*[0] is asserted when the lower half of the PROM area is accessed (0 - 0x10000000), while ROMS*[1] is asserted for the upper half. SRAM RAMOE*[4:0] - RAM output enable (output) These active low signals provide an individual output enable for each RAM bank. RAMS*[4:0] - RAM chip-select (output) These active low outputs provide the chip-select signals for each RAM bank. RWE* [3:0] - RAM write enable (output) These active low outputs provide individual wr ite strobes for each by te. RWEN[0] controls D[31:24], RWEN[1] controls D[23:16], etc. I/O IOS* - I/O select (output)

7703C–AERO–6/09 AT697F ADVANCE INFORMATION This active low output is the chip-select signal for the memory mapped I/O area. SDRAM Interface SDCLK - SDRAM clock (output) SDRAM clock provides the SDRAM interface clock reference. SDCAS* - SDRAM column address strobe (output) This active low signal provides a common CAS for all SDRAM devices. SDCS*[1:0] - SDRAM chip select (output) These active low outputs provide the chip select signals for the two SDRAM banks. SDDQM[3:0] - SDRAM data mask (output) These active low outputs provide the DQM signals for both SDRAM banks. SDRAS*- SDRAM row address strobe (output) This active low signal provides a common RAS for all SDRAM devices. SDWE* - SDRAM write strobe (output) This active low signal provides a common write strobe for all SDRAM devices. System Signals CLK - Processor clock (input) The CLK input provides the main processor clock reference. RESET* - Processor reset (input) When asserted, this active low input will reset the processor and all on-chip peripherals. WDOG* - Watchdog time-out (open-drain output) This active low output is asserted when the watchdog expires. BEXC* - Bus exception (input) This active low input is sampled simultaneously with the data during accesses on the memory bus. If asserted, a memory error will be generated. ERROR* - Processor error (open-drain output) This active low output is asserted when the processor has entered error state and is halted. This happens when traps are disabled and a synchronous (un-maskable) trap occurs. PIO[15:0] - Parallel I/O port (bi-directional) These bi-directional signals can be used as inputs or outputs to control external devices. BYPASS - PLL bypass (input) When driven to VCC, this active high input set the PLL in bypass mode. The device is then directly clocked by the external clock. When grounded, the device is clocked through the PLL. SKEW[1:0] - Clock tree skew (input) These input signals configurate the programmable skew on the triplicated clock trees. LOCK - PLL lock (output) This active high output is as serted when the PLL output (internal node) is locked at the fre - quency corresponding to four times the input command. DSU Signals DSUACT - DSU active (output) This active high output is asserted when the processor is in debug mode and controlled by the DSU. DSUBRE - DSU break enable (input)

7703C–AERO–6/09 AT697F ADVANCE INFORMATION A low-to-high transition on this active high in put will generate break condi tion and put the pro - cessor in debug mode. DSUEN - DSU enable (input) The active high input enables the DSU unit. If de-asserted, the DSU trace buffer will continue to operate but the processor will not enter debug mode. DSURX - DSU receiver (input) This active high input provides the data to the DSU communication link receiver DSUTX - DSU transmitter (output) This active high input provides the output from the DSU communication link transmitter. JTAG TCK - Test Clock (input) Used to clock serial data into boundary scan latc hes and control sequence of the test state machine. TCK can be asynchronous with CLK. TMS - Test Mode select (input) Primary control signal for the state machine. Synchronous with TCK. A sequence of values on TMS adjusts the current state of the TAP. TDI - Test data input (input) Serial input data to the boundary scan latches. Synchronous with TCK TDO - Test data output (output) Serial output data from the boundary scan latches. Synchronous with TCK TRST - Test Reset (input) Resets the test state machine. Can be as ynchronous with TCK. Shall be grounded for end application. PCI Arbiter AREQ*[3:0] - PCI bus request (Input) When asserted, these active low inputs indicate that a PCI agent is requesting the bus. AGNT*[3:0] - PCI bus grant (Output) When asserted, these active low outputs indicate that a PCI agent is granted the PCI bus.

7703C–AERO–6/09 AT697F ADVANCE INFORMATION PCI interface A/D[31:0] - PCI Address Data (bi-directional) Address and Data are multiplexed on the same PCI pins. During the address phase, A/D[31::00] contain a physical address (32 bits). For I/O, this is a byte address; for configuration and memory, it is a DWORD address. During data phases, A/D[07::00] contain the least significant byte and A/D[31::24] contain the most significant byte. C/BE[3:0]* - PCI Bus Command and Byte Enables (bi-directional) During the address phase of a transaction, C/BE[3::0]* define the bus command. During the data phase, C/BE[3::0]* are used as Byte Enables. T he Byte Enables are valid for the entire data phase. PAR - Parity (bi-directional) The number of "1"s on A/D[31::00], C/BE[3::0]*, and PAR equals an even number FRAME* - Cycle Frame (bi-directional) It is driven by the current master to indicate the beginning and duration of an access. FRAME* is asserted to indicate a bus transaction is beginni ng. While FRAME* is as serted, data transfers continue. When FRAME* is deasserted, the tr ansaction is in the final data phase or has completed. IRDY* - Initiator Ready (bi-directional) IRDY* indicates the initiating ag ent’s ability to complete the current data phas e of the transac - tion. IRDY* is used in conjunction with TRDY*. Du ring a write, IRDY* indicates that valid data is present on A/D[31::00]. During a read, it indicates the master is prepared to accept data. TRDY* - Target Ready (bi-directional) TRDY* indicates the target agent’s (selected device’s) ability to complete the current data phase of the transaction. TRDY* is used in conjunction with IRDY*. During a read, TRDY* indicates that valid data is present on AD[31::00]. During a write, it indicates the target is prepared to accept data. STOP* - Stop (bi-directional) STOP* indicates the current target is requesting the master to stop the current transaction. PCI_LOCK* - Lock (bi-directional) PCI_LOCK* indicates an atomic operation to a brid ge that may require multiple transactions to complete. IDSEL - Initialization Device Select (input) Initialization Device Select is used as a chip select during configuration read and write transactions. DEVSEL* - Device Select (bi-directional) When actively driven, indicates the driving device has decoded its address as the target of the current access. As an input, DEVSEL* indicates whet her any device on the bus has been selected. REQ* - PCI bus request (output) REQ* indicates to the arbiter that this agent desir es use of the bus. This is a point-to-point sig - nal. Every master has its own REQ* which must be tri-stated while RST* is asserted. GNT* - PCI Bus Grant (input) GNT* indicates to the agent that access to the bus has been granted. This is a point-to-point sig- nal. Every master has its own GNT* which must be ignored while RST* is asserted. PCI_CLK - PCI clock (input)

7703C–AERO–6/09 AT697F ADVANCE INFORMATION PCI_CLK provides timing for all transactions on PCI. All other PCI signals, except RST*, are sampled on the rising edge of PCI_CLK and all other timing parameters are defined with respect to this edge. RST* - PCI Reset (input) Reset is used to bring PCI-specific registers, sequencers, and signals to a consistent state. PERR* - Parity Error (bi-directional) Parity Error is only for the reporting of data par ity errors during all PCI transactions except a Special Cycle. The PERR* pin is sustained tri-state and must be driven active by the agent receiving data two clocks following the data when a data parity error is detected. The minimum duration of PERR* is one clock for each data phase that a data parity error is detected. SERR* - System Error (bi-directional) System Error is for reporting address parity errors, data parity errors on the special cycle com - mand, or any other system error where the result will be catastrophic. If an agent does not want a non-maskable interrupt (NMI) to be generated, a different reporting mechanism is required. SYSEN* - PCI Host (input) This active low input specifies the configuration of the device. At boot-up time, if SYSEN* is sam- pled at a low level, the device is configured as the host of the PCI bus. If SYSEN* is sampled at a high level, the device is configured as a satellite.

culations, control peripherals, and handle interrupts. The AT697F CPU core is based on the LEON2 architecture. Figure 2. Blo ck diagram of the AT697F Integer Unit architecture applications by including fault tolerance features. five-stage instruction pipeline that permits parallel execution of multiple instructions.

• Instruction Fetch: If the instru ctio n cache is enabled, the instruction is fetched from the instruction cache. Otherwise, the fetch is forwarded to the memory controller. The instruction is valid at the end of this stage and is latched inside the IU.
• Decode: The instruction is decoded and the op e rands are read. Operands may come from the register file or from internal data bypasses. CALL and Branch target addresses are generated in this stage.
• Execute: ALU, logical, and shift operations are performed. For memory operations and for JMPL/RET T, the address is generated.
• Memory: Data cache is accessed. For cache re ads, the data will be valid by the end of this stage, at which point it is aligned as appropriate. Store data read out in the Execute stage is written to the data cache at this time.
• Write: The result of any ALU, lo gical, shift, or cache read operations re written back to the register file. All five stages operate in parallel, working on up to five different instructions at a time. A basic ’single-cycle’ inst ruction enters the pipeline and completes in five cycles.

7703C–AERO–6/09 AT697F ADVANCE INFORMATION By the time it reaches the write stage, four more instructions have entered and are driving through the pipeline behind it. So, after the first fi ve cycles, a single-cycl e instruction exits the pipeline and a single-cycle instruction enters the pipeline on ev ery cycle. Of course, a ’single- cycle’ instruction actually takes five cycles to complete, but they are called single cycle because with this type of instruction the processor can complete one instru ction per cycle after the initial five-cycle delay. In order to maximize performance and parallelism, the AT697F SPA RC implementation uses powerful AMBA bus. Instructions in the pr ogram memory are executed with a five level pipelining. While one instruction is being executed, the ne xt instruction is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. Program Counters Two 32-bit program counters (PC and nPC) are provided. The 32-bit PC contains the address of the instruction currently being executed by the IU. The nPC holds the address of the next instruction to be executed (assuming a trap does not occur). When a trap occurs, the PC address is saved in t he local register (l1) while the nPC address is saved in the local register (l2). When returning fr om trap, l1 value is copied back to PC and l2 value is copied back to nPC. ALU - Arithmetic Logic Unit The high-performance ALU operates in direct connection with all the 32 general purpose work - ing registers. Within a single clock cycle, ar ithmetic operations between general purpose registers or between a register and an immedi ate memory address ar e executed. The imple - mentation of the architecture also provide a powerful multiplier/divider supporting both signed and unsigned multiplication/division. Support for high performance 64-bit operation is also provided.The 32-bit Y register contains the most significant word of the double-precision product of an integer multiplication, as a result of either an integer multiply instruction, or of a r outine that uses the integer multiply step instruc tion. The Y register also holds the most significant word of the double-precision dividend for an integer divide instruction. Register File - Windows The fast access register file contains 8 SPARC register windows. Each window consists in a 32- register set. When a program is running, it has access to 32 32-bit processor registers which include 8 global registers plus 24 registers that belong to the current register window.

• The first 8 registers in the window are called the in registers’ ( i0-i7). When a function is called, these registers may contain arguments that can be used.
• The next 8 are the ’local registers’ ( l0-l7) which are scratch registers that can be used for anything while the function executes.
• The last 8 registers are the ’out registers’ ( o0-o7) which the function uses to pass arguments to functions that it calls. AT697F register file implementation is based on two dual-port rams. The first dual-port ram cor - responds to %rs1 operand of a SPARC instruct ion while the second corresponds to %rs2 operand. The two dual-port rams contents are always equal. When one function calls another, the calling function can choose to execute a SAVE instruction. This instruction decrements an internal counter, the current window pointer ( cwp), shifting the register window downward. The caller’s out registers then become the calling function’s in regis- ters, and the calling function gets a new set of local and out registers for its own use. Only the pointer changes because the registers and return address do not need to be stored on a stack. The RETURN instruction acts in the opposite way

Figure 3. Overlapping Windows SAVE, RESTORE, or RETT instruction. rdware error trap (trap 0x20) is generated. with the asr16Jtcb field before being written to the register file. pply to the error injection test process.

• Test checkbits TCB[2:0] is Xored with checkbit[6:4] corresponding to the %rs1 operand.
• Test checkbits TCB[5:3] is Xored with checkbit[6:4] corresponding to the %rs2 operand. Here is a simple example for the test of a single error in register file %rs1 ! 0x32 = ! register file test enable ! tcb[2:0] = 0x4 ! tcb[5:3] = 0x1 mov 0x32, %l1 mov %l1, %asr16 ! clear %l3 ! => write 0x0 to %l3 ! forces 0x08 as checkbit for %l3 (error insertion in %rs1 dual-port ram) mov %g0, %l3 ! disable EDAC test mode mov %g0, %asr16 ! access to %l3 as %rs1 operand ! => single error detection and correction add %l3,%l2,%l1

mented each time a register correction is performed. It saturates at “111”. instructions, resulting in faster and more compact code. enabled/disables from within this register. Architecture manual that presents all the implemented instructions. tions. During the execution of floa ting-point instructions the processor pipeline is held. tolerance features like error detection and correction and triple modular redundancy. The FPU depends upon the IU to access all addr esse s and control signals for memory access. integer and floating-point instructions is provided by the IU. The FPU contains 32 32-bit floating-point f registers, which are num bered from f[0] to f[31]. by load/store single/double floating-point instructions (LDF, LDDF, STF, STDF).

• 0 = round to nearest
• 1 = round to zero
• 2 = round to +infinity
• 3 = round to -infinity

Figure 4. Rou nding Direction Schematic

0 Value > 0Value < 0

• Full triple modular redundancy (TMR) architecture The TMR architecture is based on a fully triplicated clock distribution (CLK1, CLK2 and CLK3) . The PCI clock and the CPU clock are built as three-clock trees. The same triplication is applied to the PCI reset and to the CPU re set. See figure 5 for an overview of the TMR architecture.

arbitrary single-event transient errors.

• EDAC protection on Regfile
• EDAC protection on external memory interface
• Parity protection on instruction and data caches

Figure 5. TMR structure

• break address register The break address defines a reference address for testing.
• mask register The mask indicates which bits of the break address register are to be effectively taken in accoun t during address test Configuration A watchpoint is enabled setting logical one at least one of the three bits IF, Dl or DS in the watchpoint address and mask registers. When all three bits are set logical zero, the watchpoint is disabled. If the instruction fetch bit (IF) from the watchpoint a ddress register is set logical one, any attempt to fetch an instruction from one of the address defined by ADDR and MASK results in a trap generation. If the data store bit (DS) from the watchpoint addr ess register is set logical one, any attempt to store data to one of the address defined by ADDR and MASK results in a trap generation. If the data load bit (DL) from the watchpoint mask r egister is set logical one, any attempt to load a data from one of the address defined by ADDR and MASK results in a trap generation. Operation To detect if an address is part of the memory address range that traps, address bit 31 down to bit 2 are Xored with the BADxJBADDx. This operation is based on the followin g segmentation of an address. Table 7. bit num. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field Address ignored Address Segmentation With such segmentation, it is possible to def ine trap segment from 4bytes up to 1Gbyte. The result of the Xor is then Anded with the BMAxJBMA x. If the result is zero, this indicates that address sp ecified is in the watched range. Then, a watch- point hit error is generated. Trap 0x0B is generated. If result is different from zero, address is out of the watched address range.

Figure 6. Watchpoint H it Principle

• asynchronous traps also called interrupts.

lished by supervisor and the displacement, within th e table, is determined by the trap type. ware to write the program counters (PC & nPC) into two registers of the new window. traps and their individual priority. Table 8. T rap Overview

7703C–AERO–6/09 AT697F ADVANCE INFORMATION Traps Description • reset - A reset trap is caused by an external re set request. It causes the processor to begin executing at virtual address 0. After a Reset Trap, no special memory states are defined exept the bits PSRJET’ and PSRJS that are initialized respectively ‘0’ and ‘1’.

• write error - An error exception occurred on a data store to memory.
• instruction_access_exception - A blocking er ror exception occurred on an instruction access.
• illegal_instruction - An attempt was made to execute an instruction with an unimplemented opcode, or an UNIMP instruction, or an instruction that would result in illegal processor state.
• privileged_instruction - An attempt was made to execute a privileged instruction while supervisor bit PSRJS is ‘0’ (not in supervisor mode).
• fp_disabled - An attempt was made to execut e an FPU instruction while FPU is not enabled or not present.
• cp_disabled - An attempt was made to execute a co-processor instruction while co- processor is not enabled or not present.
• watchpoint_detected - An instruction fetch memory address or load/store data memory address matched the contents of a pre-loaded implementation-dependent “watchpoint” register.
• window_overflow - A SAVE instruction attemp ted to cause the current window pointer (CWP) to point to an invalid window in the WIM.
• window_underflow - A RESTORE or RETT inst ruction attempted to cause the current window pointer (CWP) to point to an invalid window in the WIM.
• register_hardware_error - An error exception occurred on a read only register access. A register file uncorrectable error was detected.
• mem_address_not_aligned - A load/store in struction would have generated a memory address that was not properly aligned according to the instruction, or a JMPL or RETT instruction would have generated a non-word-aligned address.
• fp_exception - An FPU instru ction generated an IEEE_754_exception and its corresponding trap enable mask (TEM) bit was 1, or the FPU instruction was unimplemented, or the FPU instruction did not complete, or there was a sequence or hardware error in the FPU. The type of floating-point exception is encoded in the FSRJFTT.
• data_access_exception - A blocking error exce ption occurred on a load/store data access. EDAC uncorrectable error.
• tag_overflow - A tagged arithmetic instruction was executed, and either arithmetic overflow occurred or at least one of the tag bits of the operands was non zero.
• trap_division_by_zero - An integer divide instruction attempted to divide by zero.
• trap_instruction - A software instruction (Ticc) was executed and the trap condition evaluated to true. When multiple synchronous traps occur at the same cycle (i.e hardware errors), the highest pri- ority trap is taken, and lower priority traps are ignored.

gate interrupts requests from internal or external devices to the integer unit. Figure 7. Interrupt Controller Block D iagram Interrupt Mask & Priority Reg. priority level 0 is forwarded. acknowledgement will clear the force bit rather than the pending bit. Interrupt List The following table presents the assignement of the interrupts. Table 9. Interrupt O verview

7703C–AERO–6/09 AT697F ADVANCE INFORMATION Non Maskable Interrupt (NMI) The AT697F handles interrupt 15 (trap type TT = 0x1F). This interrupt can not be masked by the inte- ger unit of the processor. It shall be used with care as the NMI of the processor. I/O interrupts As an alternate function of the general purpose inter face, the AT697F allo ws to input interrupt from external devices. Up to eight external interrupts can be programmed at the same time. The external interrupts are assigned to interrupt 4, 5, 6, 7,10, 12, 13 and 15. Two registers are defined for configu ration of the IO interrupts :

• IOIT1 register is used for control of IO interrupt 0, 1, 2 and 3
• IOIT2 register is used for control of IO interrupt 4, 5, 6 and 7 Each I/O interrupt is controlled through four fields in one of the above register (IOITx) : ENx, LEx, PLx and ISELx. An I/O interrupt is enabled set ting logical one to IOITx JENx . Setting this bit logical zero dis - ables the interr upt. The IOITxJISELx defines which port of the general purpose interface should generate I/O interrupt x. The port can be selected from within PIO[15:0] and D[15:0]*. Each I/O interrupt can have its trigger mode and its polar ity individually configured. When bit IOITxJLEx is set logical one, the corresponding I/O interrupt is edge triggered. If the polarity bit IOITxJPLx is driven logical one the interrupt triggers when a rising edge is applied on the pin. If the polarity bit is driven logical zero the inte rrupt triggers when a falling edge is applied on the pin. When the bit IOITx JLEx is set logical zero, the corresponding I/O interrupt is level sensitive. If the polarity bit IOITxJPLx is driven logical one the interrupt triggers when a high level is applied on the pin. If the polarity bit is driven logical zero the interrupt triggers when a low level is applied on the pin. The following table summarizes the I/O interrupt configurations. Table 10. LEx PLx Trigger 0 0 low level 0 1 high level 1 0 falling edge 1 1 rising edge I/O Interrupt Configuration 2 0x12 UART 2 1 0x11 Internal bus error Interrupt TT (Trap Type) Source

AT697F ADVANCE INFORMATION 7703C–AERO–6/09 Interrupt Priority The 15 interrupts handled by the AT697F are prioritised, with interrupt 15 (TT = 0x1F) having the highest priority and interrupt 1 (TT = 0x11) the lowest. It is possible to change the priority level of an interrupt using the two priority levels from the inter- rupt mask and priority register (ITMP). Each interrupt can be assigned to one of two levels as programmed in the Interrupt mask and priority regi ster. Level 1 has higher priority than level 0. Within each level the interrupts are prioritised.

Table 11. Me mory Controller address map configure some memory spaces as 8-bit wide data bus. uration. SRAM and SDRAM are configured through MCFG2 and MCFG3. Here is an overview of the 32-bit interconnection b etween the AT697F and external memories. Figure 8. Me mory Interface Overview

(RAMOE*x) and write enable (RWE*x) lines. banks are selected with RAMS*[3] down to RAMS*[0]. pper address 0x60000000. This bank is always 256 Mbytes large. Figure 9. SRAM ban k organisation

1. When SDRAM is enabled, priority is given to the SDRAM. Any access to addresses higher

than 0x60000000 is driven to SDRAM. No SRAM control is activated. (RAMSN and RAMOE are not deasserted).

7703C–AERO–6/09 AT697F ADVANCE INFORMATION Write Protection Two write protection schemes are provided to prevent accidental over-writing to the RAM area, the “Start/End address Scheme” and the “Mask Scheme”. These two schemes are explained in the following two sub-chapter Start/End address Schem e Two memory areas are defined by using a start-address and an end-address register. The first address of the protected memory area is calculated as 0x40000000 + START*4. The last address of the protected memory area is calculated as 0x40000000 + END*4. Table 12. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 START BP 0 Start Address Register (WPSTAx) Table 13. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 STOP US SU End Address Register (WPSTOx) Setting WPSTAxJBP x to logical one, any access inside the two areas defined by the start/end registers will cause a memory exception (trap 0x2B). The first address of the protected against write operation is calculated as 0x40000000 + START*4. The first address outside the protected memory area is calculated as 0x40000000 + END*4 + 4. Setting WPSTAxJBPx to logical zero the area between the start address and the end address defines the memory where write access is permitted, and a write access ou tside both areas will cause a memory exception (trap 0x2B). The first address where write operation is permitted is calculated as 0x40000000 + START*4. The first address outside the protected allowed area is calculated as 0x40000000 + END*4 + 4. The start/end address protection scheme is enable d when at least one of the user mode protec- tion and the supervisor mode protection is valid . The write protection can be configured to prevent the application from user and/or supervisor write access.

• Memory is protected against User write when WPSTOxJUSx bit is set logical 1
• Memory is protected against Superviser write when WPSTOx JSUx bit is set logical 1

With such segmentation, memory block in the rang e of 32Kbyte up to 1Gbyte can be protected. The result of the Xor is then Anded WPRxJMASK. Figure 16. RAM Write Pro tection Overview

• If all the enable protection units are configured in b lock protect mode (BP = 0), then a write protect error is generated when any of the units signal a write protection hit. In this mode, if at least one protection error is triggered, the write protection trap is raised.
• If at least one of the protection units operates in segment mode (BP=1), then a write protect error is generated only if all units configured in segment mode signal a protection error.

enable (SDWE*), data masks (SDDQM*x) and clock lines. ow-address bits, and 4 banks. Only 32-bit data bus width is supported for SDRAM banks. 0x60000000. If MCFG2JSE if set logical zero, no SDRAM can be used. The address bus of the SDRAMs shall be connected to A[14:2], the bank address to A[16:15]. less than 13 address pins should only use the less significant bits of A[14:2]. Figure 17. SDRAM co nnection overview Table 15. SDRAM Programmable Timing Parameters

• if set to ‘01’, Precharge command is sent,
• if set to ‘10’, Auto-Refresh command is sent,
• if set to ‘11’, Load Mode Reg (LMR) is sent. When the LMR command is issued, the MCFG2 JSDRCAS delay pr ogrammed is used. MCFG2JSDRCMD is cleared after a co mmand is executed. When changing the va lue of the CAS delay, a LOAD-MODE-REGISTER command should be generated at the same time. The SDRAM controller also provides a refresh comma nd. It can be enabled by setting a logical one into MCFG2JSDRREF.

7703C–AERO–6/09 AT697F ADVANCE INFORMATION The Auto-Refresh command enables a periodical refresh for both SDRAM banks. The period between two Auto-Refresh command is programmed in MCFG3JSRCRV. Depending on SDRAM type, required period is typically 7.8 or 15.6 μs. This corresponds to 780 or 1560 clock cycle at 100MHz. Refresh period is calculated as Refresh Period Reload value 1+ SDRAM Initialisation After reset, the SDRAM controll e r automatically performs the SDRAM initialisation sequence. It consists in PRECHARGE, tw o AUTO-REFRESH cycles a nd LOAD-MODE-REG on both banks simultaneously. The controller programs the SDRAM to use page burst on read and single location access on write. A CAS latency of 3 is programmed by default. This value can be updated later by software. SDRAM Read Access A read transaction consists in three main oper a tion. First, an ACTIVATE command to the desired bank and row is performed. Then, after the programmed CAS delay, a READ command is sent. The read transaction is terminated with a PRE-CHARGE command. No bank is left open between two accesses. A burst read is performed if a burst access is requested on the internal bus. SDRAM Write Access A write transactions consists in three main operations. First, an ACTIVATE command to the desired bank and row is performed. Then, a WRITE command is sent. The write transaction is terminated with the PRE-CHARGE command. A burst write on internal bus generates a burst of write commands without idle cycles in- be tween. Access Error An access error can be indicated to the processor asserting the BEXC* signal. If enabled by set- ting logical one to MCFG1JBEXC , the BEXC* signal is sampled with the data. If the BEXC* signal is driv en low by the external device during the access, an error response is generated on the internal bus.

• Trap 0x01 is taken if an instruction fetch is in progress
• Trap 0x09 is taken if a data space access is in progress
• Trap 0x2B is taken if a data store is in progress

7703C–AERO–6/09 AT697F ADVANCE INFORMATION If the application needs more time for IO transfer, it is possible to introduce more delay by acti - vating the hardware bus ready detect ion bit MCFG1JIOBRDY. Refer to paragraph “BRDY Wait states”, page 38. Write Protection Read and write protections are provided to prevent accidental accesses to I/O area. Protection is controlled through the I/O protection bit MCFG1JIOP. Bus width To support applications with low memory and performance requirements, I/O area can be con - figured for 8-bit operations. The configuration of I/O in 8-bit mode is done programming the I/O bus width in MCFG1JIOWDH. In such configuration, I/O device is not access ed by multiple 8-bit ac cesses as other memory areas. Only one single access is performed When the I/O bus is configured as an 8-bit wid e bus, data 31 downto 24 shall be used as interface. Figure 24. CS OE WE A DIOOE* AD AT697F A[27:0] D[31:24] D[31:24] A[27:0] WRITE* IOS* I/O 8-bit bus width connection Access Error An access error can be indicated to the processor asserting the BEXC* signal. If enabled by set- ting logical one the MCFG1JBEXC , the BEXC* signal is sampled with the data.

• Trap 0x01 is taken if an instruction fetch is in progress
• Trap 0x09 is taken if a data space is in progress
• Trap 0x2B is taken if a data store is in progress BRDY Wait states For PROM accesses, for IO accesses and for RAM bank 4, but not for the other RAM banks, it is po ssible to introduce additional wait states determined by the peripherals with the BRDY* mech- anism. This capability can be enabled separ atly b y the respective configuration bits MCFG1JPBRDY, MCFG1JIOBRDY and MCFG2JRAMBRDY. If the configuration bit is set to one, the processor waits before ending the transf er, as long as the BRDY * pin is driven high. If the configuration bit is set to zero (reset stat e), the BRDY* pin is ignored.Termination of the BRDY* induced wait states can be in two different modes:
• I f M C F G 1JABRDY is set to zero (reset state), BRDY* needs to be asserted zero synchronously with respect to SDCLK, respecting the setup and hold times t19 and t20 (Refer to section “AC Characteristics”, page 130).The processor will terminate the access at the rising clock edge immediately following the r ising edge during which BRDY* was low by de-asserting the OE* and the select signal (RAMS*[4], IOS* or ROMS*), as shown in the figures.
• I f M C F G 1JABRDY is set to on e, BRDY* is double synchronised in the processor, and it can be asserted asynchronously, without respecting t19 and t20, provided it is asserted low for at least 1.5 clock cycle. Asynchronous BRDY* timing implies an uncertainty, the access terminates at the second or third edge after its assertion, and read data needs to be kept stable until OE* and the select signal (RAMS*[4], IOS* or ROMS*) are de-asserted. It should be noted that the BRDY* mechanism can be used in addition to the nominal duration of an access (one or two data cycles depending on the ac cess type) and to the fixed wait states programmed in the “WS” fields (MCFG2 JRAMWWS, MCFG1 JPRWWS, MCFG1 JIOWS). Even when BRDY* goes low earlier, the trasaction does not terminate until expiration of the pro- grammed wait states.

7703C–AERO–6/09 AT697F ADVANCE INFORMATION Error Management - EDAC Overview The AT697F processor implements an on-chip erro r detector and corrector (EDAC). The on-chip memory EDAC can correct one error in a 32-bit word and detect two errors in a 32-bit word. The processor EDAC implemention enables data correction on-the-fly so that no timing penalty occurs during correction. EDAC capability ma pping Data error management with the EDAC can be u sed on both PROM and RAM memory areas. The following table presents the EDAC protection capabilities provided by the processor. Table 16. Address Range Area EDAC Protected 0x00000000 - 0x1FFFFFFF PROM 8 bits yes 32 bits yes 0x20000000 - 0x3FFFFFFF I/O All no 0x40000000 - 0x7FFFFFFF RAM 8 bits yes 32 bits yes EDAC capability on Memories PROM protection Setting logical one the PROM EDAC enable bit MCFG3JPE, the d ata protection is enabled. For each read and write transaction to the PROM area the EDAC act as an error detector and an error corrector. When set logical zero, the EDAC is transparent for the PROM access. At power-on or at reset, the value of the MCFG3JPE i s directly copied from the PIO2 pin. In that way, it is possible to start the application with the EDAC enabled by driving high PIO2 during the power-on sequence (or reset sequence). RAM protection Setting logical one the RAM EDAC enable bit MCFG3 JRE, the data protection is enabled. For each read and write transaction to the RAM area the EDAC act as an error detector and an error corrector. When set logical zero, the EDAC is transparent for the RAM access. Operation The processor uses an EDAC based on a seven bit Ha mming code that detects any double error on a 32-bit bus and corrects any single error on a 32-bit bus. Note when the EDAC is enabled the read-modify-write bit MCFG2JRMW must be set. Hamming code For each 32-bit data, a seven bit a 7-bit checksu m is generated. The equations below show how the Hamming checkbits (CBx) are generated: CB0 = D0 ^ D4 ^ D6 ^ D7 ^ D8 ^ D9 ^ D11 ^ D14 ^ D17 ^ D18 ^ D19 ^ D21 ^ D26 ^ D28 ^ D29 ^ D31 CB1 = D0 ^ D1 ^ D2 ^ D4 ^ D6 ^ D8 ^ D10 ^ D12 ^ D16 ^ D17 ^ D18 ^ D20 ^ D22 ^ D24 ^ D26 ^ D28 CB2 = D0 ^ D3 ^ D4 ^ D7 ^ D9 ^ D10 ^ D13 ^ D15 ^ D16 ^ D19 ^ D20 ^ D23 ^ D25 ^ D26 ^ D29 ^ D31 CB3 = D0 ^ D1 ^ D5 ^ D6 ^ D7 ^ D11 ^ D12 ^ D13 ^ D16 ^ D17 ^ D21 ^ D22 ^ D23 ^ D27 ^ D28 ^ D29 CB4 = D2 ^ D3 ^ D4 ^ D5 ^ D6 ^ D7 ^ D14 ^ D15 ^ D18 ^ D19 ^ D20 ^ D21 ^ D22 ^ D23 ^ D30 ^ D31 CB5 = D8 ^ D9 ^ D10 ^ D11 ^ D12 ^ D13 ^ D14 ^ D15 ^ D24 ^ D25 ^ D26 ^ D27 ^ D28 ^ D29 ^ D30 ^ D31 CB6 = D0 ^ D1 ^ D2 ^ D3 ^ D4 ^ D5 ^ D6 ^ D7 ^ D24 ^ D25 ^ D26 ^ D27 ^ D28 ^ D29 ^ D30 ^ D31 Write operation When the processor performs a write operation to a m emory protected by the EDAC, it also out- puts the seven bit checksum on the CB[6:0] pins. Read operation During a read operation from a protected memory, the seven bit checksum is sampled from the CB[6 :0] inputs. Then, the EDAC verify the checksum to check the presence of an error. According to the checksum equations, the ED AC calculates its ow n checksum. Th en a syn - drome generator uses the calculated and the read checksum to qualify if there is no error, one er ror or two errors in the read word. Correctable error If a single error is detected, this leads to a co r rectable error. The correction is done on-the-fly during the current access and no timing penalty is induced but the corrected data is not automat- ically written back to the memory.

AT697F ADVANCE INFORMATION 7703C–AERO–6/09 The correctable error detection event is reported in the fail address register (FAILAR) and in the fail status register (FAILSR). If unmasked, interrupt 1 (trap 0x11) is generated. The interrupt can then be attached to a low priority interrupt handler that scrubs the failing memory location. Uncorrectable error If a double error is detected, this leads to an un-correctable error. An un-correctable error detec- tion during a data access leads to a data access exception (trap 0x09). In case the double error is detected during instruction fetch, it leads to an instruction access error (trap 0x01). Figure 27. Data Bus Memory Configuration Reg. MCFG3 CB[7:0] EDAC Fail Address Reg. FAILAR Fail Status Reg. FAILSR Address Bus trap 0x01 trap 0x09 trap 0x11 EDAC overview EDAC on 8-bit areas The 8-bit mode applies to RAM and PROM while SDRAM always uses 32-bit accesses. When a memory area is configured in 8-bit mo de, th e EDAC checkbit bus (CB[7:0]) is not used but it is still possible to use EDAC protection. The data bus mapped on D31:24 is always accessed in a 32-bit wide word basis (4bytes at a time) . The corresponding checkbits are located on top of the selected memory bank according to the following operation:

• The address A[27:2] of the 32-bit data word is inverted
• The resulting address is then shift ed twice right to become a byte address
• The checkbit is written to the derived byte add re ss while the data address chipselect is kept active so that the current memory area is still active. A word written as four bytes to addresses 0, 1, 2, 3 will have its checkbits at address 0x0F FFFFFF, addresses 4, 5, 6, 7 at 0x0FFFFFFE and so on. Here is an example of checkbit addressing:
• The data is written at address 0x00000004
• Inversion of this address lids to 0xFFFFFFFB
• Once shifted we have 0xFFFFFFFE
• The checkbit is located at address 0xFFFFFF FE in the same memory bank as the data. All the bits up to the maximum bank size will be inverted while the same chip-select is always asserted. This way all the bank size ca n be s upported and no memory will be unused (except for a maxi- mum of 4 Bytes in the gap between the data and checkbit area). Here is an overview of the memory organization when EDAC is enbled on a 8-bit area.

mance of the cpu core, multi-set-caches are us ed for both instruction and data caches. areas. The following table presents the caching capabilities of the processor. fined in the SPARC standard. Using the LDA/STA instructions, alternative address spaces as caches can be accessed. ASI[3:0] are used for the mapping when ASI[7:4] have no influence on operation.

• Access with ASI 0 - 3 will force a cache miss, update the cache if the data was previously cached or allocate a new line if the data was not in the cache and the address refers to a cacheable location.
• Access to ASI 4 and 7 will force a cache mi ss and update the cache if the data was previously cached. The following table shows the ASI implementation on the AT697F.

Table 18. ASI Usage Note: Please refer to the SPARC v8 specification for detailed information on ASI usage.

7703C–AERO–6/09 AT697F ADVANCE INFORMATION Overview The AT697F instruction cache is a multi-set cache of 32 kbyte divided in 4 memory sets. Multi- set-cache use improves speed per formance of the core. The instru ction cache is divided into cache lines with 32 bytes of data. Each line has a cache tag associated with it consisting of a tag field and one valid bit per 4-byte sub-block. Cache Control The instruction cache operations are controled with the cache control register (CCR). Operation On an instruction cache miss to a cachable lo cation, the instruction is fetched and the corre - sponding tag and data line updated. The instruction cache always works in one of three modes:

• disabled,
• enabled
• or frozen. The instruction cache current state is reported in the instruction cache state CCRJICS. Disabled mode If disabled, no cache operation is performed and load and store requests are passed directly to the memory controller. Enabled mode If enabled, the cache operates as described abov e. In the frozen state, the cache is accessed and kept in synchronisation with the main memory as if it was enabled, but no new lines are allo- cated on read misses. Freeze mode If CCRJIF is set logical one, the instruction cac he is frozen when an asynchronous interrupt is taken. This can be beneficial in real-time system to allow a more accurate calculation of worst- case execution time for a code segment. The execution of the interrupt handler will not evict any cache lines and when control is re turned to the interrupted task, the cache state is identical to what it was before the interrupt. If a cache has been frozen by an interrupt, it can only be enabled again by enabling the cache in the CCR. This is typically done at the end of the interrupt handler before control is returned to the interrupted task. Burst fetch An instruction burst fetch mode can be enabled setting logical one in CCR JIB. If the burst fetch is enabled, the cache line is filled from main memory starting at the missed address and until the end of the line. At the same time, the instructions are forwarded to the IU. If the IU cannot accept the streamed instructions due to internal dependencies or multi-cycle instruction, the IU is halted until the line fill is completed. If the IU executes a control transfer instruction during the line fill, the line fill will be terminated on the next fetch. If instruction burst fetch is enab led, instruction streaming is enabled even when the cache is disabled. In this case, the fetched in structions are only forwarded to the IU and the cache is not updated. Cache Flush Instruction cache can be flushed by executing the FLUSH instruction, setting logical one in CCRJFI, or writing any location with ASI=0x5. The flush operation takes one cycle per line dur ing which the IU will is not halted, but during which the cache is disabled. When the flush operation is completed, the cache will resume the state indicated in the cache control register. Error reporting If a memory access error occurs during a line fill with the IU halted, the corresponding valid bit in the cache tag is not set. If the IU later fetches an instruction from the failed address, a cache miss will occur, triggering a new access to the failed address. If the error remains, an instruction access error trap (tt=0x1) is generated. Instruction Cache Parity Error detection of cache tags and data is impl emented using two parity bits per tag and per 4- byte data sub-block. The tag parity is generat ed from the tag value and the valid bits. The data parity is derived from the sub-block data. The pa rity bits are written simultaneously with the associated tag or sub-block and checked on each access. The two parity bits correspond to the parity of odd and even data (tag) bits.

AT697F ADVANCE INFORMATION 7703C–AERO–6/09 If a tag parity error is detected during a cache access, a cache miss is generated. The tag and the data are automatically updat ed. All valid bits except the one corresponding to the newly loaded data are cleared. Each error is reported in the instruction cache tag error counter from the CCR. The instruction ca che tag error counter CCR JITE is incremented after each instruc - tion cache tag error detection. If a data sub-block parity error occurs, a miss is also generated but only the failed sub-block is updated with data from main memory. Each error is reported in the instruction cache data error counter from the CCR. The instruct ion cache data error counter CCR JIDE is incremented after each instruction cache data error detection. Data Cache Overview The AT697F data cache is a multi-set cache of 16 kbyte divided in 2 memory sets. Multi-set- cache use improves speed perfor mance. The data cache is divided into cache lines with 16 bytes of data. Each line has a cache tag associated with it consisting of a tag field and one valid bit per 4-byte sub-block. Cache Control The instruction cache operations are controled with the cache control register (CCR). Operation Write The write policy for stores is write-through with no-allocate on write-miss. The write buffer (WRB) consists of three 32-bit registers used to temporarily hold store data until it is sent to the destina- tion device. For half-word or byte stores, the stored data replicated into proper byte alignment for writing to a word-addressed device, before being loaded into one of the WRB registers. The WRB is emptied prior to a load-miss cache-fill sequence to avoid any stale data from being read in to the data cache. Read On a data cache read-miss to a cachable locati on, 4 bytes of data are loaded into the cache from main memory. Cache Flush Data cache can be flushed by executing the FL USH instruction, setting logical one in CCRJFD in the cache control register, or writing any location with ASI=0x6. The flush operation takes one cycle per line during which the IU will is not halted, but during which the cache is disabled. When the flush operation is completed, the cache will resume the state indicated in the cache control register. Error Reporting Since the processor executes in parallel with th e write buffer, a write error will not cause an exception to the store instruction. Depending on memory and cache activity, the write transac - tion may not occur until several clock cycles after the store instructions has completed. If a write error occurs, the currently executing instruction will take trap 0x2B. Note: the 0x2B trap handler should flush the data cach e, since a write hit would update the cache while the memory would keep the old value due the write error. If a memory access error occurs during a data load, the corresponding valid bit in the cache tag will not be set. and a data access error trap (tt=0x09) is generated. Data Cache Parity Error detection of cache tags and data is impl emented using two parity bits per tag and per 4- byte data sub-block. The tag parity is generat ed from the tag value and the valid bits. The data parity is derived from the sub-block data. The pa rity bits are written simultaneously with the associated tag or sub-block and checked on each access. The two parity bits correspond to the parity of odd and even data (tag) bits. If a tag parity error is detected during a cache access, a cache miss is generated. The tag and the data are automatically updat ed. All valid bits except the one corresponding to the newly loaded data are cleared. Each error is reported in the instruction cache tag error counter from the CCR. CCRJDTE is incremented after each data cache tag error detection.

7703C–AERO–6/09 AT697F ADVANCE INFORMATION If a data sub-block parity error occurs, a miss is also generated but only the failed sub-block is updated with data from main memory. Each error is reported in the data cache data error coun - ter from the CCR. CCRJDDE is incremented after each data cache data error detection. Data Cache Snooper In addition to the cache controller, a snooper is implemented on the on-chip cache subsystem. The cache snooper is enabled setting logical one in CCRJDS. This snooper is able to verify if a master on the internal bus accesses and modifies some cached data. If a master accesses a data in me mory and this data is cached, the snooper will invalidate the corresponding cache tag. Next time the IU will access the modified data, a cache miss will be generated due to not valid tag. Diagnostic Cache Access Tags and data in the instruction and data ca che can be accessed th rough ASI address space 0xC, 0xD, 0xE and 0xF by executing LDA and STA instructions. Address bits making up the cache offset will be used to index the tag to be accessed while the least significant bits of the bits making up the address tag will be used to index the cache set. Diagnostic read of tags is possible by execut ing an LDA instruction with ASI=0xC for instruction cache tags and ASI=0xE for data cache tags. Th e cache line and the cache set are indexed by the address bits making up the cache offset and the least significant bits of the address bits making up the address tag. Similarly, the data sub-blocks may be read by executing an LDA instruction with ASI=0xD for instruction cache data and ASI=0xF for data cache data. The sub-block to be read in the indexed cache line and set is selected by A[4:2]. The tags can be directly writte n by executing a STA instruction with ASI=0xC for the instruction cache tags and ASI=0xE for the data cache tags . The cache line and cache set are indexed by the address bits making up the cache offset and the least significant bits of the address bits making up the address tag. D[31:10] is writ ten into the ATAG filed and the valid bits are written with the D[7:0] of the write data. The data sub-blocks can be directly writte n by executing a STA in struction with ASI=0xD for the instruction cache data and ASI=0xF for the data cache data. The sub-block to be read in the indexed cache line and set is selected by A[4:2]. Note: Diagnostic access to the cache is not possible during a FLUSH operation and will cause a data exception (trap=0x09) if attempted.

ter restarts counting from the new value. If the counter is not refreshed before the counter reaches zero, WDOG signal is asserted. reset is about 2^34 clock cycles. Figure 32. Watchdog Block Diagram

7703C–AERO–6/09 AT697F ADVANCE INFORMATION configuring the pin The upper 16 bits of the general purpose interface can only be configured as outputs or inputs on byte basis. D[15:8] is referenced as the medium byte when D[7: 0] is referenced as the lower byte. Each byte from D[15:0] consists of two register fiel ds. As shown in the “Register Description” section, the direction fields are accessed at IODIR address when data fields at IODAT address. The IODIRJMEDDIR bit and the IODIR JLOWDIR bit select the dire ction for respectively the medium byte ( D[15:8] ) and the lower byte ( D[7: 0] ). If MEDDIR (or LOWDIR) is written logic one, the corresponding byte in D[15:0] is configur ed as output. If written logic zero, the byte is configured as an input. When configured as an input, a read of the IODAT JMEDDAT fileds returns the current value of D[15:8]. When configured as an output, the logical value from IODAT JMEDDAT field is trans - lated in physical values on D[15:8] bus. When configured as an input, a read of the IODATJLOWDAT fileds re turns the current value of D[7:0]. When configured as an output, the logical value from IODAT JLOWDAT field is trans - lated in physical values on D[7:0] bus. switching between input & outp ut When the medium byte (or the lo w er) is switched from input to output by switching MEDDIR (or LOWDIR), the value of MEDDAT (or LOWDAT) is immediatly driven on the corresponding pin. When switched from output to input by toggling MEDDIR (or LOWDIR ), the value from the pins are immediatly written to MEDDAT (or LOWDAT). GPI Alternate functions Most GPI pins have alternate functions in addition to being general I/O. Facilities like serial com- munication link, interrupt input and configurat ion are made available through these functions. The following table summaryses the assignement of the alternate functions. Table 19. GPI port pin Alternate function PIO[15] TXD1 - UART1 transmitter data PIO[14] RXD1 - UART1 receiver data PIO[13] RTS1 - UART1 request-to-send PIO[12] CTS1 - UART1 clear-to-send PIO[11] TXD2 - UART2 transmitter data PIO[10] RXD2 - UART2 receiver data PIO[9] RTS2 - UART2 request-to-send PIO[8] CTS2 - UART2 clear-to-send PIO[3] UART clock - Use as alternative UART clock PIO[2] EDAC enable - Enable EDAC checking at reset PIO[1:0] Prom width - Defines PROM bus width at reset GPI alternate functions In addition to these alternate functions, each GPI interface pin can be configured as an interrupt input to catc h interrupt from external devices. Up to four interrupts can be configured on the GPI interface by programming the I/O interrupt register (IOIT). For a detailed description of the external interrupt configuration, please refer to the “Traps and Interrupts ” section.

agents numbered from 3 downto 0. A round-robin algorithm is implemented as arbitration policy. mines that the bus can be granted to an agent, it drives low the corresponding GNT* line. defined as level 0. A low priority loop is defined as level 1. Figure 35. Arb itre operation - Agent

• All agents in one leve l have equal probability
• All agents in level 1 to gether have the same probability of access as one agent in level 0.
• If no agent is in level 0, or no agent in level 0 has a request, all agents in level 1 are granted with equal probability Bus Parking As long as no bus request is active on the arbiter, the b us is granted to the last owner. It remains granted to the last owner until another agent requests the bus. When another request is asserted, re-arbitration occurs after one turnover cycle. After reset, the bus is parked to agent 0. Agent 0 is the default owner after a reset operation. Re-arbitration When a master is managing a transfer and anoth er one makes a request to the arbiter, re-arbi - tration occurs. Only one re-arbitration is perform ed dur ing a transfer. A new arbitration will take place when the master which was granted the bus frees the bus. As long as all the PCI agents have no request pending, the arbitration is perform ed. A re-arbitration cycle also occurs when living the bus parking state. Priority definition Two different priority levels are defined for the PCI arbiter. Level 0 is defined as the high priority level. Level 1 defines the low priority level. Assignment of the PCI agents priority level is pro - grammable through the arbiter configuration register (ACR). Each PCI agent can be individually configured to op erate eith er on level 0 or on level 1, except agent 3 that is defined by hardware with a low priority (level 1). Setting logical one in PCIA JPx leads the agents x to a low priority level. Setting this bit logical zero leads to a high priority. After reset, all the PCI agents are configured in the low priority loop.

7703C–AERO–6/09 AT697F ADVANCE INFORMATION PCI Interface Overview The PCI interface implementation is compliant with the PCI 2.2 spec ification. It is a high perfor - mance 32-bit bus interface with multiplexed addr ess and data lines. It is intended for use as an interconnect mechanism between processor/ memory systems and peripheral controller components. The AT697 processor embedds the In-Silicon PCI core . It is interfaced to the processor core through the PCI to AMBA bridge developped by the European Space Agency. The PCI bus operations can be clocked at a frequency up to 33MHz, independently of the pro - cessor clock. Synchronization of the operation between PCI interface and AT697 core implies numerous FIFO usage. This implementation allo ws to use the device for Initiator (Master) and Target operations. In each mode single word and burst transfer can be executed. Two different operating modes can be used with the PCI interface :

• Host Bridge The host-bridge connects the local bus of a processor to the PCI bus. Its PCI configuration registers are accessible locally by the processor, but not through PCI configuration cycles. Host-bridge initialises other satellite devices through PCI configuration commands.
• Satellite The satellite is a PCI device, configurable via PCI configuration cycles and the idsel line, but not locally. Both, host-bridge and satellites ca n be initiator and/or target on the bus. The pr esent interface has universal functionality, allowing both operation modes. The mode is configured via a hard - ware bootstrap on the SYSEN* pi n. The state of the SYSEN* pin is copied in PCIISJSYS. This enables plug and play boot programs loading th e appropriate driver depending on the hardware configuration. In the same manner, the configuration registers are made visible as read only when the device is configured as satellite Some other features are supported by this interface like
• Target lock support
• Zero-latency Fast Back-to-Back transfers
• Zero wait state burst mode transfers
• Support for memory read line/multiple
• Support for memory write and invalidate commands
• Delayed read support
• Flexible error reporting by polling The PCI bus is a multiplexed one. In this way, address and data through the same medium. That is why PCI communication is based on two phase burst transfer. Each transfer is composed of the following phases :
• An address phase During the address phase, the initiator of the communication drives the 32-bit address concerned by the transfer and the command involved through this transfer. The command defines the space area concerned with the transfer and the direction of the transfer.
• A data phase During the data phase the initiator of the communication drives the enable bit signal so that only active part of the bus is enabled. When reading, the initiator drives the enable bits and the target set the data on the bus. PCI Initiator (Master) The PCI initiator mode of the AT697 gives a direct memory-mapped (initiator) access to the PCI bus. Any access to a memory address in the PC I address range is automatically translated by the interface into the appropriate PCI transaction. In this configuration, the PCI bus is accessed by the same instructions as the main memory . The SPARC instruction set foresees various load/store instruction types. The PCI bus foresees 32 bit wide transactions with byte-enables for each byte lane.

PCI addresses outside of this predefined range can be accessed only via DMA transactions. mine which PCI byte enable line C/BE*[3:0] sh ould be active during the transaction. significant byte lane (bits 31:24) of the PCI data bus is selected. The following table presents the transaction width authorized for PCI transfers. Table 20. Byte Enable Settings Note: PCI byte enables are active low. data in the remote PCI target. mand to execute is performed setting the value PCIICJCOMMSB. invalidate on PCI address access.

1. This indicates that the linear incrementing mode is used.
2. Select the initiator mode by se tting logical one in the PCIICJMOD.
3. Select the memory load/store command or the memory read-line/write and invalidate
4. Enabling the interrupt signalisation is optionnal. It can be enabled setting logical one in

ity Error, PCI core error and system error.

1. Engage an access to a memory address mapped in the PCI address range.

7703C–AERO–6/09 AT697F ADVANCE INFORMATION IO transaction cycles operation The following procedure shall be used to engage I/O transaction on the PCI interface: 1. Select the initiator mode by setting logical one in PCIICJMOD. 2. Select the I/O load/store command in the PCI initiator configuration register. The PCI- ICJCOMMSB shall be set logical ‘00’ for I/O operation. 3. Enabling the interrupt signalisation is optionnal. It can be enabled setting logical one in PCIITEJIMIER. Up to four interrupt sources can be defined : Initiator Error, Initiator Par- ity Error, PCI core error and system error. 4. Engage an access to an I/O address mapped in the PCI address range. Configuration cycles Target selection Accesses to a configuration address space requires the target device to be selected. Due to the address range limitation, the chip-select (IDSEL) connection necessary for device selection shall be done using only A/D[27:16]. This allows up to 12 PCI devices to be connected on the bus. Devices with chip-select line connected to A/D[31:28] can’t be configured through standard operations. DMA configuration cycles shall be used to configure the devices connected to A/D[31:28]. The PCI bus configuration cycles can be perform ed using the same instructions as the main memory. To generate such configuration cycle with the standard instructions,PCIIC JCOMMS shall be programmed to ‘01’. Then, if a load (or store) cycle is performed to an addresss in the PCI address range, a physical configuration cycle is performed on the PCI bus. The full 32-bit address defined on the internal bus is propagated on the PCI bus. Once a target is selected (DEVSEL* asserted). Operation The following procedure shall be used to engage configuration cycle on the PCI interface: 1. Select the initiator mode by setting logical one tin PCIIC JMOD 2. Select the configuration load/store command in PCIIC JCOMMS shall be set logical ‘10’ for configuration operation. 3. Enabling the interrupt signalisation is optionnal. It can be enabled setting logical one in PCIITEJIMIER. Up to four interrupt sources can be defined : Initiator Error, Initiator Par- ity Error, PCI core error and system error. 4. Engage an access to an configuration space. Limitation Configuration cycles shall only be generated by the PCI host of the bus or by a PCI-to-PCI bridges. Special cycles By default, all requests are translated into single cycle PCI transactions, each transaction con - sisting in an address phase followed by a single data phase. Linear incrementing store-word Linear incrementing store-word sequences are translated into undetermined length PCI write bursts with up to a maximum of 255 words. The PCI burst mode is then maintained as long as possible. Read/write directi on is unchanged and the address A n+1 = An + 4. When the sequence is discontinued, the PCI burst stops with a last data phase during which byte enables are 1111. Fast back2back cycles The PCI implementation only s upports fast back2back cycles to the same target. Before using fast back-2-back transfers, fa st back-2-back cycles shall be enabled setting logical one the bit COM9 in the status command register (PCISC). PCISC JCOM9 shall only be set one if all tar - gets on the bus support fast back-2-back transfers. Issuing a fast back to back transfer is done setting logical one in PCIDMAJB2B. Note: Fast back-2-back can only be generated by the in itiator. It is not accepted by the AT697 PCI tar - get.

AT697F ADVANCE INFORMATION 7703C–AERO–6/09 Error reporting Fatal (abort) and address parity errors On a fatal error ( or address parity error ), the interface flushes all the current buffer requests and all other buffer requests. Then, the interface reports the fatal error driven logical one the PCIITEJCMFER. The PCI core is restarted as soon as a new request is engaged. DMA transfer A DMA facility is available on the AT697 processor. The DMA transfer are performed through the PCI interface. The DMA controller executes data transfer between the local memory and a remote target on the PCI bus. The processor core only intervenes for the initiation of the transfer. Once transfer is initiated, DMA controller is fully autonomous. DMA transfers take place in background of the processor core activity. Thus, interrupts are provided to help to synchronise the application with start and end of the transfer. The DMA interface executes only word-size transactions with all 4 byte lanes enabled. Operation The DMA is enabled setting logical one the PCIIC JMOD. To synchronize the application with the start and the end of the transactio n, two interrupts can be enabled : PCIITE JDMAER for transfer control and PCIITEJIMIER for error control. Each DMA sequence shall program the following parameters :

• PCI start address
• PCI command type
• number of words to be transferred
• the start address in the local memory A DMA transfer is performed assuming the following operations are done in the given order : 1. Write the PCI start address of burst to the PCI start address register (PCISA). The PCISA register shall be re-writen each time a DMA transfer is initiated, even if the address is identical to the address of the previous DMA request. 2. Write together the PCI command and the number of words to be transfered in the PCI DMA configuration register (PCIDMA). Writing to the PCIDMA passes the PCI address, the word count and the PCI command to the PCI core and initiates the transaction on the PCI bus. 3. Write the start address in the local memory map to the PCI DMA address register (PCIDMAA). Once the three operation are executed, data trans fer is started in background. Once the speci - fied number of words is transfered, the interface set logical one the PCIITE JDMAER and generate an interrupt if enabled. Then DMA controller goes back to idle state. Error Reporting If the PCI core does not accept the DMA cycle request, the DMA state controller remains locked and an error is reported as initiator error with the PCIITE JIMIER bit set logical one. If the request on the PCI core was just delayed, rewriting PCIDMAA may succeed. If the problem per- sists, reset the interface by writing –1 (0xFFFFFFFF) to PCIIC. Transfer Limitation A DMA transaction may never cross a 1 KByte border. The value represented by PCIDMAA(9:2) + PCIDMA(7:0) must be less than 256. If this restriction is not respected, the data transfer stops at the 1 kByte border. Then the PCI core is flushed. Simultaneously, in the PCI interrupt pending register (PCIITP) the dma error bit PCIITE JDMAER and the initiator error bit PCIITE JIMIER are asserted logical one. If enabled with the PCI interrupr enable register (PCIITE) and unmasked in the general interrupt mask register, the PCI interrupt 14 is generated (TT = 0x1E). Debug Facilities Not implemented for application use.

7703C–AERO–6/09 AT697F ADVANCE INFORMATION Target Mode Transfer In the target mode, the PCI interface receives requests originated from remote PCI initiators (masters). Target data transfer is executed in background without AT697 core intervention. AT697 core can only intervenes is the configuration of the target.

• In host bridge mode the target is configured by the AT697 core
• In satellite mode the configuration is done by a remote device using the PCI command set Target Programming The target is configured through the following registers :
• PCISC register bits 0/1 for memory and I/O command response bit 6 for check of data and address parity error bit 7 for response to data and address parity error
• base address registers memory base address : MEMBAR1, MEMBAR2 I/O base address : IOBAR
• PCITPA register to indicate the storage location
• P C I T S CJFRTY bit to write data in memory transaction Ordering As specified in the PCI standard, delayed read fu nctionality is implemented, obeying to the fol - lowing rules:
• The interface stores one delayed read at a time. When a read request was retried (because local data not yet available), the interface remains locked for any other target read (targeting different addresses). The initiator of the original read has to repeat its request to the same address.
• A retried (delayed) read can be interrupted by one or more PCI write accesses. The PCI standard requires this write command to be processed first, to prevent a system lock-up.
• Meanwhile, the interface will pref etch read-data into the TXMT FIFO. After the (interfering) write, when the read request is repeated, and the requested data is available in the FIFO the delayed transfer completes normally. All target read accesses are generally prefetching, also reads with I/O command. Once a start address is given, the interface prefetches up to 8 words into the TXMT FIFO. After the last required data word was transferre d to PCI, the PCI core automatically flushes the FIFO to dis card the unused prefetched data. The interface assumes the complete local address space to be ‘prefetchable’, defined here as the fact, that reading from an address does not alter the data. This behaviour is to be consi dered if non-prefetchable devices (for example the UART’s) shall be read through the PCI target. PCI Error Reporting According to the PCI standard, error and status bits are implemented in the PCI status regis - ter.(PCISC). The PCI standard foresees a single parity check, by which bus-errors can be detected, but not corrected. Errors which occur in the PCI interface or on the PCI bus are also saved in status bits in the PCIITP register, and optionally, the PCI interrupt (IRQ14) is asserted. Different events can be selected to assert the interrupt. By the interrupt enable register (PCIITE) configuration you can select the interrupt events which will assert IRQ14. then an interrupt han- dler can read the interrupting event in the status register (PCIITP). Furthermore, interrupts can be forced for test purposes by writing to PCIITF. In host-bridge configuration, this allows an e rror detection by polling. Certain events and errors are also reported by the interface in the interrupt status register. For each bit of this register , interrupt generation can be programmed individualy. All PCI interrupt generated are then reported to AT697 core through the PCI interrupt (IT14). The different interrupt causes are distin guished by the interrupt status registers settings. Please refer to the register description chapter for more details on interrupt status register.

7703C–AERO–6/09 AT697F ADVANCE INFORMATION If used, the parity bit is located between the last data bit and the stop bit of the serial frame. The relation between the parity bit and data bits is as follows: Peven d7 … d3 d2 d1 d0 0 Podd Peven Parity bit using even parity Podd Parity bit using odd parity dn Data bit n of the character Clock Generation The clock generation logic generates the base clock for the Transmitters and Receivers. The bit rate of the UART is issued from the clock generator after a combination between the input clock of the clock module and a scaler. Uart Clock Two clock inputs can be used by the clock generator :

• An internal clock
• An external clock Each UART can be configured to use either the internal or the external clock source by program- ming the UACx JECx. If set l ogical zero, the UART is clocked by the internal clock. If UACxJECx is set logical one, the UART is clocked by the external clock. When using the exter- nal configuration, the UART clock shall be provided by PIO[3] from the general purpose interface. This c lock input is used as an alternate function for PIO[3]. caution : When using the external clock so urce, the frequency of PIO[3] must be less than half the fre - quency of the system clock. Baud Rate Generation To generate the bit-rate, each UART has a pr ogram mable 12-bits clock divider (UASCAx). According to the configuration of the UACxJECx, the scaler is clocked either by the system or b y an external clock. Each time the scaler underflows, a UART tick is ge nerated. The scaler is automatically reloaded with the value of the UART scaler register af ter each underflow. The resulting UART tick fre - quency should be 8 times the desired baud-rate. The following equation shall be used to calculat e the sca ler value to define, depending on the clock source and the expected baud rate. scaler uartclk 10× variable description :
• uar tclk : frequency of the uart clock
• bau drate : expected baud rate
• sc aler : value to set in (UASCAx) to reach the expected baudrate Communication Operations UARTS operations are controlled through the uart control registers (UACx) and the Uart status registers (UASx). Transmitter Operation The transmitter is enabled setting logical one the UA CxJTEx . When ready to transmit, data is transferred from the transmitter holding register to the transmitter shift register and converted to a serial frame on the transmitter serial output pin (TX). Following the transmission of the stop bit, if a new character is not avail able in the transmitter holding register, the transmitter serial data out put remains high and the transmitter shift register

AT697F ADVANCE INFORMATION 7703C–AERO–6/09 empty bit UASxJTSx. Transmission resumes and the UASxJTSx is cleared when a new char - acter is loaded in the transmitter holding register. If the transmitter is disabled, it will continue operating until the character currently being transmit- ted is completely sent out. The transmitter holding register cannot be loaded when the transmitter is disabled. If flow control is enabled, the CTS input must be low in order for the character to be transmitted. If it is deasserted in the middle of a transmission, the character in the shift register is transmitted and the transmitter serial output then remains inac tive until CTS is asserted again. If the CTS is connected to a receivers RTS, overrun can effectively be prevented. Receiver Operation The receiver is enabled for data reception when the receiver enable bit UACxJREx is set logical one. The receiver looks for a high to low transition of a start bit on the receiver serial data input pin. If a transition is detected, the state of the serial input is sampled a half bit clocks later. If the serial input is sampled high the start bit is invalid and the search for a valid start bit continues. If the serial input is still low, a valid start bit is assumed and the receiver continues to sample the serial input at one bit time intervals until the proper number of data bits and the parity bit have been assembled and one stop bit has been detected. During this process the least significant bit is received first. The serial input is sampled three times for each bit and averaged to filter out noise. The data is then transferred to the receiver holding register and the data ready bit UASxJDRx is set logical one. The parity, framing and overrun er ror bits are set at the received byte boundary, at the same time as the receiver ready bit is set. If both receiver holding and shift registers contain an un-read character when a new start bit is detected, then the character held in the receiver shift register will be lost and the overrun bit UASxJOVx is set logical one. If flow control is enabled, then the RTS will be negated (high) when a valid start bit is detected and the receiver holding register contains an un-read character. When the holding register is read, the RTS will automatically be reasserted again. A correctly received byte is indicated by the data ready bit UASxJDRx. In case of error (framing the data ready bit remains logical zero. Interrupt Generation The two UARTs can be configured to generate interrupt each time a byte is received or a byte is sent. If the UACxJTIx is set logical one, an interrupt is issued after each character sending. If set log- ical zero, no interrupt is issued on character sending. If the UACxJRIx is set logical one, an interrupt is i ssued after each character reception. If set logical zero, no interrupt is issued after a character reception. If the receiver interrupt is enabled, when error is detected during the reception of a character,an interrupt is generated. To identify the origin of the transaction failure, refer to the uart status reg- ister bits (UASxJOVx, UASxJPEx, UASxJTEx) that indicate either it is a parity, a framing or an overrun error. Loop back mode If the UACxJLBx is set, the UART will be in loop back mode. In this mode, the transmitter output is internally connected to the receiver input and the RTS is connected to the CTS. It is then pos- sible to perform loop back tests to verify op eration of receiver, transmitter and associated software routines. In this mode, the outputs remain in the inactive state, in order to avoid send - ing out data.

a debug communication link (DCL). simple read/write protocol and uses standard asynchronous UART communications. Figure 38. De bug Support Unit and Communication Link build in as a master on the internal bus. All debug features are available from any PCI master.

• executing a breakpoint instruction (ta 1)
• integer unit hardware breakpoint/watchpoint hit (trap 0x0B)
• rising edge of the external break signal (DSUBRE)
• setting the break-now DSUC JBN
• a trap that would cause the processor to enter error mode
• occurrence of any, or a selection of traps as defined in the DSU control register
• after a single-step operation
• DSU breakpoint hit The debug mode can only be entered when the debug support unit is enabled through an exter - nal pin (DSUEN). Driving the DSUEN pin high ena bles the debug mode. When the debug mode is entered, the following actions are taken:
• PC and nPC are saved in temporary registers (accessible by the debug unit)
• an output signal (DSUACT) is asse rte d to indicate the debug state

AT697F ADVANCE INFORMATION 7703C–AERO–6/09

• the timer unit is (optionally) stopped to freeze the AT697 timers and watchdog The instruction that caused the processor to enter debug mode is not executed, and the proces- sor state is kept unmodified. Execution is resumed by clearing the DSUC JBN or by de- asserting DSUEN. The timer unit will be re-enabl ed and execution will continue from the saved PC and nPC. Debug mode can also be entered after the processor has entered error mode, for instance when an application has terminated and hal ted the processor. The error mode can be reset and the processor restarted at any address. DSU Breakpoint The DSU contains two breakpoint registers for matching either internal bus addresses or exe - cuted processor instructions. A breakpoint hit is typically used to freeze the trace buffer, but can also put the processor in debug mode. Freeze operation can be delayed by programming the DSUCJDCNT to a non-zero value. In this case, the DSUC JDCNT value will be decremented for each additional trace until it reaches zero, after which the trace buffer is frozen. If the brake on trace freeze bit DSUCJBT is set logi- cal one, the DSU forces the processor into debug mode when the trace buffer is frozen. Note: Due to pipeline delays, up to 4 additional in struction can be executed before the processor is placed in debug mode. A mask register is associated with each break point, allowing breaking on a block of addresses. Only address bits with the corresponding mask bit set to ‘1’ are compared during breakpoint detection. Time Tag The DSU implements a time tag counter. This counter is decremented each clock as long as the processor is running. The counter is stopped when the processor enters debug mode. It is restarted when execution is resumed. This time tag counter is stored in the trace as an execution time reference. Trace Buffer The trace buffer consists of a circular buffer that stores the executed instructions or the internal bus data transfers. The size of the tr ace buffer is 512 lines of 16 bytes . The trace buffer opera - tion is controlled through the DSU control register (DSUC) and the trace buffer control register (TBC). When the processor enters debug mode, tracing is suspended. The trace buffer can contain the ex ecuted instructions, the transfers on the internal bus or both (mixed-mode). The trace buffer control regi ster (TBC) contains two counters TBC JBCNT and TBCJICNT that store the address of the trace buffer location that will be written on next trace. Since the buffer is circular, it actually points to the oldest entry in the buffer. The indexes are automatically incremented after each stored trace entry. Instruction trace The instruction trace mode is enabled setting logical one the trace instruction enable bit TBCJTI. During instruction tracing, one instruction is stored per line in th e trace buffer with the exception of multi-cycle instructions. Multi-cycle instructions can be entered two or three times in the trace buffer :
• For store instructions, bits [63:32] correspond to the store address on the first entry and to the stored data on the second entry (and third in case of STD). Bit 126 is set logical one on the second and third entry to indicate this.
• A double load (LDD) is entered twice in the trace buffer, with bits [63:32] containing the loaded data.
• Multiply and divide instructions are entered twice, but only the last entry contains the result. Bit 126 is set for the second entry.
• For FPU operation producing a double-precision result, the first entry puts the MSB 32 bits of the results in bit [63:32] while the second entry puts the LSB 32 bits in this field.

Table 21. Trace buffer data allocation, Instruction tracing mode 127 Instruction breakpoint hit Set to ‘1’ if a DSU instruction breakpoint hit occurred.

126 Multi-cycle instruction Set to ‘1’ on the second and third instance of a multi-cycle

33 Instruction trap Set to ‘1’ if traced instruction trapped

32 Processor error mode Set to ‘1’ if the traced instruction caused processo r error mode

When a trace is frozen, interrupt 11 is generated. Bus Trace The bus trace mode is enabled setting logical one the trace instruction enable bit TBCJTA. During bus tracing, one operation of the internal bus is stored per line in the trace buffer. 127 AHB breakpoint hit Set to ‘1’ if a DSU AHB breakpoint hit occurred.

79 Hwrite AHB HWRITE

66 Hmastlock AHB HMASTLOCK

high, while the MSB of the instruction index counter is kept low.

AT697F ADVANCE INFORMATION 7703C–AERO–6/09 DSU Memory Map Table 23. Address Register 0x800000c4 DSU UART status register 0x800000c8 DSU UART control register 0x800000cc DSU UART scaler register 0x90000000 DSU control register 0x90000004 Trace buffer control register 0x90000008 Time tag counter 0x90000010 AHB break address 1 0x90000014 AHB mask 1 0x90000018 AHB break address 2 0x9000001C AHB mask 2 0x90010000 - 0x90020000 Trace buffer ..0 Trace bits 127 - 96 ...4 Trace bits 95 - 64 ...8 Trace bits 63 - 32 ...C Trace bits 31 - 0 0x90020000 - 0x90040000 IU/FPU register file 0x90080000 - 0x90100000 IU special purpose registers 0x90080000 Y register 0x90080004 PSR register 0x90080008 WIM register 0x9008000C TBR register 0x90080010 PC register 0x90080014 NPC register 0x90080018 FSR register 0x9008001C DSU trap register 0x90080040 - 0x9008007C ASR16 - ASR31 (when implemented) 0x90100000 - 0x90140000 Instruction cache tags 0x90140000 - 0x90180000 Instruction cache data 0x90180000 - 0x901C0000 Data cache tags 0x901C0000 - 0x90200000 Data cache data DSU Map The addresses of the IU/FPU registersis defined according to how many register windows has be en implemented. The registers can be acce ssed at the following addresses (NWINDOWS = number of SPARC register windows = 8):

• % o n: 0x90 020000 + (((psr.cwp * 64) + 32 + n) mod (NWINDOWS*64))
• % l n: 0x90020000 + (((psr.cwp * 64) + 64 + n) mod (NWINDOWS*64))
• % i n: 0x90020000 + (((psr.cwp * 64) + 96 + n) mod (NWINDOWS*64))
• % g n: 0x90 020000 + (NWINDOWS*64) + 128
• % f n: 0 x90020000 + (NWINDOWS*64)

7703C–AERO–6/09 AT697F ADVANCE INFORMATION Debug Operations Instruction Breakpoints To insert instruction breakpoints, the breakpoint instruction (ta 1) should be used. This will leave the four IU hardware breakpoints free to be us ed as data watchpoints. Since cache snooping is only done on the data cache, the instruction cache must be flushed after the insertion or removal of breakpoints. To minimize the influence on exec ution, it is enough to clear the corresponding instruction cache tag (which is accesible through the DSU). The DSU hardware breakpoints should only be used to freeze the trace buffer, and not for soft - ware debugging since there is a 4-cycle delay fr om the breakpoint hit before the processor enters the debug mode. Single Stepping By writing the TBC JSS and reseting the TBC JBN bit, the processor will resume execution for one instruction and then automatically enter debug mode. DSU Trap The DSU trap register (DTR) consists in a read -only register that indicates which SPARC trap type caused the processor to enter debug mode. When debug mode is forced by setting the TBCJBN, the trap type is 0x0B.

DSU communication link consists of a UART connected to the internal bus as a master. Figure 39. DSU Co mmunication Link Block Diagram command consist of a control byte, followed by a 32-bit address, followed by optional write data. Data Frame Data is sent on 8-bit basis. Figure 40. DSU UART Data Frame and the corresponding number of data words is returned. Figure 41. DSU Commands

11 Length -1 Addr[31:24] Addr[7:0]Addr[15:8]Addr[23:16] Data[31:24] Data[7:0]Data[15:8]Data[23:16]Send

10 Length -1 Addr[31:24] Addr[7:0]Addr[15:8]Addr[23:16]Send

UART tick frequency should be 8 times the desired baud-rate.

7703C–AERO–6/09 AT697F ADVANCE INFORMATION If not programmed by software, the baud rate will be automatically be discovered. This is done by searching for the shortest period between two falling edges of the received data (correspond- ing to two bit periods). When three identical two-bit periods has been found, the corresponding scaler reload value is latched into the reload register, and the DSUUC JBL bit is set . If the DSUUCJBL is reset by software, the baud rate discovery process is restarted. The baud-rate discovey is also restarted when a ‘break’ is received by the receiver, allowing to change to baudrate from the external transmitter. For proper baudrate detection, the value 0x55 should be transmitted to the receiver after reset or after sending break. The best scaler value for manually programming th e baudrate can be calculated as follows: scaler = sdclk frequency x 10 baudrate x 8 5 Booting from DSU By asserting DSUEN and DSUBRE at reset time, the processor will directly enter debug mode without executing any instructions. The system c an then be initialised from the communication link, and applications can be downloaded and debugged. Additionally, external (flash) PROMs for standalone booting can be re-programmed.

Overview The AT697 implements a standard interface compliant with the IEEE 1149.1 JTAG specification. This interface can be used for PCB testing using the JTAG boundary-scan capability. constitute the Test Access Port (TAP). The following table summarizes the TAP pins and there function at JTAG level. TDO Test Data Output Output Serial output data from the boundary scan latches. out board-level multiplexing. Figure 42. JTAG Se rial connection using 1 TMS Signal

of shift registers including an instruction register (IR) and some registers . Figure 43. AT 697 TAP Architecture diagram. The IR is a 3-bit register which allows a test instruction to be shifted into the AT697. The instruction selects the test to be performed and the test data register to be accessed.

Figure 44. TAP - State Machine during the scanning of internal chains. TAP Instructions The following instruction are supported by the AT697 TAP. Table 25. TAP inst ruction set

000 EXTEST Boundary scan register Boundary scan chain

001 SAMPLE/PRELOAD Boundary scan register Boundary scan chain

010 BYPASS Bypass register Bypassscan chain

111 IDCODE Device id register ID register scan chain

It is used to speed up shifting at board level thro ugh components that are not to be activated.

AT697F ADVANCE INFORMATION 7703C–AERO–6/09 Boundary Scan Register A single scan chain consisting of all of the boundary scan cells (input, output and in/out cells).

• The purpose of the boundary scan is th e support of scan-based board testing. Boundary Scan register is connected between TDI and TDO. To use the boundary scan feature, the PLL will be in bypass mode, i.e. BYPASS signal direction to VCC. Checker Scan Register A single scan chain consisting of all of the scan cells of IU parity checkers. The checkers scan is only used for factory test. Checkers scan register is connected between TDI and TDO.

7703C–AERO–6/09 AT697F ADVANCE INFORMATION Execution Mode Reset Mode When the RESET input is asserted for at least two cycles, the processor enters reset mode. Under this mode, the CPU and all the peripheral s are halted. Only the following registers are affected by the reset. All other registers maintain their value or are undefined. Table 26. Register Description Reset Value PC program counter 0x0000 0000 nPC new program counter 0x0000 0004 PSR processor status register et = 0 s = CCR cache control register 0x0000 0000 MCFG1JPR WDH PROM bus width PIO[1:0] MCFG3JPE PROM EDAC enable PIO[2] Reset Operation When RESET is deasserted, execution restarts from address 0. Debug Mode Debug mode can be entered when the DSU is enabl ed through the external DSUEN pin. This allows read/write access to all processor r egisters and caches memories. In debug mode, the processor pipeline is held and the processor is controlled by the DSU. Power-down/Idle Mode AT697 can be idled by writing any value to the power-down register. During power-down mode, only the integer unit is halted. All other functions and peripherals operate as nominal. When a single write to the idle register is performed, idle mode is entered on the next load instr uction. Idle mode is terminated when an unmasked interrupt with higher level than the cur - rent processor interrupt level is pending. Th en, the integer unit is re-enabled. Here is a simple example allowing Idle mode entry : ! write any value to Idle register st %g2,[%g1 + 0x18] ! enter Idle mode ld [%o1 + 0x08],%g3

AT697F ADVANCE INFORMATION 7703C–AERO–6/09 System Clock Overview The AT697F clock system is mainly based on tw o main clock trees: the PCI clock and the CPU clock. The following figure presents the clock system of the processor and its distribution. Figure 47. PLL Alternate PCI clock CPU clock CLK BYPASS PDIV4 LOCK UART clock Uart Control Reg. UACn PCI Core SDCLK CPU Core GPITimers Uarts Memory Control PCI Wrapper Interrupt Controller Caches Reg. File Clock Distribution PCI Clock The PCI clock is dedicated to the PCI Interface. It is used in particular by the PCI wrapper that shares its activity between the two clock domains. External Clock The PCI interface and its associated wrapper can only be driven from an external clock. The PCI clock shall be connected to the PCI_CLK pin of th e PCI interface. This input shall be driven at a frequency in the range of 0 up to 33MHz. CPU Clock The CPU clock is routed to the parts of the system concerned with operation of the SPARC core. Examples of such modules are the CPU core itself, the register files... The CPU clock is also used by the majority of the I/O modules like Timers, Memory controller, Interrupt Controller, with the exception of the PCI Interface. The CPU clock is driven either directly by an external oscillator or by the internal PLL. External Clock To drive the device directly from an external clock sou rce, the CLK input shall be driven by an external clock generator while the BYPASS pin is driven high . In that way, the CPU clock is the direct representation of the clock applied to CLK. When the external CPU clock source is selected, the clock inpu t can be driven at a frequency in the range of 0MHz up to 100MHz. PLL Overview The CPU clock can be issued from the inter nal PLL. This PLL contains a phase/frequency detector, charge pump, voltage control oscillator, low pass filter, lock detector and divider.

frequency of the input clock. The following table presents th e assignement and functions of the PLL control signals. Table 27. PLL po rts description frequency of the clock applied to CLK. quency in the range of 18MHz up to 25MHz. (SEU), the AT697F processor is based on full triple modular redundancy (TMR) architecture. Figure 48. TMR struc ture that way, each one of the PCI clock and the cpu clock are build as three-clock trees. are used to program the delay induced by the skew.

• SKEW[1:0] = ’00’ : natural skew corresponding to the intrinsec routage of the chip
• SKEW[1:0] = ’01’ : medium skew ‘artificially’ injected
• SKEW[1:0] = ’10’ : maximum sk ew ‘artificially’ injected The remaining configuration (SKEW[1:0] = ’1 1’) is reserved and must not be used at application level.

Table 28. SKEW assigne ments

7703C–AERO–6/09 AT697F ADVANCE INFORMATION Package MCGA 349 Mechanical Outlines AA2 e min max min max D/E 24,8 25,2 0,976 0,992 D1/E1 A1 1,4 1,85 0,055 0,073 A2 2,4 3,45 0,094 0,136 A 4,3 5,9 0,169 0,232 b 0,79 0,99 0,031 0,04 e 0,9 0,05 inch 22,86 1,27 mm

AT697F ADVANCE INFORMATION 7703C–AERO–6/09 QFP256 package Package

Description

7703C–AERO–6/09 AT697F ADVANCE INFORMATION Registers Table 29. Register legend Table 30. Processor State Register- PSR 31..28 impl[3:0] Implementation or class of implementations of the architecture. indicates whether the ALU result was negative for the last instruction modifying icc field. indicates whether the ALU result was zero for the last instruction modifying i cc field. r the last instruction that modified the icc field. 1 = overflow, 0 = no overflow. 11..8 pil[3:0] identify the interrupt level above which the processor will accept an interrupt. 7 s determines whether the processor is in supervisor or user mo de. 1 = supervisor mode, 0 = user mode. 6 ps contains the value of the S bit at the time of the most recent trap. resumes execution at address 0. 1 = traps enabled, 0 = traps disabled.

Table 32. Y Register - Y The Y register can be read and written with the RDY and WRY instructions. Table 33. T rap Base Address - TBR This field contains the most-significant 20 bit s of the trap table address. provides an offset into the trap table. The tba field is written by the WRTBR instruction. Use of WRTBR is don’t care for tt field. instructions (modulo NWINDOWS). Table 31. Window Invalid Mask - WIM Indicated wether the window is a ‘valid’ or an ‘invalid’ one.

Table 34. Program Counters - PC The 32-bit PC contains the address of the instruction currently being executed by the IU. l1 value is copied back to PC. Table 35. Ne w Program Counters - nPC trap, l2 value is copied back to nPC. Table 36. Wa tch Point Address Registers Table 37. W atch Point Mask registers

Defines which bits are to be compared to waddr. Table 38. Re gister File Protection Control Register 11..9 cnt[2:0] Error counter. This register is accessed using the RDASR/WRASR instructions. Table 39. Window Registers

Table 40. FPU Status register - FSR Defines the rounding direction used by the AT697 FPU dur ing a floating-point arithmetic operation.

AT697F ADVANCE INFORMATION 7703C–AERO–6/09 Trap Types The f tt field can be read by the STFSR instruction. An LDFSR instruction does not affect ftt field. Table 41. TT Name Description 0 none No trap. 1 IEEE_exception An IEEE_754_exception floating-point trap type indicates that a floating-point exception occurred that conforms to the ANSI/IEEE Standard 754-1985. The exception type is encoded in the cexc field. 2 Unfinished_FPop An unfinished_FPop indicates that an implementation’s FPU was unable to generate correct results or exceptions 3 unimplemented_FPop An unimplemented_FPop indicates that an implementation’s FPU decoded an FPop that it does not implement. In this case, the cexc field is unchanged 4 sequence_error A sequence_error indicates one of three abnormal error conditions in the FPU, all caused by erroneous supervisor software: - An attempt was made to execute a floating-point instruction when the FPU was not able to accept one. This type of sequence_error arises from a logic error in supervisor software that has caused a previous floating-point trap to be incompletely serviced (for example, the floating-point queue was not emptied after a previous floating-point exception). - An attempt was made to execute a STDFQ instruction when the floatingpoint deferred-trap queue (FQ) was empty , that is, when FSR.qne = 0. (Note that generation of sequence_error is recommended, but not required in this case) 5 hardware error A hardware_error indicates that the FPU detected a catastrophic in ternal error, such as an illegal state or a parity error on an f register access. If a hardware_error occurs during execution of user code, it may not be possible to recover sufficient state to continue execution of the user application. 6 invalid register An invalid_fp_register trap type indicates that one (or more) operands of an FPop are misaligned, that is, a double- precision register number is not 0 mod 2, or a quadruple-precision register number is not 0 mod 4. It is recommended that implementations generate an fp_exception trap with FSR.ftt = invalid_fp_register in this case, but an implementation may choose not to generate a trap. Trap Type Definition 27..23 tem[4:0] Trap Enable Mask tem field enables trap s caused by FPops. These bits are ANDed with the bits of the cexc (current exception field) to determine whether to force a floating-point exception to IU. All trap enable fields correspond to the similarly named bit in the cexc field. 0 = trap disabled 1 = trap enabled 22 ns Causes the FPU to produce implementati on-defined results that may not correspond to ANSI/IEEE Standard 754-1985. For instance, to obtain higher performance, implementations may convert a subnormal floatingpoint operand or result to zero when NS is set. 19..17 ver[2:0] Identify one or more particular implementations of the FPU architecture. For each SPARC IU implementation there may be one or more FPU implementations, or none. This field identifies the particular FPU implementation present. 16..14 ftt[2:0] Floating point trap type Identify floating-point exception trap types.when floating point exception occur s, the ftt field encodes the type of floating-point exception until an STFSR or another FPop is executed. 11..10 fcc[1:0] Contain the FPU condition codes. These bit s are updated by floating-point compare instructions (FCMP and FCMPE). They are read and written by the STFSR and LDFSR instructions, respectively. FBfcc bases its control transfer on this field. 9..5 aexc[4:0] Accumulate IEEE floating-point exceptions while fp_exception trap s are disabled using the TEM field. After an FPop completes, the TEM and cexc fields are logically anded together. If the result is nonzero, an fp_exception trap is generated; otherwise, the new cexc field is or’d into the aexc field. Thus, while traps are masked, exceptions are accumulated in the aexc field. 4..0 cexc[4:0] Indicate that one or more IEEE floating-point exceptions were generated by the most recently executed FPop instruction. The absence of an exception causes the corresponding bit to be cleared. Bit Number Mnemonic Description

Table 43. Exception Fields nva nvc Invalid An operand is improper for the operation to be performed. 1 = invalid operand, 0 = valid operand(s). Examples : 0 ÷ 0, ∞ − ∞ ar e invalid. normalized number. nxc and nxa are always set as well. smallest normalized number, but the correct rounded result would be the smallest normalized number. X÷0, wh ere X is subnormal or normalized. Note that 0 ÷ 0 does not set the dzc bit. 1 = division-by-zero, 0 = no divi sion-by-zero. nxa nxc Inexact The rounded result of an operation differs from the infinitely precise correct result. 1 = inexact result, 0 = exact result. Table 44. f registers - fx ( 0 < x < 31)

Table 45. Memory Configuration Register 1 - MCFG1 if set, a PROM access will be extended until BRDY* is asserted (driven low). cycles long. Termination of the access after assertion of BRDY* will be delayed by at least one clock cycle. 28:27 iowdh[1:0] I/O bus width. Defines the data with of the I/O area (“00”=8, “10”=32). Bus error enable for RAM, PROM and IO transactions. trap (0x01, 0x09, 0x2B) depending on the type of access. ‘1’ : Read and write accesses to I/O area are enabled. If set, enables write cycles to the prom area.

used to store the EDAC checksums and cannot be used to store instructions or data. and bus ready are disabled. All other fields are undefined. Table 46. Mem If set, the SDRAM refresh will be enabled. tRP will be equal to 2 or 3 system clocks (0/1). 29..27 trfc[2:0] SDRAM tRFC timing. tRF will be equal to 3 + field-value system clocks. issued at the same time. Also sets RAS/CAS delay (tRCD). “11” = LOAD-COMMAND-REGISTER. The field is reset after command has been executed. If set, the SDRAM controller will be enabled. If set together with bit 14 (SDRAM enable), the st atic ram access will be disabled.

Table 47. Memory Configuration Register 3 - MCFG3 26..12 srcrv[14:0] SDRAM refresh counter reload value. memory checkbits during load cycles when RB is set.

Table 48. Wr ite Protection Register 1 - WPR1 Table 49. Write Protection Register 2 - WPR2

Table 50. Write Protection Start Address 1 - WPSTA1 Table 51. Write Protection End Address 1 - WPSTO1 Table 52. Write Protection Start Address 2 - WPSTA2

Table 53. Write Protection End Address 2 - WPSTO2

Table 54. Product Configuration Register - PCR 24..20 nwindows[4:0] Number of register windows. The size (in Kbytes) of the instruction cache. Instruction cache line size. The line size (in 32-bit words) of each line. The size (in kbytes) of the data cache. The line size (in 32-bit words) of each line.

Table 55. Fail Address Register - FAILAR time an error occurs on the internal bus. Table 56. Fail Status Register - FAILSR Set when a correctable EDAC error is detected. Set when a new error occurred. This bit is set if the failed access was a r ead cycle, otherwise it is cleared. 6..3 hmaster[3:0] AHB master. This field contains the HMASTER[3:0] of the failed access. 2..0 hsize[2:0] Transfer Size. This filed contains the HSIZE[2:0] of the failed transfer.

Table 57. Cache Control Register - CCR If set, will enable data cache snooping. If set, will flush the data cache. Always reads as zero. If set, will flush the instruction cache. Always reads as zero. arity bits during diagnostic writes. This bit enables burst fill during instruction fetch. This bit is set when an instruction cache flush ope ration is in progress. This bit is set when an data cache flush operation is in progress. uction cache tag parity error is detected. uction cache data sub-block parity error is detected. a cache tag parity error is detected. If set, the data cache will automatically be frozen when an asynchronous interrupt is taken. If set, the instruction cache will automatically be frozen when a n asynchronous interrupt is taken.

7703C–AERO–6/09 AT697F ADVANCE INFORMATION 1..0 ics[1:0] Instruction Cache state Define the current instruction cache according to the following : “X0” = disabled “01” = frozen “11” = enabled. Set to “00” at reset. Bit Number Mnemonic Description

Table 58. Idle Register - IDLE

Table 59. Timer 1 Counter Register - TIMC1 A read access gives the decounting value of the scaler. Table 60. Timer 1 Reload Register - TIMR1 A write access programs the reload value of Timer 1 counter. Table 61. Timer 1 Control Register - TIMCTR1 If rl1 is set, then the counter will automatically be reloaded w ith the reload value after each underflow.

Table 62. Watchdog Register - WDG 31..0 wdc[31:0] Watchdog counter. Fixes the watchdog ’Timeout’. Timeout’ is greater than ’Timeout’. Table 63. Timer 2 Counter Register - TIMC2 A read access gives the decounting value of the scaler. Table 64. Timer 2 Reload Register - TIMR2 A write access programs the reload value of Timer 1 counter.

Table 65. Timer 2 Control Register - TIMCTR2 If rl2 is set, then the counter will automatically be reloaded w ith the reload value after each underflow. Table 66. Prescaler Counter Register - SCAC A read access gives the decounting value of the prescaler. Table 67. Prescaler Reload Register - SCAR A write access programs the reload value of the prescaler. A read access gives the reload value of the prescaler. and leads to a division rate of 4.

Table 68. UART 1 Data Register - UAD1

• A write access enables the sending of the written 8-bit data on UART 1.
• A read access provides the received 8-bit data on UART1.

Table 69. UART 1 Status Register - UAS1 Indicates that a framing error was detected. indicates that a parity error was detected. Indicates that one or more character have been lost due to overrun. Indicates that a BREAK has been received. Indicates that the transmitter hold register is empty. Indicates that the transmitter shift register is empty. Indicates that new data is available in the receiver holding register. Table 70. UART 1 Control Register - UAC1

If set, loop back mode will be enabled. If set, enables flow control using CTS/RTS. If set, enables parity generation and checking. If set, enables generation of transmitter interrupt. If set, enables generation of receiver interrupt. If set, enables the transmitter. If set, enables the receiver. Table 71. UART 1 Scaler Register - UASCA1 Table 72. UART 2 Data Register - UAD2 A write access enables the sending of the written 8-bit data on UART 2. A read access provides the received 8-bit data on UART2.

Table 73. UART 2 Status Register - UAS2 Indicates that a framing error was detected. indicates that a parity error was detected. Indicates that one or more character have been lost due to overrun. Indicates that a BREAK has been received. Indicates that the transmitter hold register is empty. Indicates that the transmitter shift register is empty. Indicates that new data is available in the receiver holding register. Table 74. UART 2 Control Register - UAC2 If set, loop back mode will be enabled. If set, enables flow control using CTS/RTS. If set, enables parity generation and checking. If set, enables generation of transmitter interrupt.

If set, enables generation of receiver interrupt. If set, enables the transmitter. If set, enables the receiver. Table 75. UART 2 Scaler Register - UASCA2

Table 76. Interrupt Mask and Priority Register - ITMP indicates whether an interrupt belongs to priority level 1 ( ilevel[n]=1) or level 0 (ilevel[n]=0). After reset, the interrupt mask register is set to all ze ros while the remaining control registers are undefined. Table 77. Interrupt Pending Register - ITP When the IU acknowledges the interrupt, the corresponding pending bit is automatically cleared. Table 78. In terrupt Force Register - ITF

Table 79. Interrupt Clear Register - ITC If written with a ‘1’, will clear the corresponding bit(s) in the interr upt pending register. Table 80. Secondary Interrupt Mask Register - SITM After reset, the interrupt mask register is set to all ze ros while the remaining control registers are undefined. Table 81. Second ary Interrupt Pending Register - SITP Table 82. Second ary Interrupt Status Register - SITS

If set, then irl[4:0] is valid. If cleared, no unmasked interrupt is pending. Indicates the highest unmasked pending interrupt. Table 83. Secondary Interrupt Clear Register - SITC if written with a ‘1’, will clear the correspo nding bit(s) in the interrupt pending register.

Table 84. I/O Port Data Register - IODAT Table 85. I/O Por t Direction Register - IODIR Defines the direction of I/O ports 15 - 0. Table 86. I/O Port Interrupt Register - IOIT1

If set, the corresponding interrupt will be enabled, otherwise it will be masked. 30 le3 Level/edge triggered. If set, the interrupt will be edge-triggered, otherwise level sensitive. active low (or edge-triggered on negative edge). 28..24 isel3[4:0] I/O port select. The value of this field defines which I/O port (0 - 3 1) should generate parallel I/O port interrupt 3. If set, the corresponding interrupt will be enabled, otherwise it will be masked. 22 le2 Level/edge triggered. If set, the interrupt will be edge-triggered, otherwise level sensitive. active low (or edge-triggered on negative edge). 20..16 isel2[4:0] I/O port select. The value of this field defines which I/O port (0 - 3 1) should generate parallel I/O port interrupt 2. If set, the corresponding interrupt will be enabled, otherwise it will be masked. 14 le1 Level/edge triggered. If set, the interrupt will be edge-triggered, otherwise level sensitive. active low (or edge-triggered on negative edge). 12..8 isel1[4:0] I/O port select. The value of this field defines which I/O port (0 - 3 1) should generate parallel I/O port interrupt 1. If set, the corresponding interrupt will be enabled, otherwise it will be masked. If set, the interrupt will be edge-triggered, otherwise level sensitive. active low (or edge-triggered on negative edge). 4..0 isel0[4:0] I/O port select. The value of this field defines which I/O port (0 - 3 1) should generate parallel I/O port interrupt 0. Table 87. I/O Port Interrupt Register - IOIT2

Bit Number Mnemonic Description 31 en7 Enable. If set, the corresponding interrupt will be enabled, otherwise it will be masked. 30 le7 Level/edge triggered. If set, the interrupt will be edge-triggered, otherwise level sensitive. 29 pl7 Polarity If set, the corresponding interrupt will be active high ( or edge-triggered on positive edge). Otherwise, it will be active low (or edge-triggered on negative edge). 28..24 isel7[4:0] I/O port select. The value of this field defines which I/O port (0 - 3 1) should generate parallel I/O port interrupt 7. 23 en6 Enable. If set, the corresponding interrupt will be enabled, otherwise it will be masked. 22 le6 Level/edge triggered. If set, the interrupt will be edge-triggered, otherwise level sensitive. 21 pl6 Polarity If set, the corresponding interrupt will be active high ( or edge-triggered on positive edge). Otherwise, it will be active low (or edge-triggered on negative edge). 20..16 isel6[4:0] I/O port select. The value of this field defines which I/O port (0 - 3 1) should generate parallel I/O port interrupt 6. 15 en5 Enable. If set, the corresponding interrupt will be enabled, otherwise it will be masked. 14 le5 Level/edge triggered. If set, the interrupt will be edge-triggered, otherwise level sensitive. 13 pl5 Polarity If set, the corresponding interrupt will be active high ( or edge-triggered on positive edge). Otherwise, it will be active low (or edge-triggered on negative edge). 12..8 isel5[4:0] I/O port select. The value of this field defines which I/O port (0 - 3 1) should generate parallel I/O port interrupt 5. 7 en4 Enable. If set, the corresponding interrupt will be enabled, otherwise it will be masked. 6 le4 Level/edge triggered. If set, the interrupt will be edge-triggered, otherwise level sensitive. 5 pl4 Polarity If set, the corresponding interrupt will be active high ( or edge-triggered on positive edge). Otherwise, it will be active low (or edge-triggered on negative edge). 4..0 isel4[4:0] I/O port select. The value of this field defines which I/O port (0 - 3 1) should generate parallel I/O port interrupt 4. 108 7703C–AERO–6/09 AT697F ADVANCE INFORMATION

Table 88. PCI Device Identification Register 1 - PCIID1 31..16 device id [15:0] This field identifies the particula r device. This identifier is allocated by the vendor. ensure uniqueness. 0FFFFh is an invalid value for Vendor ID. Table 89. PCI Status - Command Register - PCISC controlled by bit 6 in the Command register). Master has terminated master abort. Master-Abort. All master devices must implement this bit. devices must implement this bit. never signal Target-Abort do not need to implement this bit. These bits encode the timing of DE VSEL*. Three allowable timings for assertion of DEVSEL* are specified. Read and Configuration Write.

7703C–AERO–6/09 AT697F ADVANCE INFORMATION 24 stat8 Master received/asserted PERR This bit is only implemented by bus masters. It is set when three conditions are met: 1) the bus agent asserted PERR* itself (on a read) or observed PERR* asserted (on a write); 2) the agent setting the bit acted as the bus master for the operation in which the error occurred; 3) the Parity Error Response bit (Command register) is set. 23 stat7 Target supports fast back2back This optional read-only bit indicates whether or not the target is capable of accepting fast back-to-back transactions when the transactions are not to the same agent. This bit can be set to 1 if the device can accept these transactions and must be set to 0 otherwise. 22 stat6 User definable features 21 stat5

66 MHz capabality

This optional read-only bit indicates whether or not this device is capable of running at 66 MHz as defined in Chapter 7. A value of zero indicates 33 MHz. A value of 1 indicates that the device is 66 MHz capable 20 stat4 Power management capability. This optional read-only bit indicates whether or not this device implements the pointer for a New Capabilities linked list at offset 34h. A value of zero indicates that no New Capabilities linked list is available. A value of one indicates that the value read at offset 34h is a pointer in Configuration Space to a linked list of new capabilities. 10 com10 Interrupt command. This bit disables the device/function from asserting INTx*. A value of 0 enables the assertion of its INTx* signal. A value of 1 disables the assertion of its INTx* signal. This bit’s state after RST* is 0. 9 com9 Master can generate fast back2back. This optional read/write bit controls whether or not a master can do fast back-to-back transactions to different devices. Initialization software will set the bit if all targets are fast back-to-back capable. A value of 1 means the master is allowed to generate fast back-to-back transactions to different agents. A value of 0 means fast back- to-back transactions are only allowed to the same agent. This bit's state after RST* is 0. 8 com8 Enable SERR driver -This bit is an enable bit for the SERR* driver. A value of 0 disables the SERR* driver. A value of 1 enables the SERR* driver. This bit's state after RST* is 0. All devices that have an SERR* pin must implement this bit. Address parity errors are reported only if this bit and bit 6 are 1. 7 com7 Address/Data stepping on PCI bus 6 com6 Enable Parity Check This bit controls the device's response to parity errors. When the bitis set, the device must take its normal action when a parity error is detected. When the bit is 0, the device sets its Detected Parity Error status bit (bit 15 in the Status register) when an error is detected, but does not assert PERR* and continues normal operation. This bit's state after RST* is 0. Devices that check parity must implement this bit. Devices are still required to generate parity even if parity checking is disabled. 5 com5 VGA palette snooping This bit controls how VGA compatible and graphics devices handle accesses to VGA palette registers. When this bit is 1, palette snooping is enabled (i.e., the device does not respond to palette register writes and snoops the data). When the bit is 0, the device should treat palette write accesses like all other accesses. VGA compatible devices should implement this bit. 4 com4 Enable memory write and invalidate. This is an enable bit for using the Memory Write and Invalidate command. When this bit is 1, masters may generate the command. When it is 0, Memory Write must be used instead. State after RST* is 0. This bit must be implemented by master devices that can generate the Memory Write and Invalidate command. 3 com3 Enable special cycles Controls a device's action on Special Cycle operations. A value of 0 causes the device to ignore all Special Cycle operations. A value of 1 allows the device to monitor Special Cycle operations. State after RST* is 0. 2 com2 Enable PCI master Controls a device's ability to act as a master on the PCI bus. A value of 0 disables the device from generating PCI accesses. A value of 1 allows the device to behave as a bus master. State after RST* is 0. 1 com1 Enable target memory command response Controls a device's response to Memory Space accesses. A value of 0 disables the device response. A value of 1 allows the device to respond to Memory Space accesses. State after RST* is 0. Bit Number Mnemonic Description

allows the device to respond to I/O Space accesses. State after RST* is 0. Table 90. PCI Device Identification 2 - PCIID2 upper byte (at offset 0Bh) is a base class code which broadly classifies the type of function the device performs. The middle byte (at offset 0Ah) is a sub-class code which identifies more specifically the function of the device. independent software can interact with the device. acceptable value. This field should be viewed as a vendor defined extension to the Device ID. Table 91. Bist, Header type, Latency, Cache line size Register - PCIBHLC bist7 : Return 1 if device supports BIST. Retur n 0 if the device is not BIST capable. is not complete after 2 seconds. specific failure codes can be encoded in the non-zero value.

Table 92. Memory Base Address Register 1 - MBAR1 31..4 MEMBAR1[27:0] Memory base address. 2..1 type1[1:0] “00” Base register is 32 bits wide and mapping can be done anywhere in the 32-bit Memory Space. “10” Base register is 64 bits wide and can be mapped anywhere in the 64-bit address space.

Table 93. Memory Base Address Register 2 - MBAR2 31..4 MEMBAR2[27:0] Memory base address. 2..1 type2 “00” Base register is 32 bits wide and mapping can be done anywhere in the 32-bit Memory Space. “10” Base register is 64 bits wide and can be mapped anywhere in the 64-bit address space. Table 94. IO Base Address Register 3 - IOBAR3 31..2 IOBAR[29:0] Memory base address.

Table 95. Subsystem Identification Register - PCISID Table 96. PCI Capabilities Pointer Register - PCICP Table 97. PCI Latency Interrupt Register - PCILI 15..8 intpin[7:0] indicates which interrupt pin the processo r uses - Always 0 due to absence of PCI interrupt management.

Table 98. PCI Retry _trdy - PCIRT Table 99. PCI Configuration Write Register - PCICW Each of the 4 bits is assigned to one 8-bit lane.

• bit ben[3] is applied to Byte 3, the most significant byte (MSB)
• bit ben[2] is applied to Byte 2
• bit ben[1] is applied to Byte 1
• bit ben[0] is applied to Byte 0, the less significant byte (LSB)

Table 100. PCI Initiator Start Address - PCISA [31:0] PCI start address for PCI initiator transactions in APB and DMA mode.

Table 101. PCI Initiator Write Register - PCIIW Each of the 4 bits is assigned to one 8-bit lane.

• bit ben[3] is applied to Byte 3, the most significant byte (MSB)
• bit ben[2] is applied to Byte 2
• bit ben[1] is applied to Byte 1
• bit ben[0] is applied to Byte 0, the less significant byte (LSB)

Table 102. PCI DMA co nfiguration Register - PCIDMA Can be written to 1, if this transaction is to the same target, as the last one. Note: works only, if the core is enabled for back2back mode. 11..8 com[3:0] PCI command to be used in DMA mode. Minimum number of words for the burst. Table 103. PCI Initiator Status Register - PCIIS

Table 104. PCI Initiator Configuration - PCIIC Specifies the two most significant bits of the command used by AHB slave interface. Table 105. PCI Target Page Address Register - PCITPA defines the 8 most significant bit s for the second memory BAR.

Table 106. PCI Target Status-Command Register - PCITSC Table 107. PCI Interrupt Enable Register - PCIITE

Note: 1. Bits are cleared when written with a 1. Writing a 0 to the register has no effect. Table 108. PCI Interrupt Pending Register - PCIITP(1)

Table 109. PCI Interrupt Force Register - PCIITF Table 110. PCI Data Register - PCID

Table 111. PCI Burst End Register - PCIBE Table 112. PCI DMA Address Register - PCIDMAA Table 113. PCI Arbiter Register - PCIA

Table 114. Trace Buffer Control Register - TBC Table 115. DSU Control Register - DSUC if set, will clear the error mode in the processor. If set, the DSU communication link will send a r esponse word after AHB transfer. Indicates when the processor has entered debug mode (read-only). DSU breakpoint is hit and the delay counter is not equal to zero.

fpu_disabled, window_overflow, window_underflow, asynchronous_interrupt, ticc_trap. If set, will force the processor into debug mode when any trap occurs. If set, will force the processor to debug mode when an DSU breakpoint is hit. Force processor into debug mode. If cleared, the pr ocessor will resume execution. If set, debug mode will be forced on a IU watchpoint (trap 0xb). If set, will generate a DSU break condition on trace freeze. Table 116. DSU UART Status Register - DSUUS Indicates that a framing error was detected. Indicates that one or more character have been lost due to overrun. Indicates that the transmitter hold register is empty. Indicates that the transmitter shift register is empty. Indicates that new data is available in the receiver holding register.

Table 117. DSU Trap Register - DTR Table 118. Break Address Register 1 - BAD1 Table 119. Break Mask Register 1 - BMA1

Table 120. Break Address Register 2- BAD2 Table 121. Break Mask Register - BMA2 Table 122. DSU UART Control Register - DSUUC Is automatically set when the baud rate is locked. If set, enables both the transmitter and receiver.

Table 123. DSU UART Scaler Reload Register - DSUUS

AT697F ADVANCE INFORMATION 127 7703C–AERO–6/09

Electrical Characteristics

Electrical Characteristics for this product have not yet been finalized. Please consider all values listed here as preliminary and non contractual Absolute Maximum Ratings Notes: 1. Stresses at or above those listed under “A bsolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifi - cation is not implied. Exposure to absolute ma ximum rating conditions for extended periods may affect device reliability. DC Characteristics Table 124. Symbol Parameter Min Typ Max Unit Test Conditions VDD Core Power Supply 1.65 1.8 1.95 V VCC I/O Power Supply Voltage 3 3.3 3.6 V IILpu Low Level Input Pull-up Current 100 500 uA Vin = VSS IIHpd High Level Input Pull-downCurrent 100 500 uA Vin = VCC (max) IIL Low Level Input Leakage Current -1 1 uA Vin = VSS IIH High Level Input Leakage Current -1 1 uA Vin = VCC (max) IOZ High Impedance Current 100 500 uA Vin = VSS or VCC (max) VIL TTL Low Level Input Voltage 0.8 V VIL CMOS 30%VCC V VIH TTL High Level Input Voltage 2 V VIH CMOS 70%VCC V VOL Low Level Output Voltage 0.4 V VCC = VCC(min) IOL = 2, 4, 8, 16mA VOL pci Low Level Output Voltage for PCI buffers 0.1 VCC V VCC = VCC(min) IOL = 1.5mA VOH High Level Output Voltage VCC - 0.4 V VCC = VCC(min) IOH = 2, 4, 8, 16mA VOH pci High Level Output Voltage for PCI buffers 0.9 VCC V VCC = VCC(min) IOH = 0.5mA ICCSb Standby Current 5 mA VCC = VCC(max) no clock active DC characteristics

may be activated or deactivated.

• Pcore represents the contribute due to the internal activity.
• Pio represents the contribute due to the IO pa ds and output load current, except the PCI bus.
• Ppci represents the contribute due to the PCI pads and output load current. The following table gives the estimated current c onsu mption for different conditions. The values are coming from estimation and calculation and not from real measurement. Table 125. Mode Typical conditions Worst Conditions P Core (1.8V) in W P I/O (3.3V) in W P PCI (3.3V) in W P Core (1.8V) in W P I/O (3.3V) in W P PCI (3.3V) in W Operating Power Dissipation Typical conditions : 25°C, 1.8V core, 3.3V I/O, High I/O and core activity Worst conditions : 125°C, 1.95 V core, 3.6V I/O; High I/O and core activity In idle mode (100 MHz external clock), the core p ower consumption is 0.5W in typical conditions and 0.7W in worst case conditions. Decoupling capacitance Two main frequencies are involved in the AT697 processor environment :
• 33MHz from the PCI interface
• 100MHz from the master clock of the processor ( either from PLL or directly from resonator input) The following hyp othesis is taken for the calculation of the decoupling capacitance :
• 1.5nH is issued from the connec tion of the capacitor to the PCB
• 1.5nH is issued from the cap acitor intrinsic inductance

Figure 50. Capacitor description This hypothesis corresponds to a capacitor connected to two micro-vias on a PCB.

• L : the inductance equivalent to the gl obal inductance on the VSS/VDD (VSS/VCC) line.
• C : the decoupling capacitance.

AT697F ADVANCE INFORMATION 129 7703C–AERO–6/09 For a processor running at 100MHz with a PCI interface at a character istic frequency of 33MHz and con- sidering that power supply pins ar grouped by multiple of four, the decoupling capacitance to set are :

• 33nF for 33MHz decoupling
• 3nF for 100MHz decoupling Parameter Description MAX CIN Standard Input Capacitance 5pF CIO Standard Input/Output Capacitance 5pF CINp PCI Input Capacitance 7pF CIOp PCI Input/Output Capacitance 7pF Capacitance Rating

of this protection is reflected by the timing figures presented in the following tables. The following tables show the timing figures for the skew condition natural and maximum.

• Temperature range : -55°C to 125°C
• Voltage range : – Core: 1.8V +/- 0.15V
• Output load : 30pF

Table 126. AC Characteristics - Natural Skew

AT697F ADVANCE INFORMATION 131 7703C–AERO–6/09 t27 0 PIO[15:0] hold time during load SDCLK + t28 PIO[15:0] hold time during write SDCLK + t101 30 PCI_CLK Period t102 13.5 PCI_CLK Low and High pulse width t110 2 12 A/D[31:0] and C/BE[3:0] output delay PCI_CLK + t111 7 A/D[31:0] and C/BE[3:0] setup time PCI_CLK + t112 0 A/D[31:0] and C/BE[3:0] hold time PCI_CLK + t113 2 11 FRAME*, PAR, PERR*, SERR*, STOP* and DEVSEL* output delay PCI_CLK + t114 2 11 IRDY* and TRDY* output delay PCI_CLK + t115 2 12 REQ* output delay PCI_CLK + t116 7 FRAME*, LOCK*, PAR, PERR*, SERR*, IDSEL*, STOP* and DEVSEL* setup time PCI_CLK + t117 7 IRDY* and TRDY* setup time PCI_CLK + t118 10 GNT* setup time PCI_CLK + t119 0 FRAME*, LOCK*, PAR, PERR*, SERR*, IDSEL*, STOP* and DEVSEL* hold time PCI_CLK + t120 0 IRDY* and TRDY* hold time PCI_CLK + t121 0 GNT* hold time PCI_CLK + Parameter Min (ns) Max (ns) Comment Reference edge (‘+’ for rising edge)

• Temperature range : -55°C to 125°C
• Voltage range : – Core: 1,8V +/- 0,15V
• Output load : 30pF

Table 127. AC Characteristics - Maximum Skew

AT697F ADVANCE INFORMATION 133 7703C–AERO–6/09 t110 2 13 A/D[31:0] and C/BE[3:0] output delay PCI_CLK + t111 7 A/D[31:0] and C/BE[3:0] setup time PCI_CLK + t112 0 A/D[31:0] and C/BE[3:0] hold time PCI_CLK + t113 2 11 FRAME*, PAR, PERR*, SERR*, STOP* and DEVSEL* output delay PCI_CLK + t114 2 11.5 IRDY* and TRDY* output delay PCI_CLK + t115 2 12 REQ* output delay PCI_CLK + t116 7 FRAME*, LOCK*, PAR, PERR*, SERR*, IDSEL*, STOP* and DEVSEL* setup time PCI_CLK + t117 7 IRDY* and TRDY* setup time PCI_CLK + t118 10 GNT* setup time PCI_CLK + t119 0 FRAME*, LOCK*, PAR, PERR*, SERR*, IDSEL*, STOP* and DEVSEL* hold time PCI_CLK + t120 0 IRDY* and TRDY* hold time PCI_CLK + t121 0 GNT* hold time PCI_CLK + Parameter Min (ns) Max (ns) Comment Reference edge (‘+’ for rising edge)

summarize the timing derating versus the load capacitance. Figure 51. Timing derating

AT697F ADVANCE INFORMATION 135 7703C–AERO–6/09 Timing Diagrams - Will be updated for production release Diagram List • Clock Input without PLL

• Clock Input with PLL
• Reset Sequence
• Fetch, Read and Write from/to 32-bit PROM - 0 Waitstate
• Fetch, Read and Write from/to 32-bit PROM - n Waitstates
• Fetch, Read and Write from/to 32-bit PROM - n Waitstates + BRDY*
• Fetch from 8-bit PROM with EDAC disabled - n Waitstates
• Word Write to 8-bit PROM with EDAC disabled - n Waitstates
• Byte and Half Word Write to 8-bit PROM with EDAC disabled - n Waitstates
• Fetch from 8-bit PROM with EDAC enabled - n Waitstates
• Fetch, Read and Write from/to 32-bit SRAM - 0 Waitstate
• Fetch, Read and Write from/to 32-bit SRAM - n Waitstates
• Burst of RAM Fetches and RAM Write Sequence - 0 Waitstate
• Burst of RAM Fetches and RAM Write Sequence - n Waitstates
• SDRAM Read (or Fetch) with Precharge - Burst length = 1; CL = 3
• SDRAM Write with Precharge - Burst length = 1; CL = 3
• Fetch from ROM, Read and Write from/to 32-bit I/O - 0 Waitstate
• Fetch from ROM, Read and Write from/to 32-bit I/O - n Waitstates
• Fetch from ROM, Read and Write from/to 32-bit I/O - n Waitstates + BRDY*

Figure 67. SDRAM Write with Precharge - Burst length = 1; CL = 3

Figure 70. Fetch from ROM, Read and Write from/to 32-bit I/O - n Waitstates +

AT697F with regards to the AT697E. Table 128. Summary of the new/modified features Table 129. Summary of the register changes

AT697F ADVANCE INFORMATION 147 7703C–AERO–6/09 ITMP 0x80000090 bit 31 - IO interrupt 7 priority level bit 29- IO interrupt 6 priority level bit 28 - IO interrupt 5 priority level bit 26 - IO interrupt 4 priority level bit 15 - IO interrupt 7 mask bit 13 - IO interrupt 6 mask bit 12 - IO interrupt 5mask bit 10 - IO interrupt 4mask bit 31 - reserved bit 29 - reserved bit 28 - reserved bit 26 - reserved bit 15 - reserved bit 13 - reserved bit 12 - reserved bit 10 - reserved ITP 0x80000094 bit 15 - IO interrupt 7 pending bit 13 - IO interrupt 6 pending bit 12 - IO interrupt 5 pending bit 10 - IO interrupt 4 pending bit 15 - reserved bit 13 - reserved bit 12 - reserved bit 10 - reserved ITF 0x80000098 bit 15 - IO interrupt 7 force bit 13 - IO interrupt 6 force bit 12 - IO interrupt 5 force bit 10 - IO interrupt 4 force bit 15 - reserved bit 13 - reserved bit 12 - reserved bit 10 - reserved ITC 0x8000009C bit 15 - IO interrupt 7 clear bit 13 - IO interrupt 6 clear bit 12 - IO interrupt 5 clear bit 10 - IO interrupt 4 clear bit 15 - reserved bit 13 - reserved bit 12 - reserved bit 10 - reserved IOIT1 0x800000A8 Renaming of IOIT IOIT IOIT2 0x800000AC IO Port Interrupt Register Configuration of IO interrupt for interrupt 4, 5, 6 and 7 not available PCIID1 0x80000100 device id : 0x1E0F vendor id : 16E3 device id : 0x1202 vendor id : 0x1438 PCIID2 0x80000108 class code : 0xB4000 revision id : 0x10 class code : 0xB revision id : 0x01 PCISID 0x8000012C subsystem id : 0x2103 subsystem vendor id : 0x16E3 subsystem id : 0x1 subsystem vendor id : 0x143E PCIIS 0x80000154 bit 12 - SYSEN* state bit 12 - reserved PCIIC 0x80000158 bit 3 - reserved bit 2 - reserved bit 1 - reserved bit 3 - PERR retry enable bit 2 - Double write configuration bit 1 - Double read configuration PCITSC 0x80000160 bit 8 - force retry bit 8 - reserved TBC 0x90000004 bit 26 - AHB trace buffer freeze bit 26 - reserved Register Address AT697F Description AT697E Description

Table 130. Summary if the pin changes

AT697F ADVANCE INFORMATION 149 7703C–AERO–6/09 Ordering Information Table 131. Part-Number Supply Voltage (core / IOs) Temperature Range Maximum Speed (MHz ) Packaging Quality Flow AT697F-2H-E 1.8V / 3.3V +25°C 100 MCGA349 Engineering Samples AT697F-KG-E 1.8V / 3.3V +25°C 100 MQFP 256 Engineering Samples Possible Order Entries Datasheet Revision History 7703A - 05/08 1. Document creation. 7703B - 12/08 1. ADVANCE INFORMATION DATASHEET Document. 7703C - 6/09 1. AB bit description change 2. Suffix N change to *. 3. modify <xxx> bit in <yyy> in register by <yyy> J<x xx> 4. Replace SYSCLK by SDCLK 5. text and wording modifications

7703C–AERO–6/09 AT697F ADVANCE INFORMATION

7703C–AERO–6/09 AT697F ADVANCE INFORMATION TABLE OF CONTENTS Features 1 AT697F CPU Core 15 Watch Points 20 Traps and Interrupts 21 Memory Interface 26 Cache Memories 43

7703C–AERO–6/09 AT697F ADVANCE INFORMATION Timer Unit 47 General Purpose Interface 49 PCI Arbiter 51 PCI Interface 52 UARTs (UART1 and UART2) 57

7703C–AERO–6/09 AT697F ADVANCE INFORMATION Debug Support Unit - DSU 60 JTAG Interface 67 Execution Mode 72 System Clock 73 Package MCGA 349 76 QFP256 package 77 Registers Description 78

7703C–AERO–6/09 AT697F ADVANCE INFORMATION Electrical Characteristics 127 Differences between AT697F and AT697E 146 Datasheet Revision History 149

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