AT69170E

AT69170E ATMEL | Alldatasheet

Document overview

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Technical content

Features

• 4Mbits x1 Non Volatile Memory Designed to Store Field Programmable Gate Arrays (FPGAs) Configurations
• In-System Programming (ISP) via Two-Wire Bus
• Simple Interface to SRAM FPGAs
• Compatible with Atmel AT40KEL040 and ATF280E FPGAs
• Cascadable Read-back to Support Additional Configurations or Higher-density Arrays
• Low-power RadHard non volatile CMOS process
• Programmable Reset Polarity
• Low-power Dissipation – Active read: 18mW max – Standby mode: 3.6mW max
• High-reliability – Endurance: 50,000 Write Cycles (page mode) – Data Retention: 10 Years
• 4Mbits On-chip Flash Array – 512 bytes Page Write
• No Single Event Latch-up below a LET Threshold of 80MeV/mg/cm 2
• Tested up to a Total Dose of 60KRads (Si) (according to MIL STD 883 Method 1019)
• Operating Range: – Voltage: 3V to 3.6V – Temperature: -55 to +125° C
• Quality Grades: – QML-Q or V – ESCC
• Package: 305 Mils FP18
• Mass: 10 grams 1. Description The AT69170E FPGA configuration memory (configurato r) is an electrically erasable and re-programmable RadHard memory organized as 4Mx 1bit. It is an easy-to-use and cost-effective configuration memory for space F ield Programmable Grid Array (FPGA). It is manufactured with ATMEL 0.18µm low po wer non volatile CMOS RadHard process. It is packaged in a 18-pin 305 Mils wide Flat Pack package. AT69170E uses a simple serial-access procedure to configure one or more FP GA devices. A two wire interface (TWI) is available for memory programming. The user can select the polarity of the reset function by programming a dedicated test sequence. These devices also support a write-protec tion mechanism within its pro- gramming mode. The factory blanks devices to all ‘1’ before shipping. Space FPGA Configuration Memory AT69170E Advanced Information 7752A–AERO–07/07

7752A–AERO–07/07 AT69170E 2. Block Diagram Figure 2-1. AT69170E Block Diagram POWER ON RESET SER_EN WP1 (2) WP2 (2) (1)READY (2)

7752A–AERO–07/07 AT69170E 3. Pin Configuration

3.1 Package Description

The AT69170E is packaged in a 18-pins Flat Pack package. Figure 3-1. AT69170E pin assignment in FP18 package Note: 1. The package lid is connected to GND

3.2 Signal Description

Table 3-1. Signal Description - Overview Pin Name Function RESET /OE Reset / Output Enable Input CE Chip Enable Input A2/CEO Device Select/ Chip Enable Output CLK Clock Input DATA Data Output READY Reset State Indicator Output SER_EN Serial Enable Input PWD Power Down Input GND Ground VDD Power Supply

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3.2.1 RESET /OE

Reset / Output Enable input The logic polarity of this input is programmable as either RESET /OE or RESET /OE . For ATMEL FPGA, RESET should be programmed active Low and OE active High. This document therefore describes the pin as RESET /OE . The RESET /OE pin of the memory is by default RESET (active Low) and Output Enable (active High) when SER_EN is High. A Low level on RESET /OE resets both the address and bit counters. A High level on RESET /OE (with CE Low) enables the data output driver.

3.2.2 SER_EN

Serial mode Enable (active Low). Serial mode Enable is held High during FPGA loading operations. Bringing SER_EN Low enables the Two-Wire Serial Programming Mode. For a pplications not using the serial mode, SER_EN should be tied to V DD . 3.2.3 CE Chip Enable input (active Low). A Low level (with OE High) allows CLK to increment the address counter and enables the data output driver. A High level on CE disables both the address and bit counters and for ces the device into a low-power standby mode. Note that this pin will not enable/disable the device in the Two-Wire Serial P rogramming mode (when SER_EN Low).

3.2.4 A2/CEO

A2 Device selection input/Chip Enable Output (active Low). A2 Device selection input is used to enable (or select) the device during programming (i.e. when SER_EN is Low). A2 has an internal pull-down resistor. Chip Enable Output (active Low). This output goes L ow when the address counter of the mem- ory has reached its maximum value. In a daisy chain of AT69170E EEPROM, the CEO pin of one device must be connected to the CE input of the next device in the chain. CEO will stay Low as long as CE is Low and OE is High. It will then follow CE until OE goes Low. Thereafter, CEO will stay high until the entire EEPROM is read again.

3.2.5 CLK

Clock input. The clock input is used to increment the internal a ddress and bit counter for reading and programming.

3.2.6 DATA

The DATA I/O is a three-state output for FPGA configuration. It is an open-collector bi-directional pin for programming.

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3.2.7 READY

Open collector reset state indicator (output). The READY line is driven Low during power-up reset. It is then released when power-up is com- plete. It is recommended to use a 4.7 k Ω pull-up resistor when this pin is used.

3.2.8 PWD

Power Down input (active high) Driving High the PWD input pin of the memory reduces the memory power consumption down to less than 1mA. For normal operation of the memory, PWD pin shall be tied to a Low level.

3.2.9 VDD

Power supply input pin.

3.2.10 GND

Ground pin. A 0.2 µF decoupling capacitor between VDD and GND i s recommended.

7752A–AERO–07/07 AT69170E 4. Power-on mode The AT69170E provides a READY output pin to indicate that the memory power-on sequence is ended and that it is ready for use. This pin is ava ilable as an open-collector indicator of the device’s reset status. It is driven Low while the device is in its power-on reset cycle and released (tri-stated) when the cycle is complete. It is recommended to pull-up this pin through a 4.7KOhms resistor. 5. Standby mode The AT69170E configurator enters a low-power standb y mode whenever CE is asserted High. In this mode, the output remains in a high-impedanc e state regardless of the state of the OE input. Power Consumption is reduced to less than 5mA of current at 3.3V. 6. Power down mode In addition to the standby mode, the AT69170E imple ments a power down mode. In this mode, the AT69170E consumes less than 1mA of current at 3.3V. The power down mode is entered driving High the PWD input pin of the memory. For normal operation of the memory, PWD pin shall be tied to a Low level. 7. Programming mode - TWI mode The AT69170E is a serial EEPROM memory used to load programmable devices. AT69170E content is loaded and read thanks to a simple 2-wir e serial interface (TWI). The programming mode is entered if SER_EN is driven Low. In this mode the chip can be progra mmed by the Two-Wire serial interface (TWI). The 2-wire interface (TWI) is based on a simple syn chronous protocol where one wire (CLOCK) functions as a clock and shall be provided by the p rogrammer and the second wire (DATA) is a bi-directional signal and is used to provide data a nd control information. The system must pro- vide a small pull-up current for the DATA line. Information is transmitted on the serial bus in frames made of:

• A Start Condition
• A Data field with Acknowledge bits
• A Stop Condition Each frame begins with a Start Condition and is end ed with a Stop Condition. The data field is made of an integer number of data bytes, each data byte consisting of 8 data bits followed by a 9th Acknowledge Bit. This Acknowledge Bit is provided by the recipient of the transmitted byte.

7.1 TWI Frame Description

While writing to the AT69170E, the programmer is re sponsible for issuing the instruction and data. The AT69170E acknowledges the transfer. While reading from the AT69170E, the pro- grammer issues the instruction and acknowledges the data from the memory as necessary. Data on the DATA pin may change only during the CLO CK Low time; whereas Start and Stop Conditions are identified as transitions during the CLOCK High time. All bytes from accepted messages must be terminated by either an Acknowledge Bit or a Stop Condition.

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7.1.1 Start and Stop Conditions

The Start Condition is indicated by a high-to-low t ransition of the DATA line when the CLOCK line is High. The Start Condition will return the device to the state where it is waiting for a Device Address. The Stop Condition is generated by a low-to-high tr ansition of the DATA line when the CLOCK line is High. The Stop Condition initiates an inter nally timed write signal whose maximum dura- tion is T WR (refer to the AC Characteristics tables for actual value). During this time, the Configurator must remain in programming mode (i.e., SER_EN is driven Low). DATA and CLOCK lines are ignored until the cycle is completed. Figure 7-1. Start and Stop Conditions

7.1.2 Data Field Format

The data field consists of an integer number of byt es, each byte consisting of 8 bits of data, fol- lowed by a 9th Acknowledge Bit. This Acknowledge Bi t is provided by the recipient of the transmitted data byte. Data on the DATA pin may change only during the CLOCK Low time. The data field of the TWI frame is used to transmit addresses and data. Depending on the type of the byte transferred, bit ordering differs.

7.1.2.1 Device Address Byte

For the Device Address Byte, the most significant bit (MSB) of the data byte is the first bit transmitted on the DATA line. The least significant bit (LSB) is the last bit transmitted. The Device address byte is defined as follow: Table 7-1. Device Address Byte The A2 bit is provided to allow selection of a memo ry in case multiple AT69170E share a com- mon bus. When the A2 pin of the device is driven hi gh (1) , A2 bit shall be set logical ‘1’ in the command issued to the memory in order to select it. When A2 pin is driven low (1) , A2 bit shall be set logical ‘0’ in the command. 8th BIT STOP Condition Byte n CLOCK DATA START Condition t WR ACK BIT TWR Bit number MSB - 7 6 5 4 3 2 1 LSB - 0 value 1 0 1 0 A2 1 1 R/W transfer order 1st 2nd 3rd 4th 5th 6th 7th 8th

7752A–AERO–07/07 AT69170E The R/W bit is used to define the type of transfer. It sha ll be set logical ‘1’ for a read operation and logical ‘0’ for a write operation. Note: 1. A2 pin on the Configurator must be forced to a logic “0” or “1” level. It is recommended that this pin is connected to GND or VDD using a 4.7 k Ω pull resistor.

7.1.2.2 EEPROM Address Bytes

The AT69170E EEPROM Address consists of three bytes . These bytes define the normal address space of the memory. Unused bits in an Address Byte must be set to “0” For each byte of the EEPROM Address Bytes, the most significant bit (MSB) of the data byte is the first bit transmitted on the DATA line. The least signif icant bit (LSB) is the last bit transmitted. Address Bytes are transmitted on the data line star ting from the most significant byte and finish- ing with the least significant byte. The EEPROM address being built of more than one byt e, each byte of the address is acknowl- edged by the memory. Each Address Byte is followed by an Acknowledge Bit from the EEPROM. Table 7-2. EEPROM Address The EEPROM address shall be aligned on a multiple o f 4 bytes (A1 =0 and A0=0) for all read/write operations. Exceptions to this are

• Data Protection configuration
• RESET Polarity configuration
• Erase command See the description of each special command for address specific definition

7.1.2.3 Data Bytes

For Data Bytes (both writing and reading), the first bit transmitted is the least significant bit. Table 7-3. Data Byte MSB LSB ACK MSB LSB ACK MSB LSB ACK 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 0 0 0 0 A 18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 0 0 1st 2nd 3rd 4th 5th 6th 7th 8th 9th 1st 2nd 3rd 4th 5th 6th 7th 8th 9th 1st 2nd 3rd 4th 5th 6th 7th 8th 9th Bit number MSB - 7 6 5 4 3 2 1 LSB - 0 value x x x x x x x x transfer order 8th 7th 6th 5th 4th 3rd 2nd 1st

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7.1.2.4 Acknowledge Bit

The Acknowledge Bit is asserted on the DATA line by the receiving device on a byte-by-byte basis. The Acknowledge (ACK) bit is provided by the memory itself when the programmer is writing to the memory. It is provided by the programmer when t he programmer is reading from the memory. A data byte is accepted by the receiver by assertin g a Low value on the DATA line, or it is refused by asserting a High value on the DATA line.

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7.2 TWI Operations

7.2.1 Write Operation

Writing to the AT69170E is based on a 512 bytes page write operation . The AT69170E implements 1024 pages of 512 bytes that can be written one after the other. The AT69170E is based on a 4-byte Word architecture . This is the reason why the number of byte written must be a multiple of 4 (an integer nu mber of Word). From 4 bytes up to 512 bytes can be written in a single write sequence. Write operation through the TWI interface is entered by bringing SER_EN Low. The first data Word (4 data bytes) is written at the transmitted address. The least significant byte of the Word is transmitted first. The last byte of a Word driven on the DATA line is the most sig- nificant Byte. The address is incremented in the memory following the receipt of each Word. Only the lower bits of the address are incremented. Thus, after wr iting to the last byte address within the given page, the address will roll over to the first byte address of the same page. Writing can start at any aligned address (i.e.: A1=0 and A0=0) within a page. Writing to the AT69170E memory consists of

• a Start Condition
• a Device Address Byte with R/W = 0 – an Acknowledge Bit from the Configurator
• MS Byte of the EEPROM Address – an Acknowledge Bit from the Configurator
• (Next) Byte of the EEPROM Address – an Acknowledge Bit from the Configurator
• LS Byte of EEPROM Address double word aligned – an Acknowledge Bit from the Configurator
• 4n Data Bytes (sent to the Configurator) – each byte followed by an Acknowledge Bit from the Configurator
• a Stop Condition Here is an overview of the write instruction frame. Figure 7-2. Write Instruction Frame START CONDITION DEVICE MS EEPROM (next) EEPROM DATA DATA STOP ADDRESS ADDRESS BYTE ADDRESS BYTE CONDITION ... ACK BIT (from configurator) LS EEPROM ADDRESS BYTE BYTE 1 BYTE 4n

7752A–AERO–07/07 AT69170E Here is a summary of the process a programmer shall use to program one page in the memory. Figure 7-3. Page Programming Summary - TWI Write

7.2.1.1 Write polling

On receipt of the Stop Condition, the Configurator enters an internally-timed write cycle. While the Configurator is busy with this write cycle, it will not acknowledge any transfers. The programmer can start the next page write by sen ding the Start Condition followed by the Device Address. As long as the internal write cycle is not ended, the AT69170E does not acknowledge the Device byte. Then the programmer sh ould abandon the transfer without asserting a Stop Condition. The programmer can then repeatedly initiate a write instruction as above, until an acknowledge is received. When the Acknowledge Bit is received, the write instruction should continue by sending the first EEPROM Address Byte to the Configurator. C_ACK? START Send Start Condition Send Stop Condition Send Device Address R/W=0 Send MSB of EEPROM Address Send 2 nd Byte of Start Condition Send LSB of EEPROM Address Yes C_ACK? C_ACK? C_ACK? Yes Yes No No No Send Data Byte C_ACK? No Last Byte ? Yes No No END C_ACK : Configurator send Acknowledge

7752A–AERO–07/07 AT69170E An alternative to write polling would be to wait a period of t WR before sending the next page of data or exiting the programming mode. All signals m ust be maintained during the entire write cycle. Figure 7-4. Write Polling Summary - TWI Polling

7.2.2 Read Operation

Read instructions are initiated similarly to write instructions, but the R/W bit in the Device Address is set logical one. There are three variants of the read instruction: current address read, random read. For all reads, it is important to understand that the internal Data Byte address counter maintains the last address accessed during the previous read or write operation, incremented by one. This address remains valid between operations as long as the chip power is maintained and the device remains in 2-wire access mode (i.e., SER_EN is driven Low). If the last operation was a read at address n, then the current address would be n + 1. If the final operation was a write at address n, then the current address would again be n + 1 with one exception. If address n was the last byte address in the page, the incremented address n + 1 would “roll over” to the first byte address on the next page.

7.2.2.1 Current address read

The current address read is the command used to rea d the memory starting from the address currently latched in the internal address counter. There is no need to transmit any address in the command sent by the programmer. After the programmer receives a Data Byte, it shall respond with either an Acknowledge Bit or a Stop condition. As long as the Configurator receive s an Acknowledge Bit, it will continue to increment the Data Byte address and serially clock out sequential Data Bytes until the memory address limit is reached. The Sequential Read instr uction is terminated when the programmer C_ACK? Send Start Condition Send Device Address R/W=0 Yes No START Write operation Ended END C_ACK : Configurator send Acknowledge

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7.2.2.2 Random read

The random read is the command used to read the mem ory starting from the address given in the command send by the programmer. The address pro vided by the programmer in the com- mand must be aligned (A1=0 and A0=0). After the programmer receives a Data Byte, it shall respond with either an Acknowledge Bit or a Stop condition. As long as the Configurator receive s an Acknowledge Bit, it will continue to increment the Data Byte address and serially clock out sequential Data Bytes until the memory address limit is reached. The Sequential Read instr uction is terminated when the programmer does not respond with an Acknowledge Bit, but instead generates a Stop Condition following the receipt of a Data Byte. A Random Address Read instruction consists of

• a Start Condition
• a Device Address with R/W = 0 – an Acknowledge Bit from the Configurator
• MS Byte of the EEPROM Address – an Acknowledge Bit from the Configurator
• (Next) Byte of the EEPROM Address – an Acknowledge Bit from the Configurator
• LS Byte of EEPROM Address double word aligned – an Acknowledge bit from the Configurator
• a Start Condition
• a Device Address with R/W = 1 – an Acknowledge Bit from the Configurator
• Data Bytes – an Acknowledge bit from the Configurator
• a Data Byte from the Configurator
• a Stop Condition from the programmer. Figure 7-7. Random Read frame START CONDITION DEVICE MS EEPROM (next) EEPROM DATA LAST STOP ADDRESS ADDRESS BYTE ADDRESS BYTE CONDITION ... ACK BIT (from configurator) LS EEPROM ADDRESS BYTE BYTE 1 BYTE START CONDITION DEVICE ADDRESS

7752A–AERO–07/07 AT69170E Figure 7-8. Random Read Summary - TWI Random Read C_ACK? START Send Start Condition Send Device Address R/W=0 Send MSB of EEPROM Address Send 2 nd Byte of Start Condition Send LSB of EEPROM Address Yes C_ACK? C_ACK? C_ACK? Yes Yes No No No No C_ACK? Send Start Condition Send Device Address R/W=1 Data Byte from AT69170E Yes No P_ACK? P_STOP ? No Yes Yes END No C_ACK : Configurator send Acknowledge P_ACK : Programmer send Acknowledge P_STOP : Programmer send STOP condition

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7.3 Special Functions

The special functions available on the AT69170E are

• Data Protection
• RESET/OE Polarity
• Full Chip Erase Access to the special functions is based on use of not aligned addresses (A1 and A0 different from 0) in the command sent by the programmer to the AT69170E.

7.3.1 Exit Special Function

In order to indicate to the memory that the special function is ended, the following sequence shall be performed at the end of each special function.

• write 0xAAAAAAAA at address 0x55555
• write 0x555555555 at address 0x2AAAA
• write 0x00000000 at address 0x55555

7.3.2 Data Protection

The AT69170E has a “Write Protection” feature that disables data write capability to the mem- ory. When the lock is activated, data loaded to the memory is not written in the memory and previous data is preserved. There is no physical write protect pins for AT69170 E. The write protection feature is determined by the state of an embedded fuses. Read and write o f the protection is done through the 2-wire bus (Clock and Data) when the memory is in the programming mode (SER_EN is driven Low).

7.3.2.1 Enabling Write Protection

To enable the write protection, the following sequence shall be applied:

• write 0xAAAAAAAA at address 0x55555
• write 0x555555555 at address 0x2AAAA
• write 0x000000A0 at address 0x55555

7.3.2.2 Disbaling Write Protection

To disable the write protection, the following sequence shall be applied:

• write 0xAAAAAAAA at address 0x55555
• write 0x555555555 at address 0x2AAAA
• write 0x00000080 at address 0x55555
• write 0xAAAAAAAA at address 0x55555
• write 0x555555555 at address 0x2AAAA
• write 0x00000020 at address 0x55555

7.3.2.3 Reading Write Protection Configuration

To read the state of the write protection, the following sequence shall be applied:

• write 0xAAAAAAAA at address 0x55555
• write 0x555555555 at address 0x2AAAA

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• write 0x000000F2 at address 0x55555
• read data from address 0x000000001 – If the most significant byte of the read data is “ 0x00” then memory can be written. – if the most significant byte of the read data is “0xFF” then memory is write pro tected.

7.3.3 RESET/OE Polarity

The AT69170E configurator allows the user to program the reset polarity as either RESET/OE or RESET /OE. This is required to allow the devices to prope rly configure various FPGA families. The default configuration is RESET /OE:

• RESET active Low
• OE active High After the RESET polarity has been modified, the Con figurator must be powered down and back up again before attempting to verify functionality or use the newly programmed RESET function.

7.3.3.1 RESET/

Configuration of the polarity as OE active high and RESET active low (RESET/ OE) is obtained applying the following sequence:

• write 0xAAAAAAAA at address 0x55555
• write 0x555555555 at address 0x2AAAA
• write 0x000000FF at address 0x55555

7.3.3.2 RESET/OE

To set the polarity option active high on RESET and active low on OE (RESET/ OE), the follow- ing sequence shall be applied:

• write 0xAAAAAAAA at address 0x55555
• write 0x555555555 at address 0x2AAAA
• write 0x0000FFFF at address 0x55555 To read the state of the (RESET/ OE) Polarity, the following sequence shall be applied:
• write 0xAAAAAAAA at address 0x55555
• write 0x555555555 at address 0x2AAAA
• write 0x000000F2 at address 0x55555
• read data from address 0x000000001 – If bit 23 of the read data is “0” then the polarit y is RESET/ OE – If bit 23 of the read data is “1” then the polarit y is RESET/OE

7.3.4 Chip Erase

The AT69170E configurator allows to erase the entir e AT69170E memory in one special com- mand. In order to erase the chip, the following sequence shall be applied:

• write 0x555555 at address 0x2AAAA
• write 0xAAAAAA at address 0x55555
• write 0x555555 at address 0x000B0

7752A–AERO–07/07 AT69170E 8. FPGA Configuration mode

8.1 Configuration mode overview

The I/O and logic functions of any SRAM-based FPGA are established by a configuration pro- gram. The program is loaded either automatically up on power-up, or on command, depending on the state of the FPGA mode pins. In Master mode, the FPGA automatically loads the config- uration program from an external memory. The AT6917 0E Serial Configuration EEPROM has been designed for compatibility with the Master Serial mode. The control signals for the AT69170E (CE , RESET/ OE and CLK) interface directly with the FPGA device control signals. All FPGA devices can c ontrol the entire configuration process and retrieve data from the AT69170E without requiring an external intelligent controller. The EEPROM RESET/ OE and CE pins control the tri-state buffer on the DATA outp ut pin and enable the address counter. When RESET/ OE is driven High, the configuration EEPROM resets its address counter and tri-states its DATA pin. Th e CE pin also controls the output of the AT69170 series configurator. If CE is held High after the RESET/ OE reset pulse, the counter is disabled and the DATA output pin is tri-stated. Whe n OE is subsequently driven Low, the counter and the DATA output pin are enabled. When R ESET/ OE is driven High again, the address counter is reset and the DATA output pin is tri-stated, regardless of the state of CE . When the configurator has driven out all of its dat a and CEO is driven Low, the device tri-states the DATA pin to avoid contention with other configu rators. Upon power-up, the AT69170E address counter is automatically reset.

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8.2 FPGA Configuration Operation

Connections between an FPGA device and the AT69170E Serial EEPROM are define as follow.

• SER_EN pin is connected to VDD to allow configuration.
• RESET /OE is connected to the FPGA configuration start indicator. It is used to put the memory in its default state and initiate the configuration.
• CE pins input is connected to the memory chip select of the FPGA.
• The FPGA master clock output drives the CLK input of the AT69170E series configurator.
• The DATA output of the AT69170E series configurator drives the input data port of the FPGA devices.
• The CEO output of the AT69170E drives the CE input of the next configurator in a cascaded chain of EEPROMs.

8.2.1 Typical Configuration with ATF280E FPGA

The ATF280E provides two signals, RESET and INIT, t hat can be used to initiate the configura- tion. One of this pin shall be connected to the AT69170E RESET/ OE pin. The ATF280E CON pin is tied to the Configurator chip enable (CE) to allow selection of the device. The ATF280E FPGA drives the CCLK clock on the AT691 70E so that the memory provides one data bit on D0 per CCLK rising edge. Each CCLK incr ements the AT69170E internal address counter, and serial data is presented to the FPGA. Once the bitstream is complete, CON is released by the FPGA, indicating the device is com- pletely ready for user operation. Figure 8-1. AT280E FPGA configuration mode CLK DATA CE RESET/OE CEO RESET INIT CON D<0> CCLK ATF280E Serial Mode AT69170E RESET INIT

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8.2.2 Cascading Serial EEPROMs

For multiple FPGAs configured as a daisy-chain, or for FPGAs requiring larger configuration memories, it is possible to cascade AT69170E. This provides additional memory to fit FPGA bit- stream size. Once the last bit from the first configurator is re ad, the memory asserts its CEO output Low and disables its DATA line driver. The second configura tor recognizes the Low level on its CE input and enables its DATA output. After configuration is complete, the address counte rs of all cascaded configurators are reset if the RESET /OE on each configurator is driven to its active (Low) level. If the address counters does not requires to be res et upon completion, then the RESET /OE input can be tied to its inactive (High) level. Figure 8-2. AT69170E Cascade CLK DATA CE RESET/OE CEO RESET INIT CON D<0> CCLK ATF280E Serial Mode AT69170E RESET INIT CEO AT69170E CLK DATA CE RESET/OE

7752A–AERO–07/07 AT69170E 9. Electrical Characteristics

9.1 Operating Conditions

9.2 Absolute Maximum Ratings*

9.3 DC Characteristics

Operating Temperature (Case) -55 to +125° C Vcc Power Supply 3V to 3.6V “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sec- tions of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. All Input Voltages (including NC Pins) All Output Voltages DD + 0.5V Symbol Parameter Condition Min. Max Units I IL , IIH Low Level Input Current VIN = 0V to 3.6V Vcc max -2 2 µ A IOZL , IOZH Output Leakage Current VI/O = 0V to 3.6V Vcc max -2 2 µ A ICCSB1 Standby Current CMOS CE >= V DD - 0.3V 1 mA ICCSB Standby Current TTL CE >= VIH 2 mA ICCOPR Read Operating Current f = 15 MHz; I OUT = 0 mA 5 mA ICCOPW Write Operating Current f = 1/Twr 70 mA VIL Input Low Voltage GND - 0.3 0.8 V VIH Input High Voltage 2.0 Vcc+0.3 V VOL Output Low Voltage I OL = 8mA 0.4 V VOH Output High Voltage I OH = -4mA Vcc - 0.4 V

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9.3.1 Input Test Waveforms and Measurement Level

9.3.2 Output Test Load

9.3.3 Pin Capacitance (f=1MHz, 25° C)

Note: 1. This parameter is guaranteed but not tested. VCC Symbol Typ Max Units Conditions C IN 7 10 pF V IN = 0V COUT 7 10 pF V OUT = 0V

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9.4 AC Characteristics & Waveforms

9.4.1 TWI characteristics & waveform

Figure 9-1. AT69170E serial data transfer - TWI Table 9-1. AT69170E serial data transfer timings - TWI Symbol Description AT69170E Units Min Max Fclock Clock Frequency - CLOCK 400 KHz Tclk Clock Period 2.5 µs Tlow Clock Low Pulse Width 1.2 µs Thigh Clock High Pulse Width 1.2 µs Taa Clock Low to Data Out Valid 0.9 µs Tbuf Time the bus must be free before a new transmis sion can start 1.2 µs Thd-sta Start Hold Time from CLOCK 0.6 µs Tsu-sta Start Setup Time from CLOCK 0.6 µs Thd-dat Data In Hold Time 0.1 µs Tsu-dat Data In Setup Time 0.1 µs Tr Inputs Rise Time 0.3 µs Tf Inputs Fall Time 0.3 µs Tsu-sto Stop Setup Time 0.6 µs Tdh Data Out Hold Time 0 µs Twr Write Cycle Time 8000 Tlck

7752A–AERO–07/07 AT69170E

9.4.2 FPGA Configuration characteristics & waveform - Memory Dump

Figure 9-2. FPGA Configuration with AT69170E - Memory Dump Figure 9-3. FPGA Configuration - AT69170E cascade mode Table 9-2. FPGA Configuration timings CE RESET/OE CLK DATA TSCE TLC THC TCACTOE TCE TOH THOE TSCE THCE TDF TOH CE RESET/OE CLK DATA CEO TCDF TOCK TOCE TOCE TOOE LAST BIT FIRST BIT Symbol Description AT69170E Units Min Max TOE Data Output Delay from OE 35 ns TCE Data Output Delay from CE 40 ns TCAC Data Output Delay from CLK 40 ns TOH Data Hold from CE , OE, or CLK 0 ns TDF Data Float Output Delay from CE or OE 30 ns Tcdf Data Float Output Delay from CLK 30 ns

7752A–AERO–07/07 AT69170E Tock CEO Output Delay from CLK 35 ns Toce CEO Output Delay from CE 25 ns Tooe CEO Output Delay from RESET /OE 25 ns TLC CLK Low Time 20 ns THC CLK High Time 20 ns TSCE CE Setup Time to CLK (to guarantee proper counting) 20 ns THCE CE Hold Time from CLK (to guarantee proper counting) 0 ns THOE RESET pulse width that guarantees the counter is re set 60 ns FMAX Maximum Clock Frequency 15 MHz Symbol Description AT69170E Units Min Max

7752A–AERO–07/07 AT69170E 10. Packaging Information Advanced Package Drawing

7752A–AERO–07/07 AT69170E 11. Ordering Information Note: 1. Contact factory for availability Ordering Code Package Flow AT69170E-Dx-E FP18 (Dx) Engineering Samples AT69170E-Dx-MQ QMLQ AT69170E-Dx-SV QMLV AT69170E-Dx-ESCC ESCC

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