AT68166HT ATMEL | Alldatasheet
Document overview
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Technical content
Features
- 16 Mbit SRAM Multi Chip Module
- Allows 32-, 16- or 8-bit access configuration
- Operating Voltage: 3.3V + 0.3V, 5V Tolerant
- Access Time: – 25 ns – 20 ns – 18 ns (preliminary information)
- Very Low Power Consumption – Active: 595 mW per byte (Max) @ 20 ns(1), 415mW per byte (Max) @ 50ns(2) – Standby: 15 mW (Typ)
- Military Temperature Range: -55 to +125°C
- TTL-Compatible Inputs and Outputs
- Asynchronous
- Die manufactured on Atmel 0.25 µm Radiation Hardened Process
- No Single Event Latch Up below LET Threshold of 80 MeV/mg/cm2@125°C
- Tested up to a Total Dose of 300 krads (Si) according to MIL-STD-883 Method 1019
- ESD better than 2000V
- Quality Grades: – QML-Q or V –E S C C
- 950 Mils Wide MQFPT68 Package
- Mass : 8.5 grams Notes: 1. For AT68166HT-20 only. 540mW for AT68166HT-25. 2. For AT68166HT-20 only. 450mW for AT68166HT-25.
Description
The AT68166HT is a 16Mbit SRAM packaged in a hermetic Multi Chip Module (MCM) for space applications. The AT68166HT MCM incorporates four 4Mbit AT60142HT SRAM dice. It can be organized as either one bank of 512Kx8, two banks of 512Kx16 or four banks of 512Kx8. It combines rad-hard capabilities, a latch-up threshold of 80MeV.cm²/mg, a Multiple Bit Upset immunity and a total dose tolerance of 300Krads, with a fast access time. The MCM packaging technology allows a reduction of the PCB area by 50% with a weight savings of 75% compared to four 4Mbit packages. Thanks to the small size of the 4Mbit SRAM die, Atmel has been able to accommo- date the assembly of the four dice on one side of the package which facilitates the power dissipation. The compatibility with other products allows designers to easily migrate to the Atmel AT68166HT memory. The AT68166HT is powered at 3.3V and is 5V tolerant. The AT68166HT is processed according to t he test methods of the latest revision of the MIL-PRF-38535 or the ESCC 9000. 7843A–AERO–10/09 Rad Hard 16 MegaBit 3.3V 5V Tolerant SRAM Multi- Chip Module AT68166HT
7843A–AERO–10/09 AT68166HT Block Diagram AT68166HT Block Diagram 512K x 8 Banks Block Diagram (AT60142HT) A[18:0] OE CS1 WE1 I/O[15:8] BANK1 512k x 8 CS2 WE2 I/O[23:16] BANK2 512k x 8 CS3 WE3 I/O[31:24] BANK3 512k x 8 CS0 WE0 I/O[7:0] BANK0 512k x 8 or I/O2[31:16] or I/O2[15:0] or I/O1[31:16] or I/O1[15:0] or I/O3[7:0] or I/O2[7:0] or I/O1[7:0] or I/O[7:0] I/Ox0 I/Ox7 CSx OE WEx
AT68166HT is packaged in a MQFPT68. The pin assignment depends on the access time. Table 1. Pin assignment for YS & YM versions
1 I/O0[0] 18 VCC 35 I/O3[7] 52 VCC
2 I/O0[1] 19 A11 36 I/O3[6] 53 A10
3 I/O0[2] 20 A12 37 I/O3[5] 54 A9
4 I/O0[3] 21 A13 38 I/O3[4] 55 A8
5 I/O0[4] 22 A14 39 I/O3[3] 56 A7
6 I/O0[5] 23 A15 40 I/O3[2] 57 A6
7 I/O0[6] 24 A16 41 I/O3[1] 58 WE0
8 I/O0[7] 25 CS0 42 I/O3[0] 59 CS3
10 I/O1[0] 27 CS1 44 I/O2[7] 61 CS2
11 I/O1[1] 28 A17 45 I/O2[6] 62 A5
12 I/O1[2] 29 WE1 46 I/O2[5] 63 A4
13 I/O1[3] 30 WE2 47 I/O2[4] 64 A3
14 I/O1[4] 31 WE3 48 I/O2[3] 65 A2
15 I/O1[5] 32 A18 49 I/O2[2] 66 A1
16 I/O1[6] 33
50 I/O2[1] 67 A0
17 I/O1[7] 34
51 I/O2[0] 68
Table 2. Pin Names Table 3. Truth Table(1) Note: 1. L=low, H=high, X= H or L, Z=high impedance.
7843A–AERO–10/09 AT68166HT
Electrical Characteristics
Absolute Maximum Ratings* Military Operating Range Recommended DC Operating Conditions Note: 1. 5.8V in transient conditions. Capacitance Note: 1. Guaranteed but not tested. (MIL STD 883D Method 3015) *NOTE: Stresses beyond those listed under "Abso- lute Maximum Ratings” may cause perma- nent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure between recommended DC operating and absolute maximum rating conditions for extended periods may affect device reliability. Operating Voltage Operating Temperature 3.3 + 0.3V -55 ⋅C to + 125⋅C Parameter Descripti on Min Typ Max Unit Vcc Supply voltage 3.0 3.3 3.6 V GND Ground 0.0 0.0 0.0 V VIL Input low voltage GND - 0.3 0.0 0.8 V VIH Input high voltage 2.2 – 5.5V (1) V Parameter Description Min Typ Max Unit Cin (1) (OE and Ax) Input capacitance – – 48 pF Cin (1) (CSx and WEx) Input capacitance – – 12 pF Cio (1) I/O capacitance – – 12 pF
7843A–AERO–10/09 AT68166HT DC Parameters DC Test Conditions TA = -55 °C to + 125°C; Vss = 0V; VCC = 3.0V to 3.6V Notes: 1. GND < V IN < VCC, GND < VOUT < VCC Output Disabled. 2. V IN = 5.5V, VOUT = 5.5V, Output Disabled. 3. V CC min, - IOL = 6 mA 4. V CC min, IOH = -4 mA Consumption Notes: 1. All CSx >VIH 2. All CSx > VCC - 0.3V 3. F = 1/ TAVAV, Iout = 0 mA, WEx = OE = VIH, VIN = GND/VCC, VCC max. 4. F = 1/ TAVAW, Iout = 0 mA, WEx = VIL, OE = VIH , VIN = GND/VCC, VCC max. Parameter Description Minimum Typical Maximum Unit AT68166HT-25 AT68166HT-20 AT68166HT-18 IIX(1) Input leakage current -1 – 1 1 1 μA IOZ(1) Output leakage current -1 – 1 1 1 μA IIH(2) at 5.5V Input Leakage Current (OE & Axx) – – 10 6 6 μA Input Leakage Current (WE & CS) – – 522 µ A IOZH(2) at 5.5V Output Leakage Current – – 5 1.5 1.5 μA VOL(3) Output low voltage – – 0.4 0.4 0.4 V VOH(4) Output high voltage 2.4 – – – – V Symbol Description TAVAV/TAVAW Test Condition AT68166HT-25 AT68166HT-20 AT68166HT-18 (preliminary) Unit Value ICCSB (1) Standby Supply Current – 10 7 7.5 mA max ICCSB1 (2) Standby Supply Current – 8 6 7 mA max ICCOP (3) Read per byte Dynamic Operating Current 18 ns 20 ns 25 ns 50 ns 1 µs 150 165 145 170 165 145 mA max I CCOP (4) Write per byte Dynamic Operating Current 18 ns 20 ns 25 ns 50 ns 1 µs 150 125 110 140 135 115 105 145 140 135 115 105 mA max
- During data retention chip select CSx must be held high within VCC to VCC -0.2V.
- Output Enable (OE ) should be held high to keep the RAM outputs high impedance, mini-
- During power-up and power-down transitions CSx and OE must be kept between VCC +
- The RAM can begin operation > t R ns after VCC reaches the minimum operation voltages
Figure 3. Data Retention Timing
- T AVAV = Read cycle time.
- All CSx = VCC, VIN = GND/VCC.
Figure 4. AC Test Loads Waveforms Table 4. Write cycle timings(1) Notes: 1. Timings figures applicable for 8-bit, 16-bit and 32-bit mode.
- Parameters guaranteed, not tested, with output loading 5 pF . (See “AC Test Loads Wave-
7843A–AERO–10/09 AT68166HT Write Cycle 1. W E Controlled, OE High During Write Write Cycle 2. W E Controlled, OE Low Write Cycle 3. CS Controlled The internal write time of the memory is defined by the overlap of CS Low and WE LOW. Both signals must be activated to initiate a write and either signal can terminate a write by going in active mode. The data input setup and hold timing should be referenced to the active edge of the signal that terminates the write. Data out is high impedance if OE= VIH. EE ADDRESS CSx WEx I/Os OE E E ADDRESS CSx WEx I/Os E ADDRESS CSx WEx I/Os
Table 5. Read cycle timings(1) Notes: 1. Timings figures applicable for 8-bit, 16-bit and 32-bit mode.
- Parameters guaranteed, not tested, with output loading 5 pF . (See “AC Test Loads Wave-
7843A–AERO–10/09 AT68166HT
Ordering Information
Note: 1. Please contact your local sales office. 2. Will be replaced by SMD part number when available. 3. Will be replaced by ESCC part number when available. Part Number Temperature Range Speed Package Flow AT68166HT-YM25-E 25 ⋅C 25 ns MQFPT68 Engineering Samples AT68166HT-YM25MQ(2) -55⋅ to +125⋅C 25 ns MQFPT68 Mil Level B AT68166HT-YM25SV(2) -55⋅ to +125⋅C 25 ns MQFPT68 Space Level B AT68166HT-YM25SR(2) -55⋅ to +125⋅C 25 ns MQFPT68 Space Level B RHA AT68166HT-YM25-SCC(3) -55⋅ to +125⋅C 25 ns MQFPT68 ESCC AT68166HT-YS20-E 25 °C 20 ns MQFPT68 Engineering Samples AT68166HT-YS20MQ(2) -55° to +125°C 20 ns MQFPT68 Mil Level B AT68166HT-YS20SV(2) -55° to +125°C 20 ns MQFPT68 Space Level B AT68166HT-YS20SR(2) -55° to +125°C 20 ns MQFPT68 Space Level B RHA AT68166HT-YS20-SCC(3) -55° to +125°C 20 ns MQFPT68 ESCC AT68166HT-YS18-E(1) 25°C 18 ns MQFPT68 Engineering Samples AT68166HT-YS18-MQ(1)(2) -55° to +125°C 18 ns MQFPT68 Mil Level B AT68166HT-YS18-SV(1)(2) -55° to +125°C 18 ns MQFPT68 Space Level B AT68166HT-YS18-SR(1)(2) -55° to +125°C 18 ns MQFPT68 Space Level B RHA AT68166HT-YS18-SCC(1)(3) -55° to +125°C 18 ns MQFPT68 ESCC
7843A–AERO–10/09 AT68166HT Package Drawing 68-lead Quad Flat Pack (950 Mils) with non conductive tie bar Note: 1. Lid is connected to Ground. 2. YM and YS package drawings are identical. Document Revision History Creation from AT66168FT without any change.
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