AT68166FT_09 ATMEL | Alldatasheet

Document overview

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Technical content

Features

  • 16 Mbit SRAM Multi Chip Module
  • Allows 32-, 16- or 8-bit access configuration
  • Operating Voltage: 3.3V + 0.3V, 5V Tolerant
  • Access Time: – 25 ns, 20 ns – 18 ns (preliminary information)
  • Very Low Power Consumption – Active: 595 mW per byte (Max) @ 20 ns(1), 415mW per byte (Max) @ 50ns(2) – Standby: 15 mW (Typ)
  • Military Temperature Range: -55 to +125°C
  • TTL-Compatible Inputs and Outputs
  • Asynchronous
  • Die manufactured on Atmel 0.25 µm Radiation Hardened Process
  • No Single Event Latch Up below LET Threshold of 80 MeV/mg/cm2
  • Tested up to a Total Dose of 300 krads (Si) according to MIL-STD-883 Method 1019
  • ESD Better than 2000V
  • Quality Grades: – QML-Q or V with SMD 5962-06229 –E S C C
  • 950 Mils Wide MQFP 68 Package
  • Mass : 8.5 grams Notes: 1. For AT68166FT-20 only. 540mW for AT68166FT-25. 2. For AT68166FT-20 only. 450mW for AT68166FT-25.

Description

The AT68166FT is a 16Mbit SRAM packaged in a hermetic Multi Chip Module (MCM) for space applications. The AT68166FT MCM incorporates four 4Mbit AT60142FT SRAM dice. It can be orga- nized as either one bank of 512Kx8, two banks of 512Kx16 or four banks of 512Kx8. It combines rad-hard capabilities, a latch-up threshold of 80MeV.cm²/mg, a Multiple Bit Upset immunity and a total dose tolerance of 300Krads, with a fast access time. The MCM packaging technology allows a reduction of the PCB area by 50% with a weight savings of 75% compared to four 4Mbit packages. Thanks to the small size of the 4Mbit SRAM die, Atmel has been able to accommo- date the assembly of the four dice on one side of the package which facilitates the power dissipation. The compatibility with other products allows designers to easily migrate to the Atmel AT68166FT memory. The AT68166FT is powered at 3.3V and is 5V tolerant. The AT68166FT is processed according to the test methods of the latest revision of the MIL-PRF-38535 or the ESCC 9000. 7531H–AERO–04/09 Rad Hard 16 MegaBit 3.3V 5V Tolerant SRAM Multi- Chip Module AT68166FT

Figure 2. 512K x 8 Banks Block Diagram (AT60142FT) – YM package where 3 pins are not connected.

7531H–AERO–04/09 AT68166FT Pin Configuration Table 1. AT68166FT pin assignment in YS package Note: In YM package leads 33, 34 and 68 are not connected. Lead Signal Lead Signal Lead Signal Lead Signal

1 I/O0[0] 18 VCC 35 I/O3[7] 52 VCC

2 I/O0[1] 19 A11 36 I/O3[6] 53 A10

3 I/O0[2] 20 A12 37 I/O3[5] 54 A9

4 I/O0[3] 21 A13 38 I/O3[4] 55 A8

5 I/O0[4] 22 A14 39 I/O3[3] 56 A7

6 I/O0[5] 23 A15 40 I/O3[2] 57 A6

7 I/O0[6] 24 A16 41 I/O3[1] 58 WE0

8 I/O0[7] 25 CS0 42 I/O3[0] 59 CS3

9G N D 2 6O E 43 GND 60 GND

10 I/O1[0] 27 CS1 44 I/O2[7] 61 CS2

11 I/O1[1] 28 A17 45 I/O2[6] 62 A5

12 I/O1[2] 29 WE1 46 I/O2[5] 63 A4

13 I/O1[3] 30 WE2 47 I/O2[4] 64 A3

14 I/O1[4] 31 WE3 48 I/O2[3] 65 A2

15 I/O1[5] 32 A18 49 I/O2[2] 66 A1

16 I/O1[6] 33 GND 50 I/O2[1] 67 A0

17 I/O1[7] 34 VCC 51 I/O2[0] 68 VCC

Table 2. Pin Names Table 3. Truth Table(1) Note: 1. L=low, H=high, X= H or L, Z=high impedance.

7531H–AERO–04/09 AT68166FT

Electrical Characteristics

Absolute Maximum Ratings* Military Operating Range Recommended DC Operating Conditions Note: 1. 5.8V in transient conditions. Capacitance Note: 1. Guaranteed but not tested. (MIL STD 883D Method 3015.3) *NOTE: Stresses beyond those listed under "Abso- lute Maximum Ratings” may cause perma- nent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure between recommended DC operating and absolute maximum rating conditions for extended periods may affect device reliability. Operating Voltage Operating Temperature 3.3 + 0.3V -55 °C to + 125°C Parameter Description Min Typ Max Unit Vcc Supply voltage 3 3.3 3.6 V GND Ground 0.0 0.0 0.0 V VIL Input low voltage GND - 0.3 0.0 0.8 V VIH Input high voltage 2.2 – 5.5V (1) V Parameter Description Min Typ Max Unit Cin (1) (OE and Ax) Input capacitance – – 48 pF Cin (1) (CSx and WEx) Input capacitance – – 12 pF Cio (1) I/O capacitance – – 12 pF

7531H–AERO–04/09 AT68166FT DC Parameters Notes: 1. GND < V IN < VCC, GND < VOUT < VCC Output Disabled. 2. V IN = 5.5V, VOUT = 5.5V, Output Disabled. 3. V CC min. - IOL = 6 mA 4. V CC min. IOH = -4 mA Parameter Description Minimum Typical Maximum UnitAT68166FT-25 AT68166FT-20 AT68166FT-18 IIX(1) Input leakage current - 1 – 111 μA IOZ(1) Output leakage current - 1 – 111 μA IIH(2) at 5.5V Input Leakage Current (OE & Axx) –– 1 0 6 6 μA Input Leakage Current (WE & CS) – – 522µ A IOZH(2) at 5.5V Output Leakage Current –– 5 1 . 5 1 . 5 μA VOL(3) Output low voltage – – 0.4 0.4 0.4 V VOH(4) Output high voltage 2 . 4 – ––– V

  1. F = 1/ TAVAV, Iout = 0 mA, WEx = OE = VIH, VIN = GND/VCC, VCC max.
  2. F = 1/ TAVAW, Iout = 0 mA, WEx = VIL, OE = VIH , VIN = GND/VCC, VCC max.
  3. During data retention chip select CSx must be held high within VCC to VCC -0.2V.
  4. Output Enable (OE ) should be held high to keep the RAM outputs high impedance, mini-
  5. During power-up and power-down transitions CSx and OE must be kept between VCC +
  6. The RAM can begin operation > t R ns after VCC reaches the minimum operation voltages

Figure 5. Data Retention Timing

7531H–AERO–04/09 AT68166FT Data Retention Characteristics Parameter Description Min Typ T A = 25°CM a x U n i t VCCDR VCC for data retention 2.0 – – V tCDR Chip deselect to data retention time 0.0 – – ns tR Operation recovery time tAVAV (1) 1. T AVAV = Read cycle time. –– n s ICCDR (2) 2. All CSx = VCC, VIN = GND/VCC. Data retention current – 3 6 (AT68166FT-25) mA4.5 (AT68166FT-20) 5 (AT68166FT-18)

Figure 6. AC Test Loads Waveforms Table 4. Write cycle timings(1) Notes: 1. Timings figures applicable for 8-bit, 16-bit and 32-bit mode.

  1. Parameters guaranteed, not tested, with output loading 5 pF. (See “AC Test Loads Waveforms” on page 10.)

Table 5. Read cycle timings(1) Notes: 1. Timings figures applicable for 8-bit, 16-bit and 32-bit mode.

  1. Parameters guaranteed, not tested, with output loading 5 pF. (See “AC Test Loads Waveforms” on page 10.)

Figure 14. 8-bit typical application (two SRAM banks)

7531H–AERO–04/09 AT68166FT

Ordering Information

Note: 1. Please contact your local sales office. 2. Will be replaced by SMD part number when available. Part Number Temperature Range Speed Package Flow AT68166FT AT68166FT-YM25-E 25 °C 25 ns MQFPT68 Engineering Samples 5962-0622901QXC -55 ° to +125°C 25 ns MQFPT68 QML Q 5962-0622901VXC -55 ° to +125°C 25 ns MQFPT68 QML V 5962R0622901VXC -55 ° to +125°C 25 ns MQFPT68 QML V RHA AT68166FT-YM25-SCC -55 ° to +125°C 25 ns MQFPT68 ESCC AT68166FT-YS20-E 25 °C 20 ns MQFPT68 Engineering Samples 5962-0622903QYC -55 ° to +125°C 20 ns MQFPT68 QML Q 5962-0622903VYC -55 ° to +125°C 20 ns MQFPT68 QML V 5962R0622903VYC -55 ° to +125°C 20 ns MQFPT68 QML V RHA AT68166FT-YS20-SCC(2) -55° to +125°C 20 ns MQFPT68 ESCC AT68166FT-YS18-E(1) 25°C 18 ns MQFPT68 Engineering Samples AT68166FT-YS18-MQ(1)(2) -55° to +125°C 18 ns MQFPT68 QML Q AT68166FT-YS18-SV(1)(2) -55° to +125°C 18 ns MQFPT68 QML V AT68166FT-YS18-SR(1)(2) -55° to +125°C 18 ns MQFPT68 QML V RHA AT68166FT-YS18-SCC(1)(2) -55° to +125°C 18 ns MQFPT68 ESCC

7531H–AERO–04/09 AT68166FT Package Drawings 68-lead Quad Flat Pack (950 Mils) with non conductive tie bar Note: Lid is connected to Ground. Note: YM and YS package drawings are identical.

7531H–AERO–04/09 AT68166FT Document Revision History Changes from Rev. C to Rev. D 1. Update of access time parameters. Changes from Rev. D to Rev. E 1. Added YS package. Changes from Rev. E to Rev. F 1. Updated ordering information. Changes from Rev. F to Rev. G 1. Split datasheet into two seperate documents: removed AT68166F from this document. Please refer to document 7747 on the Atmel web site. Changes from Rev. G to Rev. H 1. Update of Absolute Maximum Ratings section

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