AT5FC001 ATMEL | Alldatasheet
Document overview
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Technical content
Features
- Single Power Supply Read and Write Voltage, 5 V ± 5%
- High Performance 200 ns Maximum Access Time 6 ms Typical Sector Write
- CMOS Low Power Consumption 20 mA Typical Active Current (Byte Mode) 400 µA Typical Standby Current
- Fully MS-DOS Compatible Flash Driver and Formatter Virtual-Disk Flash Driver with 256 Bytes/Sector Random Read/Write to any Sector No Erase Operation Required Prior to any Write
- Zero Data Retention Power Batteries not Required for Data Storage
- PCMCIA/JEIDA 68-Pin Standard Selectable Byte- or Word-Wide Configuration
- High Re-programmable Endurance Built-in Redundancy for Sector Replacement Minimum 100,000 Write Cycles
- Five Levels of Write Protection Prevent Accidental Data Loss Block Diagram
Description
Atmel’s Flash Memory Card provides the highest system level performance for data and file storage solutions to the portable PC market segment. Data files and applications programs can be stored on the AT5FC001. This allows OEM manufacturers of portable system to eliminate the weight, power consumption and reliability issues associated with electro-mechanical disk-based systems. The AT5FC001 requires a single voltage power supply for total system operation. No batteries are needed for data re- tention due to its Flash-based technology. Since no high voltage (12-volt) is required to perform any write operation, the AT5FC001 is suitable for the emerging "mobile" personal sys- tems. The AT5FC001 is compatible with the 68-pin PCMCIA/JEIDA international standard. Atmel’s Flash Memory Cards can be read in either a byte-wide or word-wide mode which allows for flexible integration into various system platforms. It can be read like any typical PCMCIA SRAM or ROM card. The Card Information Structure (CIS) can be written by the OEM or by Atmel at the attribute memory address space using a format utility. The CIS appears at the beginning of the card’s attribute memory space and defines the low-level organization of data on the PC card. The AT5FC001 contains a separate
2 Kbyte EEPROM memory for the card’s attribute memory
space. The third party software solutions such as AWARD Software’s CardWare system and the SCM’s Flash File System (FFS), enables Atmel’s Flash Memory Card to emulate the function of essentially all the major brand personal computers that are DOS/Windows compatible. For some unique portable computers, such as the HP200/100/95LX series, the software Driver and Formatter are also available. The Atmel Driver and Formatter utilizes a self- contained spare sector replacement algorithm, enabled by At- mel’s small 256-byte sectors, to achieve long term card reliability and endurance. Block Diagram
2 AT5FC001
*NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the card. This is a stress rating only and functional operation of the card at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended pe- riods may affect device reliability. Notes: 1. Minimum DC voltage on input or I/O pins is -0.5 V. During volt- age transients, inputs may overshoot V SS to -2.0 V for periods of up to 20 ns. Maximum DC voltage on output and I/O pins is V CC +0.5 V. During voltage transitions, outputs may overshoot to V CC +2.0 V for periods up to 20 ns. 2. No more than one output shorted at a time. Duration of the short cir- cuit should not be greater than one second. Conditions equal V OUT = 0.5 V or 5.0 V, VCC = Max. Absolute Maximum Ratings* Pin Capacitance (f = 1 MHz, T = 25°C) (1) Symbol Parameter Conditions Typ Max Units C IN1 Address Capacitance V IN = 0 V 20 pF C OUT Output Capacitance V OUT = 0 V 20 pF C IN2 Control Capacitance V IN = 0 (CE) 45 pF C I/O I/O Capacitance V I/O = 0 V 20 pF Note: 1. This parameter is characterized and is not 100% tested. D.C. and A.C. Operating Range AT5FC001-20 Operating Temperature (Case) Com. 0 oC - 70oC VCC Power Supply 5 V ± 5% AT5FC001
I = Input, O = Output, I/O = Bi-directional, NC = No Connect Pin Signal I/O Function
1 GND Ground
2 D3 I/O Data Bit 3
3 D4 I/O Data Bit 4
4 D5 I/O Data Bit 5
5 D6 I/O Data Bit 6
6 D7 I/O Data Bit 7
CE 1 I Card Enable 1 (1)
8 A10 I Address Bit 10
10 A11 I Address Bit 11
11 A9 I Address Bit 9
12 A8 I Address Bit 8
13 A13 I Address Bit 13
14 A14 I Address Bit 14
16 NC No Connect
18 NC No Connect
19 A16 I Address Bit 16
20 A15 I Address Bit 15
21 A12 I Address Bit 12
22 A7 I Address Bit 7
23 A6 I Address Bit 6
24 A5 I Address Bit 5
25 A4 I Address Bit 4
26 A3 I Address Bit 3
27 A2 I Address Bit 2
28 A1 I Address Bit 1
29 A0 I Address Bit 0
30 D0 I/O Data Bit 0
31 D1 I/O Data Bit 1
32 D2 I/O Data Bit 2
33 WP O Write Protect
(1)
34 GND Ground
35 GND Ground
CD 1 O Card Detect 1 (1)
37 D11 I/O Data Bit 11
38 D12 I/O Data Bit 12
39 D13 I/O Data Bit 13
40 D14 I/O Data Bit 14
41 D15 I/O Data Bit 15
CE 2 I Card Enable 2 (1)
43 NC No Connect
44 RFU Reserved
45 RFU Reserved
46 A17 I Address Bit 17
47 A18 I Address Bit 18
48 A19 I Address Bit 19
49 NC No Connect
50 NC No Connect
52 NC No Connect
53 NC No Connect
54 NC No Connect
55 NC No Connect
56 NC No Connect
57 NC No Connect
58 NC No Connect
59 NC No Connect
60 NC No Connect
62 BVD 2 O Battery Voltage Detect 2 (2)
63 BVD 1 O Battery Voltage Detect 1 (2)
64 D8 I/O Data Bit 8
65 D9 I/O Data Bit 9
66 D10 I/O Data Bit 10
CD 2 O Card Detect 2 (1)
68 GND Ground
Notes: 1. Signal must not be connected between cards. 2. BVD = Internally pulled up.
4 AT5FC001
A0-A19 Address Inputs Input Address Inputs are internally latched during write cycles. D0-D15 Data Input/Output Input/Output Data Input/Outputs are internally latched on write cycles. Data outputs are latched during read cycles. Data pins are active high. When the memory card is de-selected or the outputs are disabled the outputs float to tri-state. CE 1, CE 2 Card Enable Input Card Enable is active low. The memory card is de-selected and power consumption is reduced to standby levels when CE is high. CE activates the internal memory card circuitry that controls the high and low byte control logic of the card, input buffers, segment decoders, and associated memory devices. OE Output Enable Input Output Enable is active low and enables the data buffers through the card outputs during read cycles. WE Write Enable Input Write Enable is active low and controls the write function to the memory array. The target address is latched on the falling edge of the WE pulse and the appropriate data is latched on the rising edge of the pulse. VCC PC Card Power Supply PC Card Power Supply for device operation (5.0 V ± 5%) GND Ground Ground CD 1, CD 2 Card Detect Output When Card Detect 1 and 2 = Ground the system detects the card. WP Write Protect Output Write Protect is active high and indicates that all card write operations are disabled by the write protect switch. NC No Connect Corresponding pin is not connected internally. BVD 1, BVD 2 Battery Voltage Detect Output Internally pulled up. (There is no battery in the card.) REG Register Select Input Provide access to Card Information Structure in the Attribute Memory Device AT5FC001
The AT5FC001 Flash Memory Card is organized as an array of eight individual AT29C010A devices. They are logically de- fined as contiguous sectors of 256 bytes. Each sector can be read and written randomly as designated by the host. There is NO need to erase any sector prior to any write operation. Also, there is NO high voltage (12 V) required to perform any write opera- tions. The common memory space data contents are altered in a simi- lar manner as writing to individual Flash memory devices. On- card address and data buffers activate the appropriate Flash de- vice in the memory array. Each device internally latches address and data during write cycles. Refer to the Memory Operations Table. Byte-Wide Operations The AT5FC001 provides the flexibility to operate on data in byte-wide or word-wide operations. Byte-wide data is available on D0-D7 for read and write operations ( CE 1 = low, CE 2 = high). Even and odd bytes are stored in a pair of memory chip segments (i.e., S0 and S1) and are accessed when A0 is low and high respectively. Word-Wide Operations The 16-bit words are accessed when both CE 1 and CE 2 are forced low, A0 = don’t care. D0-D15 are used for word-wide operations Read Enable/Output Disable Data outputs from the card are disabled when OE is at a logic- high level. Under this condition, outputs are in the high-imped- ance state. The A18 and A19 select the paired memory chip seg- ments, while A0 decides the upper or lower bank. The CE 1/CE 2 pins determine either byte or word mode operation. The Output Enable (OE) is forced low to activate all outputs of the memory chip segments. The on-card I/O transceiver is set in the output mode. The AT5FC001 sends data to the host. Refer to A.C. Read Waveforms drawing. Standby Operations When both CE 1 and CE 2 are at logic-high level, the AT5FC001 is in Standby mode; i.e., all memory chip segments as well as the decoder/transceiver are completely de-selected at minimum power consumption. Even in the byte-mode read operation, only one memory chip segment (even or odd) is active at any time. The other seven memory chip segments remain in standby. In the word-mode there are two memory chip segments in active and six in standby. Write Operations The AT5FC010 is written on a sector basis. Each sector of 256 bytes can be selected randomly and written independently with- out any prior erase cycle. A8 to A17 specify the sector address, while A18 and A19 specify the Flash chip segment pair. Within each sector, the individual byte address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Each byte pair to be pro- grammed must have its high-to-low transition on WE (or CE) within 150 µs of the low-to- high transition of WE (or CE) of the preceding byte pair. If a high-to-low transition is not detected within 150 µs of the last low-to-high transition, the data load period will end and the internal programming period will start. All the bytes of a sector are simultaneously programmed during the internal programming period. A maximum write time of 10 ms per sector is self-controlled by the Flash devices. Refer to A.C. Write Waveforms drawings. Write Protection The AT5FC001 has five types of write protection. The PCMCIA/JEIDA socket itself provides the first type of write protection. Power supply and control pins have specific pin lengths in order to protect the card with proper power supply sequencing in the case of hot insertion and removal. A mechanical write protection switch provides a second type of write protection. When this switch is activated, WE is internally forced high. The Flash memory arrays are therefore write-dis- abled. The third type of write protection is achieved with the built-in low VCC sensing circuit within each Flash device. If the exter- nal VCC is below 3.8 V (typical), the write function is inhibited. The fourth type of write protection is a noise filter circuit within each Flash device. Any pulse of less than 15 ns (typical) on the WE, CE 1 or CE 2 inputs will not initiate a program cycle. The last type of write protection is based on the Software Data Protection (SDP) scheme of the AT29C010A devices. Each of the eight devices needs to enable and disable the SDP individu- ally. Refer to the SDP Algorithm Table for descriptions of en- able and disable SDP operations. Card Detection Each CD (output) pin should be read by the host system to de- termine if the memory card is properly seated in the socket. CD 1 and CD 2 are internally tied to the ground. If both bits are not detected, the system should indicate that the card must be re-inserted. CIS Data The Card Information Structure (CIS) describes the capabilities and specifications of a card. The CIS of the AT5FC001 can be written either by the OEM or by Atmel at the attribute memory space beginning at address 00000H by using a format utility. The AT5FC001 contains a separate 2 Kbyte EEPROM memory for the card’s attribute memory space. The attribute is active when the REG pin is driven low. D0-D7 are active during at- tribute memory access. D8-D15 should be ignored. Odd order bytes present invalid data. Refer to the Attribute Memory Operations table.
6 AT5FC001
X = Don’t Care, where Don’t Care is either VIL or VIH levels. Pins REG CE 2 CE 1 OE WE A0 D8-D15 D0-D7 Read-Only Read (x8) (1) VIH VIH VIL VIL VIH VIL High Z Data Out-Even Read (x8) (2) VIH VIH VIL VIL VIH VIH High Z Data Out-Odd Read (x8) (3) VIH VIL VIH VIL VIH X Data Out-Odd High Z Read (x16) (4) VIH VIL VIL VIL VIH X Data Out-Odd Data Out-Even Output Disable V IH XX V IH VIH X High Z High Z Standby X V IH VIH X X X High Z High Z Write-Only Write (x8) (1) VIH VIH VIL VIH VIL VIL High Z Data In-Even Write (x8) (2) VIH VIH VIL VIH VIL VIH High Z Data In-Odd Write (x8) (3) VIH VIL VIH VIH VIL X Data In-Odd High Z Write (x16) (4) VIH VIL VIL VIH VIL X Data In-Odd Data In-Even Output Disable V IH XX V IH VIL X High Z High Z Notes: 1. Byte access - Even. In this x8 mode, D0-D7 contain the "even" byte (low byte) of the x16 word. D8-D15 are inactive. 2. Byte access - Odd. In this x8 mode, D0-D7 contain the "odd" byte (high byte) of the x16 word. This is accomplished internal to the card by transposing D8-D15 to D0-D7. D8-D15 are inactive. 3. Odd byte only access. In this x8 mode, D8-D15 contain the "odd" byte (high byte) of the x16 word. D0-D7 are inactive. A1 = X. 4. Word access. In this mode D0-D7 contain the "even" byte while D8-D15 contain the "odd" byte. A0 = X BEGIN INTERLEAVING LOW
128 BYTES AND
Memory Card Program Routine Byte Mode BEGIN LOW AND HIGH BYTES SIMULTANEOUSLY SELECT SECTOR WAIT FOR A MAXIMUM OF 10 ms LOAD ADDRESS/DATA OF 128 WORDS SECTOR PROGRAM COMPLETE Memory Card Program Routine Word Mode AT5FC001
Attribute Memory Operations X = Don’t Care, where Don’t Care is either VIL or VIH levels. Pins REG CE 2 CE 1 OE WE A0 D8-D15 D0-D7 Read-Only Read (x8) (1) VIL VIH V IL VIL VIH VIL High Z Data Out-Even Read (x8) V IL VIH V IL VIL VIH VIH High Z Not Valid Read (x8) V IL VIL V IH VIL VIH X Not Valid High Z Read (x16) V IL VIL V IL VIL VIH X Not Valid Data Out-Even Output Disable V IL XX V I H V IH X High Z High Z Standby X V IH VIH X X X High Z High Z Write-Only Write (x8) (1) VIL VIH VIL VIH VIL VIL High Z Data In-Even Write (x8) V IL VIH V IL VIH VIL VIH High Z Not Valid Write (x8) V IL VIL V IH VIH VIL X Not Valid High Z Write (x16) V IL VIL V IL VIH VIL X Not Valid Data In-Even Output Disable V IL XX V IH VIL X High Z High Z Note: 1. Byte access - Even. In this x8 mode, D0-D7 contain the "even" byte (low byte) of the x16 word. D8-D15 are inactive.
8 AT5FC001
D.C. Characteristics, Byte-Wide Operation Symbol Parameter Condition Min Typ Max Units ILI Input LeakageCurrent VCC = VCC Max, VIN = VCC or VSS 1.0 ±20 µA ILO Output Leakage CurrentVCC = VCC Max, VOUT = VCC or VSS 1.0 20 µA ISB VCC Standby Current VCC = VCC Max, CE = VCC ± 0.2 V 0.4 0.8 mA ICC1 (1) VCC Active Read Current VCC = VCC Max, CE = VIL, OE = VIH, IOUT = 0 mA, at 5 MHz 20 40 mA ICC2 VCC Active Write CurrentCE = VIL,WE = VIL, Programming in Progress 20 40 mA VIL Input Low Voltage 0.8 V VIH Input High Voltage 2.4 V VOL Output Low Voltage I OL = 3.2 mA 0.40 V VOH Output High Voltage I OH = -2.0 mA 3.8 V Notes: 1. One Flash device active, seven in standby. D.C. Characteristics, Word-Wide Operation Symbol Parameter Condition Min Typ Max Units ILI Input LeakageCurrent VCC = VCC Max, VIN = VCC or VSS 1.0 ±20 µA ILO Output Leakage Current VCC = VCC Max, VOUT = VCC or VSS 1.0 20 µA ISB VCC Standby Current VCC = VCC Max, CE = VCC ± 0.2 V 0.4 0.8 mA ICC1 (1) VCC Active Read Current VCC = VCC Max, CE = VIL, OE = VIH, IOUT = 0 mA, at 5 MHz 40 80 mA ICC2 VCC Active Write CurrentCE = VIL, WE = VIL, Programming in Progress 40 80 mA VIL Input Low Voltage 0.8 V VIH Input High Voltage 2.4 V VOL Output Low Voltage I OL = 3.2 mA 0.40 V VOH Output High Voltage I OH = -2.0 mA 3.8 V Notes: 1. Two Flash devices active, six in standby. AT5FC001
A.C. Read Characteristics Symbol Parameter Min Max Units tRC Read Cycle Time 200 ns tCE Chip Enable Access Time 200 ns tACC Address Access Time 200 ns tOE Output Enable Access Time 100 ns tLz Chip Enable to Output in Low Z 5 ns tDF Chip Disable to Output in High Z 60 ns tOLZ Output Enable to Output in Low Z 5 ns tDF Output Disable to Output in High Z 60 ns tOH Output Hold Time from First of Address, CE, or OE Change 5 ns tWC Write Recovery Time Before Read 10 ms Input test Waveforms and Measurement Level tR, tF < 5 ns Output Test Load tOH tDF tDFtWC tOE tCE tLZ tOLZ tACC tRC ADDRESS ADDRESSES STABLE VCC OE WE CE DATA POWER-UP, STANDBY OUTPUT VALID HIGH Z STANDBY, POWER-DOWN DEVICE AND ADDRESS SELECTION OUTPUT ENABLED DATA VALID 5.0 V A.C. Read Waveforms (1) Note: 1. CE refers to CE 1, and/or CE 2
10 AT5FC001
Write Cycle Characteristics Symbol Parameter Min Max Units tWC Write Cycle Time 10 ms tAS Address Set-up Time 10 ns tAH Address Hold Time 60 ns tDS Data Set-up Time 60 ns tDH Data Hold Time 10 ns tWP Write Pulse Width 100 ns tBLC Byte Load Cycle Time 150 µs tWPH Write Pulse Width High 100 ns tAH tDH tWP tWPH tDS tAS tWCtBLC BYTEADDRESS SECTORADDRESS OE WE CE 1 CE 2 DATA BYTE 0 BYTE 1 BYTE 254 BYTE 2 BYTE 255 A1-A7 A8-A19 A.C. Write Waveforms (Byte Mode) Notes: 1. A18 and A19 specify the pair of AT29C010A devices to be written, while A0 controls the selection of even and odd bytes. A0, A18 and A19 must be valid throughout the entire WE low pulse. 2. A8 through A17 must specify the sector address during each high to low transition of WE (or CE ). 3. OE must be high when WE and CE are both low. 4. All bytes that are not loaded within the sector being pro- grammed will be indeterminate. AT5FC001
CE 1,2 DATA WORD 0 WORD 1 WORD 126WORD 2 WORD 127 A1-A7 A8-A19 1. A18 and A19 specify the pair of AT29C010A devices to be writ- ten; they must be valid throughout the entire WE low pulse. A0 is don’t care. 2. A8 through A17 must specify the sector address during each high to low transition of WE (or CE ). 3. OE must be high when WE and CE are both low. 4. All bytes that are not loaded within the sector being pro- grammed will be indeterminate. A.C. Write Waveforms (Word Mode)
12 AT5FC001
Software Data Protected Programming Algorithm (1) D e v i c e 01234567 Data Address AA 0AAAA AA 0AAAB AA 4AAAA AA 4AAAB AA 8AAAA AA 8AAAB AA CAAAA AA CAAAB Data Address 05554 05555 45554 45555 85554 85555 C5554 C5555 Data Address 0AAAA 0AAAB 4AAAA 4AAAB 8AAAA 8AAAB CAAAA CAAAB Writes Enabled Write Bytes Write Bytes Write Bytes Write Bytes Write Bytes Write Bytes Write Bytes Write Bytes Note: 1. Load 3 bytes to corresponding Flash chip segment individually to enable software data protection. Software Data Protected Disable Algorithm (1) D e v i c e 01234567 Data Address AA 0AAAA AA 0AAAB AA 4AAAA AA 4AAAB AA 8AAAA AA 8AAAB AA CAAAA AA CAAAB Data Address 05554 05555 45554 45555 85554 85555 C5554 C5555 Data Address 0AAAA 0AAAB 4AAAA 4AAAB 8AAAA 8AAAB CAAAA CAAAB Data Address AA 0AAAA AA 0AAAB AA 4AAAA AA 4AAAB AA 8AAAA AA 8AAAB AA CAAAA AA CAAAB Data Address 05554 05555 45554 45555 85554 85555 C5554 C5555 Data Address 0AAAA 0AAAB 4AAAA 4AAAB 8AAAA 8AAAB CAAAA CAAAB Writes Enabled Write Bytes Write Bytes Write Bytes Write Bytes Write Bytes Write Bytes Write Bytes Write Bytes Note: 1. Load 6 bytes to corresponding Flash chip segment individually to disable software data protection. AT5FC001
CardWareTM may be trademarks of others. tACC (ns) Ordering Code Package Operation Range
200 AT5FC001-20 PCMCIA Type 1 Commercial
(0°C to 70°C)
Ordering Information
85.6 0.2 mm 10.0 MIN. (mm) 10.0 MIN. (mm) 54.0 0.1 mm 3.3 0.1 mm
34 FRONT SIDE
PCMCIA, Type 1 PC Memory Card Dimensions in millimeters