AT59C11 ATMEL | Alldatasheet

Document overview

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Technical content

Features

  • Low Voltage and Standard Voltage Operation – 5.0 (VCC = 4.5V to 5.5V) – 2.7 (VCC = 2.7V to 5.5V) – 2.5 (VCC = 2.5V to 5.5V)
  • User Selectable Internal Organization – 1K: 128 x 8 or 64 x 16 – 2K: 256 x 8 or 128 x 16 – 4K: 512 x 8 or 256 x 16
  • 4-Wire Serial Interface
  • Self-Timed Write Cycle (10 ms max)
  • High Reliability – Endurance: 1 Million Write Cycles – Data Retention: 100 Years – ESD Protection: >4000V
  • 8-Pin PDIP and 8-Pin EIAJ SOIC Packages

Description

The AT59C11/22/13 provides 1024/2048/4096 bits of serial EEPROM (Electrically Erasable Programmable Read Only Memory) organized as 64/128/256 words of 16 bits each, when the ORG Pin is connected to V CC and 128/256/512 words of 8 bits each when it is tied to ground. The device is optimized for use in many industrial and commercial applications where low power and low voltage operation are essential. The AT59C11/22/13 is available in space saving 8-pin PDIP and 8-pin EIAJ SOIC packages. The AT59C11/22/13 is enabled through the Chip Select pin (CS), and accessed via a 4-wire serial interface consisting of Data Input (DI), Data Output (DO), and Clock (CLK). Upon receiving a READ instruction at DI, the address is decoded and the data is clocked out serially on the data output pin DO, the WRITE cycle is completely self- timed and no separate ERASE cycle is required before WRITE. The WRITE cycle is only enabled when the part is in the ERASE/WRITE ENABLE state. Ready/Busy sta- tus can be monitored upon completion of a programming operation by polling the Ready/Busy pin. sions. 4-Wire Serial EEPROMs 1K (128 x 8 or 64 x 16) 2K (256 x 8 or 128 x 16) 4K (512 x 8 or 256 x 16) AT59C11 AT59C22 AT59C13 Rev. 0173K–07/98 4-Wire, 1K Serial E 2PROMPin Configurations Pin Name Function CS Chip Select CLK Serial Data Clock DI Serial Data Input DO Serial Data Output GND Ground V CC Power Supply ORG Internal Organization RDY/BUSY Status Output 8-Pin PDIP 8-Pin SOIC

Block Diagram(1) Note: 1. When the ORG pin is connected to VCC , the x 16 organization is selected. When it is connected to ground, the x 8 organiza- tion is selected. If the ORG pin is left unconnected, then an internal pullup device will select the x 16 organization. Absolute Maximum Ratings* Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability Voltage on Any Pin

Note: 1. This parameter is characterized and is not 100% tested. Note: 1. V IL min and VIH max are reference only and are not tested. Pin Capacitance(1) Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted). Test Conditions Max Units Conditions C OUT Output Capacitance (DO) 5 pF V OUT = 0V C IN Input Capacitance (CS, CLK, DI, RDY/BUSY)5 p F V IN = 0V DC Characteristics Applicable over recommended operating range from: TAI = -40°C to +85°C, VCC = +2.5V to +5.5V, TAC = 0°C to +70°C, VCC = +2.5V to +5.5V (unless otherwise noted). Symbol Parameter Test Condition Min Typ Max Units VCC1 Supply Voltage 1.8 5.5 V VCC2 Supply Voltage 2.5 5.5 V VCC3 Supply Voltage 2.7 5.5 V VCC4 Supply Voltage 4.5 5.5 V ICC Supply Current V CC = 5.0V READ at 1.0 MHz 0.5 2.0 mA WRITE at 1.0 MHz 0.5 2.0 mA ISB1 Standby Current V CC = 2.5V CS = 0V 6.0 10.0 µA ISB2 Standby Current V CC = 2.7V CS = 0V 6.0 10.0 µA ISB3 Standby Current V CC = 5.0V CS = 0V 21.0 30.0 µA IIL Input Leakage V IN = 0V to VCC 0.1 1.0 µA IOL Output Leakage V IN = 0V to VCC 0.1 1.0 µA VIL1 (1) VIH1 (1) Input Low Voltage Input High Voltage 4.5V ≤ VCC ≤ 5.5V -0.6 2.0 0.8 VCC + 1 V VIL2 (1) VIH2 (1) Input Low Voltage Input High Voltage 2.5V ≤ VCC ≤ 2.7V -0.6 VCC x 0.7 VCC x 0.3 VCC + 1 V VOL1 VOH1 Output Low Voltage Output High Voltage 4.5V ≤ VCC ≤ 5.5V IOL = 2.1 mA IOH = 0.4 mA 2.4 0.4 V VOL2 VOH2 Output Low Voltage Output High Voltage 2.5V ≤ VCC ≤ 2.7V IOL = 0.15 mA IOH = -0.1 mA V CC - 0.2 0.2 V

Note: 1. This paramter is characterized and is not 100% tested. AC Characteristics Applicable over recommended operating range from TA = -40°C to +85°C, VCC = +2.5V to +5.5V, CL = 1 TTL Gate and 100 pF (unless otherwise noted). Symbol Parameter Test Condition Min Typ Max Units fCLK CLK Clock Frequency 4.5V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 5.5V 2.5V ≤ VCC ≤ 5.5V 1.8V ≤ VCC ≤ 5.5V 0.5 0.25 MHz t CKH CLK High Time 4.5V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 5.5V 2.5V ≤ VCC ≤ 5.5V 1.8V ≤ VCC ≤ 5.5V 250 250 500 1000 ns tCKL CLK Low Time 4.5V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 5.5V 2.5V ≤ VCC ≤ 5.5V 1.8V ≤ VCC ≤ 5.5V 250 250 500 1000 ns tCS Minimum CS Low Time 4.5V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 5.5V 2.5V ≤ VCC ≤ 5.5V 1.8V ≤ VCC ≤ 5.5V 250 250 500 1000 ns t CSS CS Setup Time Relative to SK 4.5V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 5.5V 2.5V ≤ VCC ≤ 5.5V 1.8V ≤ VCC ≤ 5.5V 100 200 ns tDIS DI Setup Time Relative to SK 4.5V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 5.5V 2.5V ≤ VCC ≤ 5.5V 1.8V ≤ VCC ≤ 5.5V 100 100 200 400 ns t CSH CS Hold Time Relative to SK 0 ns tDIH DI Hold Time Relative to SK 4.5V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 5.5V 2.5V ≤ VCC ≤ 5.5V 1.8V ≤ VCC ≤ 5.5V 100 100 200 400 ns tPD1 Output Delay to ‘1’ AC Test 4.5V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 5.5V 2.5V ≤ VCC ≤ 5.5V 1.8V ≤ VCC ≤ 5.5V 250 250 500 1000 ns tPD0 Output Delay to ‘0’ AC Test 4.5V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 5.5V 2.5V ≤ VCC ≤ 5.5V 1.8V ≤ VCC ≤ 5.5V 250 250 500 1000 ns t RBD RDY/BUSY Delay to Status Valid AC Test 4.5V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 5.5V 2.5V ≤ VCC ≤ 5.5V 1.8V ≤ VCC ≤ 5.5V 250 250 500 1000 ns tCZ CS to DO in High Impedance AC Test CS = VIL 4.5V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 5.5V 2.5V ≤ VCC ≤ 5.5V 1.8V ≤ VCC ≤ 5.5V 100 100 200 400 ns t WC Write Cycle Time 0.1 10 ms Endurance(1) 5.0V , 25°C, Page Mode 1M Write Cycles

Instruction Set for the AT59C11 Instruction SB Op Code Address Data Commentsx 8 x 16 x 8 x 16 READ 1 10XX A 6 - A0 A5 - A0 Reads data stored in memory, at specified address. EWEN 1 0011 XXXXXXX XXXXXX Write enable must precede all programming modes. WRITE 1 X1XX A 6 - A0 A5 - A0 D 7 - D0 D 15 - D0 Writes memory location An - A0. ERAL 1 0010 XXXXXXX XXXXXX Erases all memory locations. Valid only at VCC = 4.5V to 5.5V . WRAL 1 0001 XXXXXXX XXXXXX D 7 - D0 D 15 - D0 Writes all memory locations. Valid only at VCC = 4.5V to 5.5V . EWDS 1 0000 XXXXXXX XXXXXX Disables all programming instructions. Instruction Set for the AT59C22 Instruction SB Op Code Address Data Commentsx 8 x 16 x 8 x 16 READ 1 10XX A 7 - A0 A6 - A0 Reads data stored in memory, at specified address. EWEN 1 0011 XXXXXXXX XXXXXXX Write enable must precede all programming modes. WRITE 1 X1XX A 7 - A0 A6 - A0 D 7 - D0 D 15 - D0 Writes memory location An - A0. ERAL 1 0010 XXXXXXXX XXXXXXX Erases all memory locations. Valid only at VCC = 4.5V to 5.5V . WRAL 1 0001 XXXXXXXX XXXXXXX D 7 - D0 D 15 - D0 Writes all memory locations. Valid when VCC = 5.0V ± 10% and Disable Register cleared. EWDS 1 0000 XXXXXXXX XXXXXXX Disables all programming instructions.

Instruction Set for the AT59C13 Instruction SB Op Code Address Data Commentsx 8 x 16 x 8 x 16 READ 1 10XX A 8 - A0 A7 - A0 Reads data stored in memory, at specified address. EWEN 1 0011 XXXXXXXXX XXXXXXXX Write enable must precede all programming modes. WRITE 1 X1XX A 8 - A0 A7 - A0 D 7 - D0 D 15 - D0 Writes memory location An - A0. ERAL 1 0010 XXXXXXXXX XXXXXXXX Erases all memory locations. Valid only at VCC = 4.5V to 5.5V . WRAL 1 0001 XXXXXXXXX XXXXXXXX D 7 - D0 D 15 - D0 Writes all memory locations. Valid when VCC = 5.0V ± 10% and Disable Register cleared. EWDS 1 0000 XXXXXXXXX XXXXXXXX Disables all programming instructions.

The AT59C11/22/13 are accessed via a simple and versa- tile 4-wire serial communication interface. Device operation is controlled by six instructions issued by the host proces- sor. A valid instruction starts with a rising edge of CS and consists of a Start Bit (logic ‘1’) followed by the appro- priate Op Code and the desired memory Address location. READ (READ): The Read (READ) instruction contains the Address code for the memory location to be read. After the instruction and address are decoded, data from the selected memory location is available at the serial output pin DO. Output data changes are synchronized with the ris- ing edges of serial clock CLK. It should be noted that a dummy bit (logic ‘0’) precedes the 8- or 16-bit data output string. ERASE/WRITE (EWEN): To assure data integrity, the part automatically goes into the Erase/Write Disable (EWDS) state when power is first applied. An Erase/Write Enable (EWEN) instruction must be executed first before any programming instructions can be carried out. Please note that once in the Erase/Write Enable state, program- ming remains enabled until an Erase/Write Disable (EWDS) instruction is executed or V CC power is removed from the part. WRITE (WRITE): The Write (WRITE) instruction contains the 8 or 16 bits of data to be written into the specified mem- ory location. The self-timed programming cycle, t WP , starts after the last bit of data is received at serial data input pin DI. The Ready/Busy status of the AT59C11/22/13 can be determined by polling the RDY/BUSY pin. A logic ‘0’ at RDY/BUSY indicates that programming is still in progress. A logic ‘1’ indicates that the memory location at the speci- fied address has been written with the data pattern con- tained in the instruction and the part is ready for further instructions. ERASE ALL (ERAL): The Erase All (ERAL) instruction programs every bit in the memory array to the logic ‘1’ state and is primarily used for testing purposes. The Ready/Busy status of the AT59C11/22/13 can be determined by polling the RDY/BUSY pin. The ERAL instruction is valid only at VCC = 5.0V ± 10%. WRITE ALL (WRAL): The Write All (WRAL) instruction programs all memory locations with the data patterns spec- ified in the instruction. The Ready/Busy status of the AT59C11/22/13 can be determined by polling the RDY/BUSY pin. The WRAL instruction is valid only at VCC = 5.0V ± 10%. ERASE/WRITE DISABLE (EWDS): To protect against accidental data disturb, the Erase/Write Disable (EWDS) instruction disables all programming modes and should be executed after all programming operations. The operation of the READ instruction is independent of both the EWEN and EWDS instructions and can be executed at any time. Timing Diagrams Synchronous Data Timing Note: 1. This is the minimum CLK period.

Organization Key for Timing Diagrams I/O Density 1K Density 2K Density 4K x 8 x 16 x 8 x 16 x 8 x 16 AN A6 A5 A7 A6 A8 A7 D N D 7 D 15 D 7 D 15 D 7 D 15 CS CLK DI A N D N D 0 A011000 ... ...DO HIGH-Z CS CLK DI tWC tRBD RDY/BUSY CS CLK DI 00 * XXXXXXX1 ENABLE = 11 *DISABLE = 00

D 011 1 XXXXXXX ...000 RDY/BUSY

tWC (max) (ms) ICC (max) (µA) ISB (max) (µA) fMAX (kHz) Ordering Code Package Operation Range 10 2000 30.0 1000 A T59C11-10PC A T59C11W-10SC 8P3 8S2 Commercial (0°C to 70°C) 30.0 1000 AT59C11-10PI A T59C11W-10SI 8P3 8S2 Industrial (-40°C to 85°C) 10 800 10.0 1000 A T59C11-10PC-2.7 A T59C11W-10SC-2.7 8P3 8S2 Commercial (0°C to 70°C) 10.0 1000 A T59C11-10PI-2.7 A T59C11W-10SI-2.7 8P3 8S2 Industrial (-40°C to 85°C) 10 600 10.0 500 A T59C11-10PC-2.5 A T59C11W-10SC-2.5 8P3 8S2 Commercial (0°C to 70°C) 10.0 500 AT59C11-10PI-2.5 A T59C11W-10SI-2.5 8P3 8S2 Industrial (-40°C to 85°C) Package Type 8P3 8-Lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8S2 8-Lead, 0.200" Wide, Plastic Gull Wing Small Outline (EIAJ SOIC) Options Blank Standard Device (4.5V to 5.5V) -2.7 Low-Voltage (2.7V to 5.5V) -2.5 Low-Voltage (2.5V to 5.5V)

tWC (max) (ms) ICC (max) (µA) ISB (max) (µA) fMAX (kHz) Ordering Code Package Operation Range 10 2000 30.0 1000 A T59C22-10PC AT59C22W-10SC 8P3 8S2 Commercial (0°C to 70°C) 30.0 1000 A T59C22-10PI AT59C22W-10SI 8P3 8S2 Industrial (-40°C to 85°C) 10 800 10.0 1000 AT59C22-10PC-2.7 AT59C22W-10SC-2.7 8P3 8S2 Commercial (0°C to 70°C) 10.0 1000 A T59C22-10PI-2.7 AT59C22W-10SI-2.7 8P3 8S2 Industrial (-40°C to 85°C) 10 600 10.0 500 AT59C22-10PC-2.5 AT59C22W-10SC-2.5 8P3 8S2 Commercial (0°C to 70°C) 10.0 500 A T59C22-10PI-2.5 AT59C22W-10SI-2.5 8P3 8S2 Industrial (-40°C to 85°C) Package Type 8P3 8-Lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8S2 8-Lead, 0.200" Wide, Plastic Gull Wing Small Outline (EIAJ SOIC) Options Blank Standard Device (4.5V to 5.5V) -2.7 Low-Voltage (2.7V to 5.5V) -2.5 Low-Voltage (2.5V to 5.5V)

tWC (max) (ms) ICC (max) (µA) ISB (max) (µA) fMAX (kHz) Ordering Code Package Operation Range 10 2000 30.0 1000 A T59C13-10PC AT59C13W-10SC 8P3 8S2 Commercial (0°C to 70°C) 30.0 1000 AT59C13-10PI AT59C13W-10SI 8P3 8S2 Industrial (-40°C to 85°C) 10 800 10.0 1000 A T59C13-10PC-2.7 AT59C13W-10SC-2.7 8P3 8S2 Commercial (0°C to 70°C) 10.0 1000 AT59C13-10PI-2.7 AT59C13W-10SI-2.7 8P3 8S2 Industrial (-40°C to 85°C) 10 600 10.0 500 A T59C13-10PC-2.5 AT59C13W-10SC-2.5 8P3 8S2 Commercial (0°C to 70°C) 10.0 500 A T59C13-10PI-2.5 AT59C13W-10SI-2.5 8P3 8S2 Industrial (-40°C to 85°C) Package Type 8P3 8-Lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8S2 8-Lead, 0.200" Wide, Plastic Gull Wing Small Outline (EIAJ SOIC) Options Blank Standard Device (4.5V to 5.5V) -2.7 Low-Voltage (2.7V to 5.5V) -2.5 Low-Voltage (2.5V to 5.5V)

.400 (10.16) .355 (9.02) PIN .280 (7.11) .240 (6.10) .037 (.940) .210 (5.33) MAX SEATING PLANE .100 (2.54) BSC .015 (.380) MIN .022 (.559) .014 (.356) .150 (3.81) .115 (2.92) .070 (1.78) .045 (1.14) .325 (8.26) .300 (7.62)

15 REF

.430 (10.9) MAX .012 (.305) .008 (.203) .020 (.508) .012 (.305) .213 (5.41) .205 (5.21) .330 (8.38) .300 (7.62)PIN 1 .050 (1.27) BSC .212 (5.38) .203 (5.16) .080 (2.03) .070 (1.78) .013 (.330) .004 (.102) 8 REF .010 (.254) .007 (.178) .035 (.889) .020 (.508) 8P3, 8-Lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) Dimensions in Inches and (Millimeters) JEDEC STANDARD MS-001 BA 8S2, 8-Lead, 0.200" Wide, Plastic Gull Wing Small Outline (EIAJ SOIC) Dimensions in Inches and (Millimeters)