AT572D740

AT572D740 ATMEL | Alldatasheet

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Technical content

Features

• Dual Core System Integrating an ARM7TDMI ARM Thumb Processor Core and a mAgic DSP for Audio, Communication and Beam-forming Applications
• High Performance DSP Operating at 100 MHz – 1 GFLOPS - 1.5 Gops – 10 Arithmetic Operations per Cycle (4 Multiply, 2 Add/subtract, 1 Add, 1 Subtract Floating and Fixed Point) Allowing Single Cycle FFT Butterfly – Native Support for Complex Arithmetic and Vectorial SIMD Operations: One Complex Multiply with Dual Add/sub per Clock Cycle or Two Real Multiply and Two Add/sub or Simple Scalar Operations – 32-bit Integer and IEEE 40-bit Extended Precision Floating Point Numeric Format – Large Multi-port Data Register File: 512 Registers Organized in Two 4-input 4- output 256-register Banks – Orthogonal VLIW Architecture, Code Compression for Code Size Reduction – Flexible Addressing Capability: 2 Independent Address Generation Units Operating on a 16 Registers Address Register File Supporting Programmable Stride, Circular Pointers and Bit Reversal – 1.7 Mbits of On-chip SRAM:

17 K x 40-bit Data Memory Locations

8 K x 128-bit Program Memory Location, Equivalent to 24K Instructions

– DMA Access to the External Program and Data Memory – Two Main Operating Modes: Run and System Mode – Efficient Optimizing Assembler: Allows Easy Exploitation of the Available Hardware Resources Parallelism

• Utilizes the ARM7TDMI Processor Core with 32 K Byte of Integrated SRAM, Operating at 50 MHz – Fully-programmable External Bus Interface (EBI) Maximum External Address Space of 4 M Bytes Up to 4 Chip Selects Software-programmable 8/16-bit External Data Bus – 8-channel Peripheral Data Controller (PDC) – 8-level Priority, Individually Maskable Vectored Interrupt Controller

4 External, 20 Internal Interrupt Sources, Including a High-priority, Low-latency

– 28 Programmable I/O Lines – 8-channel 11-bit Programmable Clock Prescaler Feeding the Timer, Watchdog, USARTs, SPIs – 3-channel 16-bit Timer/Counter

5 Internal Clock Sources and 3 Configurable Sources (External Source or

Cascaded Timer Configuration)

2 Multi-purpose Output Pins plus 1 Output Dedicated to the ADDA Interface plus

3 Outputs Dedicated to the mAgic DSP

– 2 USARTs

2 Dedicated Peripheral Data Controller (PDC) Channels per USART

1 USART Supporting Full Modem Interface

– 2 Master/Slave SPI Interfaces

2 Dedicated Peripheral Data Controller (PDC) Channels per SPI

8- to 16-bit Programmable Data Length

4 External Slave Chip Selects for each SPI

– Programmable Watchdog Timer – ADDA (A/D and D/A Converters) Interface Supporting up to 4 Analog to Digital and

4 Digital to Analog, Stereo 24-bit Converters

– IEEE 1149.1 JTAG Boundary Scan on all Active Pins

• Efficient ARM - DSP Interface Based on 1K x 40-bit Dual Ported Shared Memory, Memory Mapped Register Access, and Interrupt Lines
• 1.8 V Core Operating Voltage, 3.3 V I/O Operating Voltage
• On-chip PLL for 100 Mhz Operation from 25 Mhz Reference Clock
• 352-ball PBGA Package DIOPSIS 740 Dual Core DSP AT572D740 Summary Note: This is a summary document. A complete document is not available at this time. For more information, please contact your local Atmel sales office.

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7001AS–DPS–03/04 Description DIOPSIS 740 is a Dual CPU Processor integrating a mAgic DSP and an ARM7TDMI™ RISC MCU, plus a total of 245 Kbytes SRAM. The system combines the flexibility of the ARM7TDMI RISC controller with the very high performance of the DSP. mAgic is a high performance VLIW DSP delivering 1 Giga floating-point operations per second (GFLOPS) at a clock rate of 100 MHz. It has 512 data registers, 16 address reg- isters, 10 independent operating units and 2 independent address generation units. For instance, activating all the computing units, it can produce one complete FFT butterfly per cycle. mAgic operates on 32-bit fixed-point and IEEE 754 40-bit extended precision floating-point numeric format. It has also on-chip 17K x 40-bit data memory locations and 8K x 128-bit program memory locations. E fficient usage of the internal program memory is achieved through a code compression mechanism. An optimizing assembler frees the user from the burden of dealing with the parallelism of the processor resources and drastically simplifies the code development. The ARM7TDMI™ embedded micro controller core is a member of the Advanced RISC Machines (ARM ®) family of general purpose 32-bit microprocessors, which offer high performance and very low power consumption. The ARM architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and the related decode mechanism are much simpler than those of micro programmed Complex Instruction Set Computers. This simplicity results in a high instruction throughput and impressive real-time interrupt response. The ARM7TDMI™ supports 16-bit Thumb® subset of the most commonly used 32-bit instructions. These are expanded at run time with no degradation of system performance. This gives 16-bit code density (saving memory area and cost) coupled with 32-bit processor performance. A rich set of peripheral and a 32 Kbytes internal memory provide a highly flexible and integrated system solution.

Table 1. D740 Ball Assignment (243 I/O)

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Table 1. D740 Ball Assignment (243 I/O) (Continued) Table 2. D740 Ball Assignment (VDD = 3.3V)

All balls not comprised in Tables 1 to 5 are “not connected”. Table 3. D740 Ball Assignment (VDDI = 1.8V) Table 4. D740 Ball Assignment (VDDPLL = 1.8V) Table 5. D740 Ball Assignment (GND)

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Table 6. D740 Pin Description

SPI SPI0_NSS[3:1] SPI 0 Output Chip Selects out-02 SPI SLV /g224 n.a. Table 6. D740 Pin Description (Continued)

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SPI SPI1_NSS[3:1] SPI 1 Output Chip Selects out-02 SPI SLV /g224 n.a.

Figure 1. D740 Architecture

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7001AS–DPS–03/04 Architectural Overview DIOPSIS 740 (also named D740) is a high per formance dual-core processing platform for audio, communication and beam-forming applications, integrating a floating-point DSP (mAgic DSP) and an ARM7TDMI™ Reduced Instruction Set Computer (RISC). The D740 is optimally suited for floating point applications with a significant need for complex domain computations like FFT and frequency domain phase-shift algorithms, requiring high dynamic range and maximum numerical precision. The D740 combines the flexibility of the ARM7 RISC controller with the very high perfor- mance of the DSP oriented VLIW architecture of mAgic. System management The availability of a standard RISC on-chip lowers software development effort for non critical and control segments of the application. ARM7TDMI supports the usage of light RTOS and has efficient interrupt management, leaving mAgic fully available for the numerically intensive part of the application. The synchronization between the two pro- cessors can be either based on software polling on semaphores or on interrupts. The ARM is the D740 master processor. The bootstrap sequence of the D740 starts from the bootstrap of the ARM from its external non-volatile memory. The ARM then boots mAgic from a non-volatile memory. After bootstrap the D740 can start its normal operations. The DSP side of many applications can be implemented on the D740 using only the internal memory. In fact the program memory size of 8K by 128-bit coupled with the availability of the code compression, gives an equivalent on-chip program memory size of about 24K instructions (typical). The ARM standard In-Circuit Emulation debug interface is supported via the ICE port. mAgic DSP Processor The mAgic DSP is the VLIW numeric processor of the D740. It operates on IEEE 754 40-bit extended precision floating-point and 32-bit integer numeric format. The main components of the DSP subsystem are the co re processor, the on-chip memories and the interfaces to and from the ARM subsystem. The operators block, the register file, the address generation unit and the program decoding and sequencing unit compose the core processor. A short description of each block is given in the following paragraphs. Core processor mAgic is a VLIW engine, but from an user point of view, it works like a RISC machine by implementing triadic computing operations on data coming from the register file, and data move operations between the local memories and the register file. The operators are pipelined for maximum performance. The pipeline depth depends on the operator used. The operations scheduling and parallelism are automatically defined and man- aged at compile time by the assembler-optimizer, allowing efficient code execution. In order to give the best support to the RISC-like programming model, mAgic is equipped with a complex 256-entry register file. It can be used as a complex register file (real + imaginary part), or as a dual register file for vectorial operations. When performing sin- gle instructions the register file can be used as an ordinary 512 register file. Both the left and right side of the register file are 8-ported, making a total of 16 I/O port available for the data move to and from the operator block and the memory. The total data bandwidth between the register file and the operator block is 70 bytes per clock cycle, avoiding bot- tlenecks in the data flow between the two units.

Figure 2. mAgic DSP Block Diagram extended precision 40-bit floating-point data. 10 floating-point operations per clock cycle. addressing. The address generation unit has 16 registers.

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7001AS–DPS–03/04 Internal memories, External memories and DMA mAgic has four on-chip memory blocks: the Program Memory, the Data Memory, the Data Buffer, and the dual ported memory shared with the ARM processor. An External Memory Interface multiplexes the Data accesses and the Program accesses to and from the External Memory. The Program Memory stores the VLIW program to be executed by mAgic. It is 8K words by 128-bit single port memory. When mAgic is in System Mode the ARM can modify the content of the mAgic Program Memory in two different ways. The ARM can directly write a Program Memory location by accessing the memory address space assigned to the mAgic Program Memory in the ARM memory map. In this access mode the ARM writes four 32-bit words to four consecutive addresses at correct address boundaries, in order to properly complete a single VLIW word write cycle. The ARM can also modify the content of the mAgic Program Memory by initiating a DMA transfer from the External Memory to the mAgic Program Memory. In this access mode a single VLIW word is transferred from the mAgic External Memory to the mAgic Program Memory 64- bit per cycle, that is a complete word every two clock cycles. Due to the program com- pression scheme used, which allows an average program compression between 2 and 3, the code accessing capability of mAgic from its External Memory is greater than an instruction per clock cycle. When mAgic is in Run Mode, the ARM cannot get access to the mAgic Program Memory. When in Run Mode mAgic can initiate a DMA transfer from the External Memory to the mAgic Program Memory to load a new code segment. The mAgic internal Data Memory is made of three memory pages, 2K words by 40-bit for the left data memory and 2K words by 40-bit for the right data memory, giving a total of 6K words for the left and for the right memory banks (a total of 12K words ). Each Data Memory bank is a dual port memory that allows four simultaneous accesses, two read and two write. The core can access vectorial and single data stored in the Data Memory. Accessing complex data is equivalent to accessing vectorial data. During simultaneous read and write memory accesses, the MAGU generates two independent read and write addresses common to both the left and the right memory banks. The total available bandwidth between the Register File and the Data Memory is 20 bytes per clock cycle, allowing full speed implementation of numerically intensive algorithms (e.g. complex FFT and FIR). The Buffer Memory is 2K words by 40-bit for both the left and the right memory. The Buffer Memory is a dual port memory. A port is connected to the core processor. The MAGU generates the Buffer Memory addresses for transferring data to and from the core. The second port of the Buffer Memory is connected to the External Memory Inter- face. The Buffer Memory does not support dual read and write accesses neither from the core nor from the External Memory Interface. The available bandwidth between the core processor and the Buffer Memory is equal to the available bandwidth between the External Memory Interface and the Buffer Memory: 10 bytes per clock cycle. The maxi- mum External Memory size of mAgic is 16 Mword Left and Right (equivalent to 32 Mword or 160 Mbytes; 24-bit address bus). A DMA controller manages the data transfer between the External Memory and the Buffer Memory. The DMA controller can generate accesses with stride for the External Memory. The DMA transfers to and from the Buffer Memory can be executed in parallel with the full speed core instructions execution with zero-overhead and without the intervention of the core processor, except for initiating it. The last memory block in the address spac e of the mAgic DSP is the memory shared (PARM) between mAgic and the ARM processor. It is a dual port memory 512 words by 40- bit for both the left and the right bank (total 1K by 40-bit). This memory can be used to efficiently transfer data between the two processors. The available bandwidth between the core processor and the shared memory is 10 bytes per clock cycle. On the

7001AS–DPS–03/04 ARM side the available bandwidth is limited by the bus size of the ARM processor (32 bits) giving a bandwidth of 4 bytes per ARM clock cycle. ARM interface (mAAr) The D740 master is the ARM7 RISC processor. mAgic behaves as a standard AMBA ASB slave device, allowing access to different resources depending on the operating mode (Run or System). In System Mode, mAgic halts its execution and the ARM takes control of it. When mAgic is in System mode the ARM can access many mAgic internal devices. The ability of the ARM to access internal mAgic resources in System Mode can be used for initialization and debugging purposes. By accessing the Command Register, the ARM can change the operating status of the DSP (Run/System Mode), initiate DMA transactions, force single or multiple step execution, or simply read the DSP operating status. In Run Mode, mAgic works under direct control of its own VLIW program and the ARM has access only to the 1K x 40-bit dual ported shared memory (PARM) and to the mAgic Command Register. In order to allow a tight coupling between the operations of mAgic and the ARM at run time, they can exchange synchronization signals, based on interrupts. ARM System: ARM7TDMI Processor and Peripherals The ARM7TDMI is a 32-bit RISC microprocessor; it is a member of the Advanced RISC Machines (ARM) family of general-purpose 32-bit microprocessors, offering high perfor- mance and very low power consumption. The ARM architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and related decode mechanism are much simpler than those of microprogrammed Complex Instruction Set Computers. This simplicity results in a high instruction throughput and a real-time interrupt response. Pipelining is employed so that all parts of the processing and memory syst ems can operate continuously. The typical operating scheme of the ARM7TDMI is the sequence fetch-decode-execute. The ARM7TDMI processor employs the architectural strategy known as THUMB. THUMB instructions operate with the standard ARM register configuration, allowing excellent interoperability between ARM and THUMB states. Each 16-bit THUMB instruction has a corresponding 32-bit ARM instruction with the same effect on the pro- cessor model. The 16-bit instructions are expanded at run time with no degradation of the system performance. This provides far better performance than a 16-bit architecture, with better code density than a 32-bit architecture. The ARM7TDMI processor is built around a bank of 37 32-bit registers and six status registers. The ARM7TDMI supports seven operation modes: 1. User (usr): The normal ARM program execution state 2. FIQ (fiq): Fast Interrupt reQuest; it is connected to the mAgic Halt signal 3. IRQ (irq): Used for general-purpose interrupt handling 4. Supervisor (svc): Protected mode for the operating system 5. Abort mode (abt): Entered after data or instruction prefetch abort 6. System (sys): A privileged user mode for the operating system 7. Undefined (und):Entered when an undefined instruction is executed Mode changes can be made under software control or can be brought about by external interrupts or exception processing. Most application programs execute in User mode. The non-user modes - known as privileged modes – are entered in order to service interrupts or exceptions, or to access protected resources. Each operating mode has dedicated banked registers for fast exception handling. The FIQ mode has five addi-

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7001AS–DPS–03/04 tional banked working registers, r8_fiq to r12_fiq, to enhance interrupt processing speed. The ARM7TDMI processor operates in little-endian mode. To speed-up critical routine execution or critical data segment access, the ARM7 is equipped with 32 Kbyte of zero wait states on-chip memory. The ARM system has two buses. The main bus is the ASB (ARM System Bus). The APB (ARM Peripheral Bus) is designed for accesses to on-chip peripherals. The AMBA Bridge provides an interface between the ASB and the APB. The D740 is equipped with a set of peripherals controlled by the ARM. An on-chip Peripheral Data Controller (PDC) transfers data between the on-chip USARTs/SPI and the on- and off-chip memories in the DMA without the intervention of the processor. Most importantly, the PDC removes the processor interrupt handling overhead and sig- nificantly reduces the number of clock cycles required for data transfer. Each peripheral has a 16K-byte address space allocated in the upper 3M bytes of the 4Gbyte address space. The peripheral register set is composed of control, mode, data, status, and interrupt registers. To maximize the efficiency of bit manipulation, frequently written registers are mapped into three memory locations. A short description of the available peripherals is given in the following.

• EBI (External Bus Interface): the EBI generates the signals that control the access to the External Memory or peripheral devices.
• ADDA (Analog to Digital and Digital to Analog interface): the ADDA provides 4 channel serial interface toward stereo audio 24-bit ADC and DAC.
• PDC (Peripheral Data Controller): The PDC provides 8 communication channels dedicated to the two USARTs and to the two SPIs. One PDC channel is connected to the receiving channel and the one to the transmitting channel of each peripheral.
• USART (Universal Synchronous / Asynchronous Receiver / Transmitter): two, full- duplex, universal synchronous/asynchronous receiver/transmitters provide a simple standard communication way managed by the Peripheral Data Controller.
• SPI (Serial Peripheral Interface): two four-wire serial interfaces provide a simple industry-standard communication way managed by the Peripheral Data Controller.
• AIC (Advanced Interrupt Controller): the AIC is an 8-level priority, individually- maskable, vectored interrupt controller. The interrupt controller is connected to the NFIQ (fast interrupt request) and the NIRQ (standard interrupt request) inputs of the ARM7TDMI processor.
• PIO (Parallel I/O Controller): The PIO features 32 programmable I/O lines, 28 PIO lines are available on D740 pads, while the remaining 4 are only internal.
• TC (Timer Counter): the TC contains three identical 16-bit timer/counter channels.
• WD (Watchdog Timer): the WD can be used to guard against system lock-up if the software becomes trapped in a deadlock. If an overflow occurs, the watchdog timer generates processor interrupts via the Advanced Interrupt Controller (AIC) and an external low pulse through the PIO.
• CLKGEN (Clock Generator): The clock generator provides divided clocks for several peripherals: the Timer Counter, the Watchdog, the USARTs and the SPIs.

Figure 3. Armsystem Architecture

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7001AS–DPS–03/04 Development Tools D740 is supported with a complete set of software and hardware development tools. MADE The D740 is supported by a set of developm ent tools integrated into a visual develop- ment environment called MADE (Multicore Application Development Environment). MADE provides the user with an integrated environment for producing applications for both the D740 cores, the ARM7TDMI and the mAgic DSP, by means of a common project management and support for the MARMOS Minimal Bios. Code generation tools for the ARM include the GNU Code Development Chain for ARM7 (C-C++ compiler, assembler, linker and utilities) and the ARM SDT Code Devel- opment Chain (C-C++ compiler, assembler, linker and utilities). Code generation tools for mAgic include C compiler (GNU gcc based, ANSI compliant), VLIW assembler-optimizer, code compressor, linker and utilities. MADE supports the MARMOS Minimal Bios, a set of helper functions for the ARM- mAgic intercommunication and the D740 peripherals management. MARMOS gives the user the basic APIs for building an integrated ARM-mAgic application. MADE provides the user wi th a simulation engine and an emulation kernel: the Cycle- Accurate simulator and the D740 emulator board support. JTAG-ICE The ARM Standard In-Circuit-Emulation debug interface is supported via the JTAG-ICE port of the D740. When the ARM ICE configuration is selected, the usual debug capabilities for the ARM System are supported, while the support for the mAgic core is limited to memory and status registers inspection. The 5 jtag pins are shared between ARM7TDMI ICE functionality and the DIOPSIS 740 chip Boundary Scan Logic. The “JCFG” pin acts as ARM jtag / D740 BSL selector. When “JCFG” pin is high the ARM ICE is selected, while DIOPSIS 740 BSL is selected when “JCFG” is low. JTST JTST is a low cost general-purpose module that provides the appropriate resources in order to test DIOPSIS 740. JTST provides the following resources to DIOPSIS 740: – mAgic SSRAM, ARM FLASH and SRAM – 4 Stereo Audio 20 bit CODECs – 1 USB 2.0 Full (12 Mbps) – 2 RS232/LVTTL a/synchronous serial I/O lines – 2 SPI serial I/O lines – Reset Logic (Power ON, Push Button, WDG) – IO connectors (USART, SPI, USB, PIO, AUDIO) – PLL-Clock Logic (25 MHz oscillator + CLK connector) – DIP SWITCH & Status 7-segment Display – Voltage Regulators 5V/3.3V & 5V/1.8V –M - I C E J T A G

7001AS–DPS–03/04 Mechanical Drawing

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Table 7. D740 Dimensions (mm)

• VDDCORE pins, which power the chip core (1.8V)
• VDDIO pins, which power the I/O lines (3.3V)
• VDDPLL pins, which power the oscillator and PLL cells (1.8V) The total power dissipation is the sum of two basic contributions: P D = PIO + PCORE PIO represents the contribute due to the IO pads current and the output load current. PCORE represents the contribute due to the internal activity current. The following table defines the current consumption on different conditions:
• Idd peak = mAgic FFT; both mAgic and ARM ext mem written 100% with continuous toggling data
• Idd high = mAgic FFT; both mAgic and ARM ext mem read and written alternatively 100% with 50% toggling data
• Idd no ext = mAgic FFT; ARM FLASH access 100%; no mAgic ext mem access
• Idd sys mode = mAgic in system mode; ARM FLASH accesses 100%;
• Idd rst = D740 under reset
• typical condition = typical process; Tj = 25°; Vdd = nom
• worst condition = worst process; Tj = 100°; Vdd = nom + 10% To estimate power consumption for a spec ific application use the following equation where % is the amount of time your program spends in that state and each “Idd” contrib- ute corresponds to “IO” or “CORE” columns: P CORE = ((%peak × Idd peak) + (%high × Idd high) + (%no ext × Idd no ext) + (%sys mode × Idd sys mode) + (%rst × Idd rst)) x 1.8 PIO = ((%peak × Idd peak) + (%high × Idd high) + (%no ext × Idd no ext) + (%sys mode × Idd sys mode) + (%rst × Idd rst)) x 3.3 Note: Idd peak represents worst-case processor operation (for Idd IO particularly) and it is not considerable for also for hard applications where all data bits do not toggle every cycle.

Table 8. Power Dissipation

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Table 9. Silicon Block Size

Table 10. Ordering Information

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