AT52BR1672-85CI

AT52BR1672 ATMEL | Alldatasheet

Document overview

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Technical content

Features

• 16-Mbit Flash and 2-Mbit/4-Mbit SRAM  Single 66-ball 8 mm x 10 mm x 1.2 mm CBGA Package  2.7V to 3.3V Operating Voltage Flash  2.7V to 3.3V Read/Write  A c c e s sT i m e–8 5n s  Sector Erase Architecture – Thirty-one 32K Word (64K Byte) Sectors with Individual Write Lockout – Eight 4K Word (8K Byte) Sectors with Individual Write Lockout  Fast Word Program Time – 20 µs  Fast Sector Erase Time – 300 ms  Dual-plane Organization, Permitting Concurrent Read While Program/Erase – Memory Plane A: Eight 4K Word and Seven 32K Word Sectors – Memory Plane B: Twenty-four 32K Word Sectors  Erase Suspend Capability – Supports Reading and Programming from Any Sector by Suspending Erase of a Different Sector – Supports Reading Any Word by Suspending Programming of Any Other Word  Low-power Operation –3 0 m A A c t i v e – 10 µA Standby  Data Polling, Toggle Bit, Ready/Busy for End of Program Detection  VPP Pin for Accelerated Program/Erase Operations  RESET Input for Device Initialization  Sector Lockdown Support  Top/Bottom Block Configuration  128-bit Protection Register SRAM  2-megabit (128K x 16)/4-megabit (256K x 16)  2.7V to 3.3V VCC Operating Voltage  70 ns Access Time  Fully Static Operation and Tri-state Output  1.2V (Min) Data Retention  Industrial Temperature Range Device Number Flash Plane Architecture Flash Configuration SRAM Configuration A T52BR1672(T) 12M + 4M 16M (1M x 16) 2M (128K x 16) A T52BR1674(T) 12M + 4M 16M (1M x 16) 4M (256K x 16) 16-megabit Flash and 2-megabit/ 4-megabit SRAM Stack Memory AT52BR1672(T) AT52BR1674(T) Preliminary Rev. 2604B–STKD–09/02

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2604B–STKD–09/02 CBGA Top View Pin Configurations A14 I/O11 A B C D E F G H 3 456789 1 0 A15 A10 A19 SOE A13 I/O15 I/O13 I/O12 I/O9 CE A12 SWE I/O6 SCS2 I/O10 I/O8 GND GND I/O14 I/O4 SVcc I/O2 I/O0 OE NC I/O7 I/O5 Vcc I/O3 I/O1 SCS1 NC NC A16 WE SGND NC SLB A18 NC A11 RDY BUSY RESET Vpp SUB A17 NC NC NC NC NC NC NC NC 1 2 11 12 Pin Name Function A0 - A16 Flash/SRAM Common Address Input for 2M SRAM A0 - A17 Flash/SRAM Common Address Input for 4M SRAM A18 - A19 Flash Address Input CE Flash Chip Enable OE/SOE Flash/SRAM, Output Enable WE/SWE Flash/SRAM, Write Enable VCC Flash Power Supply VPP Optional Flash Power Supply for Faster Program/Erase Operations I/O0-I/O15 Data Inputs/Outputs SCS1 , SCS2 SRAM Chip Select RDY/BUSY Flash Ready/Busy Output SVCC SRAM Power Supply GND/SGND Flash/SRAM GND SUB SRAM Upper Byte SLB SRAM Lower Byte NC No Connect RESET Flash Reset

AT52BR1672(T)/1674(T) 2604B–STKD–09/02 Description The AT52BR1672(T) combines a 16-megabit Flash (1M x 16) and a 2-megabit SRAM (orga- nized as 128K x 16) in a stacked CBGA package; while the AT52BR1674(T) combines a 16- megabit Flash (1M x 16) and a 4-megabit SRAM (organized as 256K x 16) in a stacked CBGA package. Both devices operate at 2.7V to 3.3V in the industrial temperature range. The mod- ules use a 16-megabit Flash with dual plane architecture for concurrent read/write operations. The Flash is organized as 12M + 4M for planes B and A, respectively. Block Diagram FLASH SRAM ADDRESS DATA RESET CE RDY/BUSY SCS1 WEOE SWE SOE Absolute Maximum Ratings Maximum Ratings”may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. All Input Voltages except V PP and RESET (including NC Pins) Voltage on VPP Voltage on RESET All Output Voltages DC and AC Operating Range AT52BR1672(T)/1674(T) Operating Temperature (Case) Industrial -40 °C-8 5 °C VCC Power Supply 2.7V to 3.3V

4 AT52BR1672(T)/1674(T)

2604B–STKD–09/02 16-megabit Flash

Description

The 16-megabit Flash memory organized as 1,048,576 words of 16 bits each. The x16 data appears on I/O0 - I/O15. The memory is divided into 39 sectors for erase operations.The device has CE and OE control signals to avoid any bus contention. This device can be read or reprogrammed using a single 2.7V power supply, making it ideally suited for in-system programming. The device powers on in the read mode. Command sequences are used to place the device in other operation modes such as program and erase. The device has the capability to protect the data in any sector (see Sector Lockdown section). The device is segmented into two memory planes. Reads from memory plane B may be per- formed even while program or erase functions are being executed in memory plane A and vice versa. This operation allows improved system performance by not requiring the system to wait for a program or erase operation to complete before a read is performed. To further increase the flexibility of the device, it contains an Erase Suspend feature. This feature will put the erase on hold for any amount of time and let the user read data from or program data to any of the remaining sectors within the same memory plane. There is no reason to suspend the erase operation if the data to be read is in the other memory plane. The end of a program or an erase cycle is detected by the Ready/Busy pin, Data Polling or by the toggle bit. The VPP pin provides faster program/erase times. With V PP at 5.0V or 12.0V, the program and erase operations are accelerated. A six-byte command (Enter Single Pulse Program Mode) sequence to remove the requirement of entering the three-byte program sequence is offered to further improve programming time. After entering the six-byte code, only single pulses on the write control lines are required for writing into the device. This mode (Single Pulse Word Program) is exited by powering down the device, or by pulsing the RESET pin low for a minimum of 500 ns and then bringing it back to V CC. Erase and Erase Suspend/Resume commands will not work while in this mode; if entered they will result in data being programmed into the device. It is not recommended that the six-byte code reside in the software of the final product but only exist in external program- ming code.

AT52BR1672(T)/1674(T) 2604B–STKD–09/02 16-megabit Flash Memory Block Diagram IDENTIFIER REGISTER STATUS REGISTER DATA COMPARATOR OUTPUT MULTIPLEXER OUTPUT BUFFER INPUT BUFFER COMMAND REGISTER DATA REGISTER Y-GATING WRITE STATE MACHINE PROGRAM/ERASE VOLTAGE SWITCH RDY/BUSY VPP VCC GND Y-DECODER X-DECODER INPUT BUFFER ADDRESS LATCH I/O0 - I/O15 A0 - A19 PLANE B SECTORS PLANE A SECTORS CE WE OE RESET

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2604B–STKD–09/02 Device Operation READ: The 16-megabit Flash is accessed like an EPROM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins are asserted on the outputs. The outputs are put in the high-impedance state whenever CE or OE is high. This dual-line control gives designers flexibility in preventing bus contention. COMMAND SEQUENCES: When the device is first powered on it will be reset to the read or standby mode, depending upon the state of the control line inputs. In order to perform other device functions, a series of command sequences are entered into the device. The command sequences are shown in the Command Definitions table (I/O8 - I/O15 are don ’t care inputs for the command codes). The command sequences are written by applying a low pulse on the WE or CE input with CE or WE low (respectively) and OE high. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Standard microprocessor write timings are used. The address locations used in the command sequences are not affected by entering the command sequences. RESET: A RESET input pin is provided to ease some system applications. When RESET is at a logic high level, the device is in its standard operating mode. A low level on the RESET input halts the present device operation and puts the outputs of the device in a high-impedance state. When a high level is reasserted on the RESET pin, the device returns to the read or standby mode, depending upon the state of the control inputs. ERASURE: Before a word can be reprogrammed, it must be erased. The erased state of memory bits is a logical “1”. The entire device can be erased by using the Chip Erase com- mand or individual sectors can be erased by using the Sector Erase command. CHIP ERASE: The entire device can be erased at one time by using the six-byte chip erase software code. After the chip erase has been initiated, the device will internally time the erase operation so that no external clocks are required. The maximum time to erase the chip is t EC. If the sector lockdown has been enabled, the chip erase will not erase the data in the sector that has been locked out; it will erase only the unprotected sectors. After the chip erase, the device will return to the read or standby mode. SECTOR ERASE: As an alternative to a full chip erase, the device is organized into 39 sec- tors (SA0 - SA38) that can be individually erased. The Sector Erase command is a six-bus cycle operation. The sector address is latched on the falling WE edge of the sixth cycle while the 30H data input command is latched on the rising edge of WE . The sector erase starts after the rising edge of WE of the sixth cycle. The erase operation is internally controlled; it will automatically time to completion. The maximum time to erase a section is t SEC. When the sec- tor programming lockdown feature is not enabled, the sector will erase (from the same Sector Erase command). An attempt to erase a sector that has been protected will result in the oper- ation terminating in 2 µs. WORD PROGRAMMING: Once a memory block is erased, it is programmed (to a logical “0”) on a word-by-word basis. Programming is accomplished via the internal device command reg- ister and is a four-bus cycle operation. The device will automatically generate the required internal program pulses. Any commands written to the chip during the embedded programming cycle will be ignored. If a hardware reset happens during programming, the data at the location being programmed will be corrupted. Please note that a data “0”cannot be programmed back to a “1”;o n l ye r a s e operations can convert “0”st o “1”s. Programming is completed after the specified t BP cycle time. The Data Polling feature or the Toggle Bit feature may be used to indicate the end of a program cycle. VPP PIN: The circuitry of the 16-megabit Flash is designed so that the device can be pro- grammed or erased from the V CC power supply or from the VPP input pin. When V PP is less than or equal to the VCC pin, the device selects the V CC supply for programming and erase

AT52BR1672(T)/1674(T) 2604B–STKD–09/02 operations. When the VPP pin is greater than the V CC supply, the device will select the V PP input as the power supply for programming and erase operations. The device will allow for some variations between the V PP input and the VCC power supply in its selection of V CC or VPP for program or erase operations. If the VPP pin is within 0.3V of V CC for 2.7V < V CC <3 . 3 V , then the program or erase operations will use V CC and disregard the V PP input signal. When the VPP signal is used to accelerate program and erase operations, the V PP must be in the 5V ± 0.5V or 12V ± 0.5V range to ensure proper operation. The V pp pin can be left unconnected. SECTOR LOCKDOWN: Each sector has a programming lockdown feature. This feature pre- vents programming of data in the designated sectors once the feature has been enabled. These sectors can contain secure code that is used to bring up the system. Enabling the lock- down feature will allow the boot code to stay in the device while data in the rest of the device is updated. This feature does not have to be activated; any sector ’s usage as a write protected region is optional to the user. At power-up or reset all sectors are unlocked. To activate the lockdown for a specific sector, the six-bus cycle Sector Lockdown command must be issued. Once a sector has been locked down, the contents of the sector is read-only and cannot be erased or programmed. SECTOR LOCKDOWN DETECTION: A software method is available to determine if program- ming of a sector is locked down. When the device is in the software product identification mode (see Software Product Identification Entry and Exit sections) a read from address loca- tion 00002H within a sector will show if programming the sector is locked down. If the data on I/O0 is low, the sector can be programmed; if the data on I/O0 is high, the program lockdown feature has been enabled and the sector cannot be programmed. The software product identi- fication exit code should be used to return to standard operation. SECTOR LOCKDOWN OVERRIDE: The only way to unlock a sector that is locked down is through reset or power-up cycles. After power-up or reset, the content of a sector that is locked down can be erased and reprogrammed. ERASE SUSPEND/ERASE RESUME: T h eE r a s eS u s p e n dc o m m a n da l l o w st h es y s t e mt o interrupt a sector erase operation and then program or read data from a different sector within the same plane. Since this device has a dual-plane architecture, there is no need to use the Erase Suspend feature while erasing a sector when you want to read data from a sector in the other plane. After the Erase Suspend command is given, the device requires a maximum time of 15 µs to suspend the erase operation. After the erase operation has been suspended, the plane that contains the suspended sector enters the erase-suspend-read mode. The system can then read data or program data to any other sector within the device. An address is not required during the Erase Suspend command. During a sector erase suspend, another sector cannot be erased. To resume the sector erase operation, the system must write the Erase Resume command. The Erase Resume command is a one-bus cycle command, which does require the plane address (determined by A18 and A19). The device also supports an erase suspend during a complete chip erase. While the chip erase is suspended, the user can read from any sector within the memory that is protected. The command sequence for a chip erase suspend and a sector erase suspend are the same. PRODUCT IDENTIFICATION: The product identification mode identifies the device and man- ufacturer as Atmel. It may be accessed by hardware or software operation. The hardware operation mode can be used by an external programmer to identify the correct programming algorithm for the Atmel product. For details, see “Operating Modes ”on page 13 (for hardware operation) or “Software Product Identification Entry/Exit ”on page 21. The manufacturer and device codes are the same for both modes.

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2604B–STKD–09/02 128-BIT PROTECTION REGISTER: The 16-megabit Flash contains a 128-bit register that can be used for security purposes in system design. The protection register is divided into two 64-bit blocks. The two blocks are designated as block A and block B. The data in block A is non-changeable and is programmed at the factory with a unique number. The data in block B is programmed by the user and can be locked out such that data in the block cannot be repro- grammed. To program block B in the protection register, the four-bus cycle Program Protection Register command must be used as shown in the Command Definition table on page 9. To lock out block B, the four-bus cycle Lock Protection Register command must be used as shown in the Command Definition table. Data bit D1 must be zero during the fourth bus cycle. All other data bits during the fourth bus cycle are don ’t cares. Please see the “Pro- tection Register Addressing Table ” on page 10 for the address locations in the protection register. To read the protection register, the Product ID Entry command is given followed by a normal read operation from an address within the protection register. After reading the protec- tion register, the Product ID Exit command must be given prior to performing any other operation. DATA POLLING: The Flash features Data Polling to indicate the end of a program cycle. Dur- ing a program cycle an attempted read of the last word loaded will result in the complement of the loaded data on I/O7. Once the program cycle has been completed, true data is valid on all outputs and the next cycle may begin. During a chip or sector erase operation, an attempt to read the device will give a “0”on I/O7. Once the program or erase cycle has completed, true data will be read from the device. Data Polling may begin at any time during the program cycle. Please see “Status Bit Table”on page 22 for more details. TOGGLE BIT: In addition to Data Polling, the 16-megabit Flash provides another method for determining the end of a program or erase cycle. During a program or erase operation, suc- cessive attempts to read data from the same memory plane will result in I/O6 toggling between one and zero. Once the program cycle has completed, I/O6 will stop toggling and valid data will be read. Examining the toggle bit may begin at any time during a program cycle. An additional toggle bit is available on I/O2, which can be used in conjunction with the toggle bit that is available on I/O6. While a sector is erase suspended, a read or a program operation from the suspended sector will result in the I/O2 bit toggling. Please see “Status Bit Table ”on page 22 for more details. RDY/BUSY : For the 16-megabit Flash, an open-drain Ready/Busy output pin provides another method of detecting the end of a program or erase operation. RDY/BUSY is actively pulled low during the internal program and erase cycles and is released at the completion of the cycle. The open-drain connection allows for OR-tying of several devices to the same RDY/BUSY line. HARDWARE DATA PROTECTION: The Hardware Data Protection feature protects against inadvertent programs to the Flash in the following ways: (a) V CC sense: if V CC is below 1.8V (typical), the program function is inhibited. (b) V CC power-on delay: once V CC has reached the VCC sense level, the device will automatically time out 10 ms (typical) before programming. (c) Program inhibit: holding any one of OE low, CE high or WE high inhibits program cycles. (d) Noise filter: pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a pro- gram cycle. INPUT LEVELS: While operating with a 2.7V to 3.3V power supply, the address inputs and control inputs (OE ,C E and WE) may be driven from 0 to 5.5V without adversely affecting the operation of the device. The I/O lines can only be driven from 0 to V CC +0 . 6 V . OUTPUT LEVELS: For the 16-megabit Flash, output high levels (V OH) are equal to V CCQ - levels, VCCQ must be regulated to 2.0V ± 10%, while V CC must be regulated to 2.7V - 3.0V (for minimum power).

AT52BR1672(T)/1674(T) 2604B–STKD–09/02 Notes: 1. The DA TA FORMAT shown for each bus cycle is as follows; I/O7 - I/O0 (Hex). In word operation I/O15 - I/O8 are Don ’tC a r e . The ADDRESS FORMAT shown for each bus cycle is as follows: A11 - A0 (Hex). Address A19 through A11 are Don ’tC a r e . 2. Since A11 is a Don ’t Care, AAA can be replaced with 2AA. 3. SA = sector address. Any word address within a sector can be used to designate the sector address (see page 11 for details). 4. Once a sector is in the lockdown mode, data in the protected sector cannot be changed unless the chip is reset or power cycled. 5. PA is the plane address (A19-A18). 6. Either one of the Product ID Exit commands can be used. 7. If data bit D1 is “0”, block B is locked. If data bit D1 is “1”, block B can be reprogrammed. C o m m a n dD e f i n i t i o ni nH e x(1) Command Sequence Bus Cycles 1st Bus Cycle 2nd Bus Cycle 3rd Bus Cycle 4th Bus Cycle 5th Bus Cycle 6th Bus Cycle Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Read 1 Addr D OUT Chip Erase 6 555 AA AAA (2) 55 555 80 555 AA AAA 55 555 10 Sector Erase 6 555 AA AAA 55 555 80 555 AA AAA 55 SA (3)(4) 30 Word Program 4 555 AA AAA 55 555 A0 Addr D IN Enter Single Pulse Program Mode 6 555 AA AAA 55 555 80 555 AA AAA 55 555 A0 Single Pulse Word Program 1A d d r D IN Sector Lockdown 6 555 AA AAA 55 555 80 555 AA AAA 55 SA (3)(4) 60 Erase Suspend 1 XXX B0 Erase Resume 1 PA (5) 30 Product ID Entry 3 555 AA AAA 55 555 90 Product ID Exit (6) 3 555 AA AAA 55 555 F0 Product ID Exit(6) 1 XXX F0 Program Protection Register 4 555 AA AAA 55 555 C0 Addr D IN Lock Protection Register - Block B 4 555 AA AAA 55 555 C0 080 X0 Status of Block B Protection 4 555 AA AAA 55 555 90 80 D OUT (7) Absolute Maximum Ratings* Maximum Ratings”may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. All Input Voltages (including NC Pins) All Output Voltages CC +0 . 6 V Voltage on OE and VPP

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2604B–STKD–09/02 Note: 1. All address lines not specified in the above table must be 0 when accessing the protection register, i.e., A19 - A8 = 0. Protection Register Addressing Table Word Use Block A7 A6 A5 A4 A3 A2 A1 A0

0 F a c t o r y A 10000001

1 F a c t o r y A 10000010

2 F a c t o r y A 10000011

3 F a c t o r y A 10000100

4 U s e r B 10000101

5 U s e r B 10000110

6 U s e r B 10000111

7 U s e r B 10001000

AT52BR1672(T)/1674(T) 2604B–STKD–09/02 Top Boot 16-megabit Flash (12M + 4M) – Sector Address Table Plane Sector Size (Words) x16 Address Range (A19 - A0) B SA0 32K 00000 - 07FFF B SA1 32K 08000 - 0FFFF B SA2 32K 10000 - 17FFF B SA3 32K 18000 - 1FFFF B SA4 32K 20000 - 27FFF B SA5 32K 28000 - 2FFFF B SA6 32K 30000 - 37FFF B SA7 32K 38000 - 3FFFF B SA8 32K 40000 - 47FFF B SA9 32K 48000 - 4FFFF B SA10 32K 50000 - 57FFF B SA11 32K 58000 - 5FFFF B SA12 32K 60000 - 67FFF B SA13 32K 68000 - 6FFFF B SA14 32K 70000 - 77FFF B SA15 32K 78000 - 7FFFF B SA16 32K 80000 - 87FFF B SA17 32K 88000 - 8FFFF B SA18 32K 90000 - 97FFF B SA19 32K 98000 - 9FFFF B SA20 32K A0000 - A7FFF B SA21 32K A8000 - AFFFF B SA22 32K B0000 - B7FFF B SA23 32K B8000 - BFFFF A SA24 32K C0000 - C7FFF A SA25 32K C8000 - CFFFF A SA26 32K D0000 - D7FFF A SA27 32K D8000 - DFFFF A SA28 32K E0000 - E7FFF A SA29 32K E8000 - EFFFF A SA30 32K F0000 - F7FFF A SA31 4K F8000 - F8FFF A SA32 4K F9000 - F9FFF A SA33 4K FA000 - FAFFF A SA34 4K FB000 - FBFFF A SA35 4K FC000 - FCFFF A SA36 4K FD000 - FDFFF A SA37 4K FE000 - FEFFF A SA38 4K FF000 - FFFFF

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2604B–STKD–09/02 Bottom Boot 16-megabit Flash (12M + 4M) – Sector Address Table Plane Sector Size (Words) x16 Address Range (A19 - A0) A SA0 4K 00000 - 00FFF A SA1 4K 01000 - 01FFF A SA2 4K 02000 - 02FFF A SA3 4K 03000 - 03FFF A SA4 4K 04000 - 04FFF A SA5 4K 05000 - 05FFF A SA6 4K 06000 - 06FFF A SA7 4K 07000 - 07FFF A SA8 32K 08000 - 0FFFF A SA9 32K 10000 - 17FFF A SA10 32K 18000 - 1FFFF A SA11 32K 20000 - 27FFF A SA12 32K 28000 - 2FFFF A SA13 32K 30000 - 37FFF A SA14 32K 38000 - 3FFFF B SA15 32K 40000 - 47FFF B SA16 32K 48000 - 4FFFF B SA17 32K 50000 - 57FFF B SA18 32K 58000 - 5FFFF B SA19 32K 60000 - 67FFF B SA20 32K 68000 - 6FFFF B SA21 32K 70000 - 77FFF B SA22 32K 78000 - 7FFFF B SA23 32K 80000 - 87FFF B SA24 32K 88000 - 8FFFF B SA25 32K 90000 - 97FFF B SA26 32K 98000 - 9FFFF B SA27 32K A0000 - A7FFF B SA28 32K A8000 - AFFFF B SA29 32K B0000 - B7FFF B SA30 32K B8000 - F7FFF B SA31 32K C0000 - C7FFF B SA32 32K C8000 - CFFFF B SA33 32K D0000 - D7FFF B SA34 32K D8000 - DFFFF B SA35 32K E0000 - E7FFF B SA36 32K E8000 - EFFFF B SA37 32K F0000 - F7FFF B SA38 32K F8000 - FFFFF

AT52BR1672(T)/1674(T) 2604B–STKD–09/02 Notes: 1. X can be V IL or VIH. 2. Refer to AC programming waveforms on page 18. 3. V H = 12.0V ± 0.5V . 4. Manufacturer Code: 001FH. Device Code: 00C2H (T op Boot); 00C0H (Bottom Boot). 5. See details under “Software Product Identification Entry/Exit ”on page 21. 12V ± 0.5V . DC and AC Operating Range AT52BR1672(T)-85 AT52BR1674(T)-85 Operating Temperature (Case) Industrial -40 °C-8 5 °C- 4 0 °C-8 5 °C VCC Power Supply 2.7V to 3.3V 2.7V to 3.3V Operating Modes Mode CE OE WE RESET VPP Ai I/O Read V IL VIL VIH VIH XA i D OUT Program/Erase(2) VIL VIH VIL VIH VPP (6) Ai D IN Standby/Program Inhibit V IH X(1) XV IH XX H i g h - Z Program Inhibit XX V IH VIH X XV IL XV IH X Output Disable X V IH XV IH XH i g h - Z Reset X X X V IL XX H i g h - Z Product Identification Hardware V IL VIL VIH VIH A1 - A19 = VIL,A 9=V H (3),A 0=V IL Manufacturer Code(4) A1 - A19 = VIL,A 9=V H (3),A 0=V IH Device Code(4) Software(5) VIH A0 = VIL,A 1-A 1 9=V IL Manufacturer Code(4) A0 = VIH,A 1-A 1 9=V IL Device Code(4)

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2604B–STKD–09/02 Notes: 1. In the erase mode, I CC is 50 mA. 2. For 3.3V < V CC <3 . 6 V , ICC (max) = 35 mA. DC Characteristics Symbol Parameter Condition Min Max Units ILI Input Load Current V IN =0 Vt oV CC 10 µA ILO Output Leakage Current V I/O =0 Vt oV CC 10 µA ISB1 VCC Standby Current CMOS CE =V CC -0 . 3 Vt oVCC 10 µA ISB2 VCC Standby Current TTL CE =2 . 0 Vt oVCC 1m A ISB3 VCC Standby Current TTL CE =2 . 0 Vt oVCC,V CC = 2.85V 10 µA ICC (1)(2) VCC Active Read Current f = 5 MHz; I OUT =0m A ,3 . 3 V≤ VCC 30 mA ICC1 VCC Programming Current (VPP =V CC) 45 mA IPP1 VPP Input Load Current VPP =0 V ,VCC =3 . 0 V 1 0 µ A VPP =V CC =3 . 0 V 1 0 µ A ICC2 VCC Programming Current (VPP = 5.0V ± 0.5V) 40 mA IPP2 VPP Programming Current (VPP = 5.0V ± 0.5V) 5m A ICC3 VCC Programming Current (VPP = 12.0V ± 0.5V) 40 mA IPP3 VPP Programming Current (VPP = 12.0V ± 0.5V) 6m A VIL Input Low Voltage 0.6 V VIH Input High Voltage 2.0 V VOL1 Output Low Voltage I OL =2 . 1m A 0 . 4 5 V VOL2 Output Low Voltage I OL =1 . 0m A 0 . 2 0 V VOH1 Output High Voltage IOH =- 4 0 0µ A IOH =- 4 0 0µ A VCCQ <2 . 6 V VCCQ ≥ 2.6V VCCQ -0 . 2 2.4 V V VOH2 Output High Voltage IOH =- 1 0 0µ A IOH =- 1 0 0µ A VCCQ <2 . 6 V VCCQ ≥ 2.6V VCCQ -0 . 1 2.5 V V

AT52BR1672(T)/1674(T) 2604B–STKD–09/02 AC Read Waveforms(1)(2)(3)(4) Notes: 1. CE may be delayed up to tACC -t CE after the address transition without impact on t ACC. 2. OE may be delayed up to tCE -t OE after the falling edge of CE without impact on t CE or by tACC -t OE after an address change without impact on tACC. 3. t DF is specified from OE or CE, whichever occurs first (CL = 5 pF). 4. This parameter is characterized and is not 100% tested. AC Read Characteristics Symbol Parameter AT52BR1672(T)-85 AT52BR1674(T)-85 UnitsMin Max Min Max tACC Address to Output Delay 85 85 ns tCE (1) CE to Output Delay 85 85 ns tOE (2) OE to Output Delay 0 40 0 40 ns tDF (3)(4) CE or OE to Output Float 0 25 0 25 ns tOH Output Hold from OE,C E or Address, whichever occurred first 0 0 ns tRO RESET to Output Delay 100 100 ns OUTPUT VALID OUTPUT HIGH Z RESET OE tOE tCE ADDRESS VALID tDF tOHtACC tRO CE ADDRESS

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2604B–STKD–09/02 Input Test Waveforms and Measurement Level tR,t F <5n s Output Test Load Note: 1. This parameter is characterized and is not 100% tested. Pin Capacitance f=1M H z ,T=2 5 °C(1) Symbol Typ Max Units Conditions CIN 46 p F V IN =0 V COUT 81 2 p F V OUT =0 V

AT52BR1672(T)/1674(T) 2604B–STKD–09/02 AC Word Load Waveforms WE Controlled CE Controlled AC Word Load Characteristics Symbol Parameter Min Max Units tAS,t OES Address, OE Setup Time 0 ns tAH Address Hold Time 40 ns tCS Chip Select Setup Time 0 ns tCH Chip Select Hold Time 0 ns tWP Write Pulse Width (WE or CE)4 0 n s tDS Data Setup Time 30 ns tDH,t OEH Data, OE Hold Time 0 ns tWPH Write Pulse Width High 30 ns

18 AT52BR1672(T)/1674(T)

2604B–STKD–09/02 Program Cycle Waveforms Program Cycle Characteristics Symbol Parameter Min Typ Max Units tBP Word Programming Time (0V < VPP < 4.5V) 20 50 µs tBPVPP Word Programming Time (VPP > 4.5V) 10 25 µs tAS Address Setup Time 0n s tAH Address Hold Time 40 ns tDS Data Setup Time 30 ns tDH Data Hold Time 0n s tWP Write Pulse Width 40 ns tWPH Write Pulse Width High 30 ns tWC Write Cycle Time 70 ns tSR/W Latency between Read and Write Operations 50 ns tRP Reset Pulse Width 500 ns tRH Reset High Time before Read 50 ns tEC Chip Erase Cycle Time (VPP <4 . 5 V ) 12 seconds tECVPP Chip Erase Cycle Time (VPP > 4.5V) 6 seconds tSEC Sector Erase Cycle Time (VPP <4 . 5 V ) 300 400 ms tEPS Erase or Program Suspend Time 15 µs OE PROGRAM CYCLE ADDRESS A055 555 AA AAA tBPtWPHtWP CE WE A0- A 1 9 DATA tAS tAH tWC tDH tDS OUTPUT DATA 555 SR/Wt VALID READ ADDRESS ACCt INPUT DATA

AT52BR1672(T)/1674(T) 2604B–STKD–09/02 Sector or Chip Erase Cycle Waveforms Notes: 1. OE must be high only when WE and CE are both low. 2. For chip erase, the address should be 555. For sector erase, the address depends on what sector is to be erased. (See note 3 under Command Definitions.) 3. For chip erase, the data should be 10H, and for sector erase, the data should be 30H. OE (1) AA80 Note 355 55 555 555 Note 2 AA WORD 0 WORD 1 WORD 2 WORD 3 WORD 4 WORD 5 AAA AAA tWPHtWP CE WE A0 - A19 DATA tAS tAH ECt tDH tDS 555 tWC ADDRESS VALID OUTPUT VALID ACCt t SR/Wt

20 AT52BR1672(T)/1674(T)

2604B–STKD–09/02 Notes: 1. These parameters are characterized and not 100% tested. 2. See t OE spec in “AC Read Characteristics”on page 15. Data Polling Waveforms Notes: 1. These parameters are characterized and not 100% tested. 2. See t OE spec in “AC Read Characteristics”on page 15. Toggle Bit Waveforms(1)(2)(3) Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit. The tOEHP specification must be met by the toggling input(s). 2. Beginning and ending state of I/O6 will vary. 3. Any address location may be used but the address should not vary. Data Polling Characteristics(1) Symbol Parameter Min Typ Max Units tDH Data Hold Time 10 ns tOEH OE Hold Time 10 ns tOE OE to Output Delay(2) ns tWR Write Recovery Time 0 ns Toggle Bit Characteristics(1) Symbol Parameter Min Typ Max Units t DH Data Hold Time 10 ns tOEH OE Hold Time 10 ns tOE OE to Output Delay(2) ns tOEHP OE High Pulse 50 ns tWR Write Recovery Time 0 ns

AT52BR1672(T)/1674(T) 2604B–STKD–09/02 Software Product Identification Entry(1) Software Product Identification Exit(1)(6) Notes: 1. Data Format: I/O15 - I/O8 (Don ’t Care); I/O7 - I/O0 (Hex) Address Format: A11 - A0 (Hex) and A11 - A19 (Don ’tC a r e ) . 2. A1 - A19 = V IL. Manufacturer Code is read for A0 = V IL; Device Code is read for A0 = VIH. Additional Device Code is read for address 0003H 3. The device does not remain in identification mode if powered down. 4. The device returns to standard operation mode. 5. Manufacturer Code: 001FH. Device Code: 00C2H (T op Boot); 00C0H (Bottom Boot). Additional Device Code: 00C8H. 6. Either one of the Product ID Exit commands can be used. LOAD DATA AA TO ADDRESS 555 LOAD DATA 55 TO ADDRESS AAA LOAD DATA 90 TO ADDRESS 555 ENTER PRODUCT IDENTIFICATION MODE(2)(3)(5) LOAD DATA AA TO ADDRESS 555 LOAD DATA 55 TO ADDRESS AAA LOAD DATA F0 TO ADDRESS 555 EXIT PRODUCT IDENTIFICATION MODE(4) OR LOAD DATA F0 TO ANY ADDRESS EXIT PRODUCT IDENTIFICATION MODE(4) Sector Lockdown Enable Algorithm(1) Notes: 1. Data Format: I/O15 - I/O8 (Don ’t Care); I/O7 - I/O0 (Hex) Address Format: A11 - A0 (Hex) and A11 - A19 (Don ’t Care). 2. Sector Lockdown feature enabled. LOAD DATA AA TO ADDRESS 555 LOAD DATA 55 TO ADDRESS AAA LOAD DATA 80 TO ADDRESS 555 LOAD DATA AA TO ADDRESS 555 LOAD DATA 55 TO ADDRESS AAA LOAD DATA 60 TO SECTOR ADDRESS PAUSE 200 µs(2)

22 AT52BR1672(T)/1674(T)

2604B–STKD–09/02 Status Bit Table Status Bit I/O7 I/O6 I/O2 Read Address In Plane A Plane B Plane A Plane B Plane A Plane B While Programming in Plane A I/O7 DATA TOGGLE DA TA 1 DATA Programming in Plane B DA TA I/O7 DA TA TOGGLE DATA 1 Erasing in Plane A 0 DATA TOGGLE DA TA TOGGLE DATA Erasing in Plane B DA TA 0 DA TA TOGGLE DATA TOGGLE Erase Suspended & Read Erasing Sector 1 1 1 1 TOGGLE TOGGLE Erase Suspended & Read Non-erasing Sector DATA DATA DATA DATA DATA DATA Erase Suspended & Program Non-erasing Sector in Plane A I/O7 DATA TOGGLE DA TA TOGGLE DATA Erase Suspended & Program Non-erasing Sector in Plane B DATA I/O7 DA TA TOGGLE DATA TOGGLE

AT52BR1672(T)/1674(T) 2604B–STKD–09/02 2-megabit SRAM The 2-megabit SRAM is a high-speed, super low-power CMOS SRAM organized as 128K words by 16 bits. The SRAM uses high-performance full CMOS process technology and is designed for high-speed and low-power circuit technology. It is particularly well-suited for the high-density low-power system application. This device has a data retention mode that guar- antees data to remain valid at a minimum power supply voltage of 1.2V.  Fully Static Operation and Tri-state Output  TTL Compatible Inputs and Outputs  Battery Backup – 1.2V (Min) Data Retention Block Diagram Voltage (V) Speed (ns) Operation Current/ICC (mA) (Max) Standby Current (µA) (Max) Temperature (°C) 2.7 - 3.3 70 10 10 -40 - 85 MEMORY ARRAY 512K X 16 I/O0 SUB SLB SOE SCS2 SCS1 SWE DATA I/O BUFFER SENSE AMPWRITE DRIVER I/O7 I/O8 I/O15 ROW DECODER COLUMN DECODER BLOCK DECODER PRE DECODER ADD INPUT BUFFER A16

24 AT52BR1672(T)/1674(T)

2604B–STKD–09/02 Note: 1. Stresses greater than those listed under “Absolute Maximum Ratings ”may cause permanent damage to the device. This is stress rating only and the functional operation of the device under these or any other conditions above those indicated in the operation of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect reliability. Notes: 1. H = V IH,L=V IL,X=D o n ' tC a r e( VIL or VIH) 2. SUB ,S L B(Upper, Lower Byte Enable). These active LOW inputs allow individual bytes to be written or read. When SLB is LOW, data is written or read to the lower byte, I/O0 - I/O8. When SUB is LOW, data is written or read to the upper byte, I/O9 - I/O16. Note: 1. Undershoot: V IL = -1.5V for pulse width less than 30 ns. Undershoot is sampled, not 100% tested. Absolute Maximum Ratings(1) Symbol Parameter Rating Unit VIN,V OUT Input/Output Voltage -0.3 to 3.6 V VCC Power Supply -0.3 to 4.6 V TA Operating T emperature -40 to 85 °C TSTG Storage Temperature -55 to 150 °C PD Power Dissipation 1.0 W Truth Table SCS1 SCS2 SWE SOE SLB(2) SUB(2) Mode I/O Pin PowerI/O0 - I/O7 I/O8 - I/O15 H(1) X XX XX Deselected High-Z High-Z StandbyX(1) L XX H H L(1) HHH LH Output Disabled High-Z High-Z ActiveHL LL LH L X LH Write DIN High-Z ActiveHL H i g h - Z D IN LL D IN DIN LH H L LH Read DOUT High-Z ActiveHL H i g h - Z D OUT LL D OUT DOUT Recommended DC Operating Condition Symbol Parameter Min Typ Max Unit VCC Supply Voltage 2.3 3.0 3.3 V VSS Ground 0 0 0 V VIH Input High Voltage 2.2 V CC +0 . 3 V VIL (1) Input Low Voltage -0.2 (1) 0.4 V

AT52BR1672(T)/1674(T) 2604B–STKD–09/02 Note: 1. Typical values are at V CC =3 . 0 V ,TA =2 5°C. T ypical values are not 100% tested. Note: 1. These parameters are sampled and not 100% tested. TA =- 4 0°Ct o8 5°C Symbol Parameter Test Condition Min Typ (1) Max Unit ILI Input Leakage Current V SS <V IN <V CC -1 1 µA ILO Output Leakage Current V SS <V OUT <V CC, SCS1 =V IH or SCS2=VIL or SOE =V IH or SWE =V I Lo r SUB =V IH,S L B=V IH -1 1 µA ICC Operating Power Supply Current SCS1 =V IL,S C S 2 = VIH, VIN =V IH or VIL,I I/O =0m A 51 0 m A ICC1 Average Operating Current Cycle Time = 1 µs II/O =0m A , SCS1 = 0.2V , SCS2 = VCC -0.2V , VIN ≤ 0.2V or VIN ≥ VCC -0 . 2 V 46 m A Cycle Time = Min, 100% Duty, II/O =0m A SCS1 =V IL,S C S 2=VIH, VIN =V IH or VIL 30 45 mA ISB Standby Current (TTL Input) SCS1 =V IH or SCS2 = VIL 0.5 mA ISB1 Standby Current (CMOS Input) SCS1 ≥ VCC -0 . 2 V or SCS2 ≤ VSS +0 . 2 V LL 0.4 10 µA SL 2 µA VOL Output Low I OL =0 . 5m A 0 . 4 V VOH Output High I OH =- 0 . 5m A 2 . 0 V Capacitance(1) (Temp = 25°C, f = 1.0 MHz) Symbol Parameter Condition Max Unit CIN Input Capacitance (Add, SCS1 , SCS2, SLB,S U B,S W E,S O E) VIN =0V 8 p F COUT Output Capacitance (I/O) V I/O =0V 1 0 p F

26 AT52BR1672(T)/1674(T)

2604B–STKD–09/02 AC Characteristics TA =- 4 0°Ct o8 5°C, Unless Otherwise Specified # Symbol Parameter 70 ns UnitMin Max 1t RC Read Cycle Time 70 ns 2t AA Address Access Time 70 ns 3t ACS Chip Select Access Time 70 ns 4t OE Output Enable to Output Valid 35 ns 5t BA SLB,S U BAccess Time 35 ns 6t CLZ Chip Select to Output in Low Z 5 ns 7t OLZ Output Enable to Output in Low Z 0 ns 8t BLZ SLB,S U BEnable to Output in Low Z 0 ns 9t CHZ Chip Deselection to Output in High Z 0 30 ns 10 t OHZ Out Disable to Output in High Z 0 30 ns 11 t BHZ SLB,S U BDisable to Output in High Z 0 30 ns 12 t OH Output Hold from Address Change 10 ns 13 t WC W r i t eC y c l eT i m e 7 0 n s 14 t CW Chip Selection to End of Write 60 ns 15 t AW Address Valid to End of Write 60 ns 16 t BW SLB,S U BV a l i dt oE n do fW r i t e 6 0 n s 17 t AS Address Setup Time 0 ns 18 t WP Write Pulse Width 50 ns 19 t WR Write Recovery Time 0 ns 20 t WHZ Write to Output in High Z 0 25 ns 21 t DW Data to Write Time Overlap 30 ns 22 t DH Data Hold from Write Time 0 ns 23 t OW Output Active from End of Write 5 ns AC Test Conditions TA = -4 0°Ct o8 5°C, Unless Otherwise Specified Parameter Value Input Pulse Level 0.4V to 2.2V Input Rise and Fall Time 5 ns Input and Output Timing Reference Level 1.5V Output Load CL = 5 pF + 1 TTL Load CL = 5 pF + 1 TTL Load CL = 30 pF + 1 TTL Load CL = 30 pF + 1 TTL Load

AT52BR1672(T)/1674(T) 2604B–STKD–09/02 Output Test Load Timing Diagrams Read Cycle 1(1),(4) Read Cycle 2(1),(2),(4) Read Cycle 3(1),(2),(4) Notes: 1. Read Cycle occurs whenever a high on the SWE and SOE is low, while SUB and/or SLB and SCS1 and SCS2 are in active status. 2. SOE =V IL. 3. Transition is measured + 200 mV from steady state voltage. This parameter is sampled and not 100% tested. 4. SCS1 in high for the standby, low for active. SCS2 in low for the standby, high for active. SUB and SLB in high for the standby, low for active. ADDRESS SOE SUB, SLB SCS1 SCS2 DATA OUT HIGH-Z DATA VALID tAA tRC tBA tACS tOE tOLZ tBLZ tCLZ tBHZ tCHZ tOH tOHZ (3) (3) (3) (3) (3) (3) DATA OUT ADDRESS tAA PREVIOUS DATA tOH DATA VALID tOH tRC SUB, SLB SCS1 SCS2 DATA OUT tACS tCLZ (3) DATA VALID tCHZ (3)

28 AT52BR1672(T)/1674(T)

2604B–STKD–09/02 W r i t eC y c l e1( S W EControlled)(1),(4),(8) W r i t eC y c l e2( S C S 1, SCS2 Controlled)(1),(4),(8) Notes: 1. A write occurs during the overlap of a low SWE ,al o wS C S 1, a high SCS2 and a low SUB and/or SLB. 2. t WR is measured from the earlier of SCS1 ,S L B,S U B,o rS W Egoing high or SCS2 going low to the end of write cycle. 3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the output must not be applied. 4. If the SCS1 ,S L Band SUB low transition and SCS2 high transition occur simultaneously with the SWE low transition or after the SWE transition, outputs remain in a high impedance state. 5. Q (data out) is the same phase with the write data of this write cycle. 6. Q (data out) is the read data of the next address. 7. Transition is measured + 200 mV from steady state. This parameter is sampled and not 100% tested. 8. SCS1 in high for the standby, low for active SCS2 in low for the standby, high for active. SUB and SLB in high for the standby, low for active. ADDRESS SWE SUB, SLB DATA IN SCS1 SCS2 DATA OUT tWC tCW tAW tBW tWP tAS tWHZ tWR tDW tDH tOW DATA VALIDHIGH-Z tAS (2) (5) (5) (3)(7) ADDRESS SWE SUB, SLB DATA IN SCS1 SCS2 DATA OUT tWC tCW tAW tBW tWP tAS tWR tDW tDH DATA VALIDHIGH-Z (2) HIGH-Z

AT52BR1672(T)/1674(T) 2604B–STKD–09/02 Notes: 1. Typical values are under the condition of T A =2 5°C. T ypical values are sampled and not 100% tested. 2. t RC is read cycle time. Data Retention Timing Diagram 1 Data Retention Timing Diagram 2 Data Retention Electric Characteristic TA =- 4 0°Ct o8 5°C Symbol Parameter Test Condition Min Typ Max Unit VDR VCC for Data Retention SCS1 >V CC -0.2V, SCS2 ≤ 0.2V or VCC -0 . 2 V , VSS ≤ VIN ≤ VCC 1.2 3.3 V ICCDR Data Retention Current V CC =3 . 0 V , SCS1 >V CC -0 . 2 Vo r SCS2 ≤ VSS +0 . 2 Vo r VSS ≤ VIN ≤ VCC 9.5 µA 0.4(1) 0.7 µA tCDR Chip Deselect to Data Retention Time See Data Retention Timing Diagram 0n s tR Operating Recovery Time t RC (2) ns DATA RETENTION MODE tRtCDR VCC SCS1 > VCC - 0.2V 2.3V IH VDR SCS1 VSS VCC 2.3V VDR SCS2 VSS 0.4V DATA RETENTION MODE tRtCDR SCS2 < 0.2V

30 AT52BR1672(T)/1674(T)

2604B–STKD–09/02 4-megabit SRAM The 4-megabit SRAM is a high-speed, super low-power CMOS SRAM organized as 256K words by 16 bits. The SRAM uses high-performance full CMOS process technology and is designed for high-speed and low-power circuit technology. It is particularly well-suited for the high-density low-power system application. This device has a data retention mode that guar- antees data to remain valid at a minimum power supply voltage of 1.2V.  Fully Static Operation and Tri-state Output  TTL Compatible Inputs and Outputs  Battery Backup – 1.2V (Min) Data Retention Block Diagram Voltage (V) Speed (ns) Operation Current/ICC (mA) (Max) Standby Current (µA) (Max) Temperature (°C) 2.7 - 3.3 70 5 15 -40 - 85 MEMORY ARRAY 256K X 16 I/O0 SUB SLB SOE SCS2 SCS1 SWE DATA I/O BUFFER SENSE AMPWRITE DRIVER I/O7 I/O8 I/O15 ROW DECODER COLUMN DECODER BLOCK DECODER PRE DECODER ADD INPUT BUFFER A17

AT52BR1672(T)/1674(T) 2604B–STKD–09/02 Note: 1. Stresses greater than those listed under “Absolute Maximum Ratings ”may cause permanent damage to the device. This is stress rating only and the functional operation of the device under these or any other conditions above those indicated in the operation of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect reliability. Notes: 1. H = V IH,L=V IL,X=D o n ' tC a r e( VIL or VIH) 2. SUB ,S L B(Upper, Lower Byte Enable). These active LOW inputs allow individual bytes to be written or read. When SLB is LOW, data is written or read to the lower byte, I/O0 - I/O7. When SUB is LOW, data is written or read to the upper byte, I/O8 - I/O15. Note: 1. Undershoot: V IL = -1.5V for pulse width less than 30 ns. Undershoot is sampled, not 100% tested. Absolute Maximum Ratings(1) Symbol Parameter Rating Unit VIN,V OUT Input/Output Voltage -0.3 to 3.6 V VCC Power Supply -0.3 to 4.6 V TA Operating T emperature -40 to 85 °C TSTG Storage Temperature -55 to 150 °C PD Power Dissipation 1.0 W Truth Table SCS1 SCS2 SWE SOE SLB(2) SUB(2) Mode I/O Pin PowerI/O0 - I/O7 I/O8 - I/O15 H(1) X XX XX Deselected High-Z High-Z StandbyX(1) L XX HH L(1) HHH LH Output Disabled High-Z High-Z ActiveHL LL LHLX LH Write DIN High-Z Active HL H i g h - Z D IN LL DIN DIN DIN High-Z LHHL LH Read DOUT High-Z Active HL H i g h - Z D OUT LL DOUT DOUT DOUT High-Z Recommended DC Operating Condition Symbol Parameter Min Typ Max Unit VCC Supply Voltage 2.7 3.0 3.3 V VSS Ground 0 0 0 V VIH Input High Voltage 2.2 V CC +0 . 3 V VIL (1) Input Low Voltage -0.31 (1) 0.6 V

32 AT52BR1672(T)/1674(T)

2604B–STKD–09/02 Note: 1. These parameters are sampled and not 100% tested. TA =- 4 0°Ct o8 5°C Symbol Parameter Test Condition Min Max Unit ILI Input Leakage Current V SS <V IN <V CC -1 1 µA ILO Output Leakage Current V SS <V OUT <V CC, SCS1 =V IH or SCS2=VIL or SOE =V IH or SWE =V I Lo r SUB =V IH,S L B=V IH -1 1 µA ICC Operating Power Supply Current SCS1 =V IL,S C S 2 = VIH, VIN =V IH or VIL,I I/O =0m A 5m A ICC1 Average Operating Current SCS1 =V IL,S C S 2=VIH, VIN =V IH or VIL,C y c l eT i m e=M i n 100% Duty, II/O =0m A 35 mA SCS1 < 0.2V , SCS2 > VCC -0 . 2 V VIN <0 . 2 Vo rVIN >V CC -0 . 2 V , C y c l eT i m e=1µ s 100% Duty, II/O =0m A 5m A ISB Standby Current (TTL Input) SCS1 =V IH or SCS2 = VIL or SUB,S L B=V IH VIN =V IH or VIL 0.5 mA ISB1 Standby Current (CMOS Input) SCS1 >V CC -0 . 2 Vo r SCS2 < VSS +0 . 2 Vo r SUB,S L B>V CC -0 . 2 V VIN >V CC -0 . 2 Vo r VIN <V SS +0 . 2 V SL 4 µA LL 15 µA VOL Output Low I OL =0 . 1m A 0 . 4 V VOH Output High I OH =- 0 . 1m A 2 . 4 V Capacitance(1) (Temp = 25°C, f = 1.0 MHz) Symbol Parameter Condition Max Unit CIN Input Capacitance (Add, SCS1 , SCS2, SLB,S U B,S W E,S O E) VIN =0V 8 p F COUT Output Capacitance (I/O) V I/O =0V 1 0 p F

AT52BR1672(T)/1674(T) 2604B–STKD–09/02 AC Characteristics TA =- 4 0°Ct o8 5°C, Unless Otherwise Specified # Symbol Parameter 70 ns UnitMin Max 1t RC Read Cycle Time 70 ns 2t AA Address Access Time 70 ns 3t ACS Chip Select Access Time 70 ns 4t OE Output Enable to Output Valid 35 ns 5t BA SLB,S U BAccess Time 70 ns 6t CLZ Chip Select to Output in Low Z 10 ns 7t OLZ Output Enable to Output in Low Z 5 ns 8t BLZ SLB,S U BEnable to Output in Low Z 10 ns 9t CHZ Chip Deselection to Output in High Z 0 30 ns 10 t OHZ Out Disable to Output in High Z 0 30 ns 11 t BHZ SLB,S U BDisable to Output in High Z 0 30 ns 12 t OH Output Hold from Address Change 10 ns 13 t WC W r i t eC y c l eT i m e 7 0 n s 14 t CW Chip Selection to End of Write 60 ns 15 t AW Address Valid to End of Write 60 ns 16 t BW SLB,S U BV a l i dt oE n do fW r i t e 6 0 n s 17 t AS Address Setup Time 0 ns 18 t WP Write Pulse Width 50 ns 19 t WR Write Recovery Time 0 ns 20 t WHZ Write to Output in High Z 0 20 ns 21 t DW Data to Write Time Overlap 30 ns 22 t DH Data Hold from Write Time 0 ns 23 t OW Output Active from End of Write 5 ns AC Test Conditions TA = -4 0°Ct o8 5°C, Unless Otherwise Specified Parameter Value Input Pulse Level 0.4V to 2.2V Input Rise and Fall Time 5 ns Input and Output Timing Reference Level 1.5V Output Load CL = 5 pF + 1 TTL Load CL = 5 pF + 1 TTL Load CL = 30 pF + 1 TTL Load CL = 30 pF + 1 TTL Load

34 AT52BR1672(T)/1674(T)

2604B–STKD–09/02 Output Test Load Timing Diagrams Read Cycle 1(1),(4) Read Cycle 2(1),(2),(4) Read Cycle 3(1),(2),(4) Notes: 1. Read Cycle occurs whenever a high on the SWE and SOE is low, while SUB and/or SLB and SCS1 and SCS2 are in active status. 2. SOE =V IL. 3. Transition is measured + 200 mV from steady state voltage. This parameter is sampled and not 100% tested. 4. SCS1 in high for the standby, low for active. SCS2 in low for the standby, high for active. SUB and SLB in high for the standby, low for active. ADDRESS SOE SUB, SLB SCS1 SCS2 DATA OUT HIGH-Z DATA VALID tAA tRC tBA tACS tOE tOLZ tBLZ tCLZ tBHZ tCHZ tOH tOHZ (3) (3) (3) (3) (3) (3) DATA OUT ADDRESS tAA PREVIOUS DATA tOH DATA VALID tOH tRC SUB, SLB SCS1 SCS2 DATA OUT tACS tCLZ (3) DATA VALID tCHZ (3)

AT52BR1672(T)/1674(T) 2604B–STKD–09/02 W r i t eC y c l e1( S W EControlled)(1),(4),(8) W r i t eC y c l e2( S C S 1, SCS2 Controlled)(1),(4),(8) Notes: 1. A write occurs during the overlap of a low SWE ,al o wS C S 1, a high SCS2 and a low SUB and/or SLB. 2. t WR is measured from the earlier of SCS1 ,S L B,S U B,o rS W Egoing high or SCS2 going low to the end of write cycle. 3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the output must not be applied. 4. If the SCS1 ,S L Band SUB low transition and SCS2 high transition occur simultaneously with the SWE low transition or after the SWE transition, outputs remain in a high impedance state. 5. Q (data out) is the same phase with the write data of this write cycle. 6. Q (data out) is the read data of the next address. 7. Transition is measured + 200 mV from steady state. This parameter is sampled and not 100% tested. 8. SCS1 in high for the standby, low for active SCS2 in low for the standby, high for active. SUB and SLB in high for the standby, low for active. ADDRESS SWE SUB, SLB DATA IN SCS1 SCS2 DATA OUT tWC tCW tAW tBW tWP tAS tWHZ tWR tDW tDH tOW DATA VALIDHIGH-Z tAS (2) (5) (5) (3)(7) ADDRESS SWE SUB, SLB DATA IN SCS1 SCS2 DATA OUT tWC tCW tAW tBW tWP tAS tWR tDW tDH DATA VALIDHIGH-Z (2) HIGH-Z

36 AT52BR1672(T)/1674(T)

2604B–STKD–09/02 Note: 1. Typical values are under the condition of T A =2 5°C. T ypical values are sampled and not 100% tested. 2. t RC is read cycle time. Data Retention Timing Diagram 1 Data Retention Timing Diagram 2 Data Retention Electric Characteristic TA =- 4 0°Ct o8 5°C Symbol Parameter Test Condition Min Typ (1) Max Unit VDR VCC for Data Retention SCS1 >V CC -0 . 2 Vo r SCS2 < VSS +0 . 2 Vo r SUB,S L B>V CC -0 . 2 V VIN >V CC -0 . 2 Vo r VIN <V SS +0 . 2 V 1.2 3.3 V ICCDR Data Retention Current Vcc=1.5V , SCS1 >V CC -0 . 2 Vo r SCS2 < VSS +0 . 2 Vo r SUB,S L B>V CC -0 . 2 V VIN >V CC -0 . 2 Vo r VIN <V SS +0 . 2 V SL 0.1 2 µA LL 0.1 10 µA tCDR Chip Deselect to Data Retention Time See Data Retention Timing Diagram 0n s tR Operating Recovery Time t RC (2) ns DATA RETENTION MODE tRtCDR VCC SCS1 > VCC - 0.2V 2.7V IH VDR SCS1 VSS VCC 2.7V VDR SCS2 VSS 0.4V DATA RETENTION MODE tRtCDR SCS2 < 0.2V

AT52BR1672(T)/1674(T) 2604B–STKD–09/02

Ordering Information

tACC (ns) Voltage Range Ordering Code Package Operation Range 85 2.7V - 3.3V AT52BR1672(T)-85CI 66C5 Industrial (-40° to 85°C) 85 2.7V - 3.3V AT52BR1674(T)-85CI 66C5 Industrial (-40° to 85°C) 85 2.7V - 3.3V AT52BR1672-85CI 66C5 Industrial (-40° to 85°C) 85 2.7V - 3.3V AT52BR1674-85CI 66C5 Industrial (-40° to 85°C) Package Type 66C5 66-ball, Plastic Chip-scale Ball Grid Array Package (CBGA)

38 AT52BR1672(T)/1674(T)

2604B–STKD–09/02 Package Drawing 66C5 – CBGA

2325 Orchard Parkway

San Jose, CA 95131 TITLE DRAWING NO. R REV. 66C5, 66-ball (12 x 8 Array), 10 x 8 x 1.2 mm Body, 0.8 mm Ball Pitch Chip-scale Ball Grid Array Package (CBGA) A66C5 09/19/01 Side View A 0.12 Seating PlaneC C Top View Bottom View

0.60 REF

E D A1 Ball Corner Øb Marked A1 Identifier A B C D E F G H 123456789101112

1.20 REF

e e COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE E 9.90 10.00 10.10 E1 – 8.80 – D 7.90 8.00 8.10 D1 – 5.60 – A – – 1.20 A1 0.25 – – e 0.80 BSC Øb – 0.40 –

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