AT52BC1661A ATMEL | Alldatasheet

Document overview

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Technical content

Features

  • 16-Mbit (x16) Flash and 8-Mbit PSRAM
  • 2.7V to 3.3V Operating Voltage
  • Low Operating Power – 27 mA Operating Current – 53 µA Standby Current
  • Extended Temperature Range Flash
  • 2.7V to 3.3V Read/Write
  • Access Time – 70 ns
  • Sector Erase Architecture – Thirty-one 32K Word (64K Byte) Sectors with Individual Write Lockout – Eight 4K Word (8K Byte) Sectors with Individual Write Lockout
  • Fast Word Program Time – 12 µs
  • Suspend/Resume Feature for Erase and Program – Supports Reading and Programming from Any Sector by Suspending Erase of a Different Sector – Supports Reading Any Word by Suspending Programming of Any Other Word
  • Low-power Operation – 12 mA Active – 13 µA Standby
  • Data Polling, Toggle Bit, Ready/Busy for End of Program Detection
  • VPP Pin for Write Protection and Accelerated Program/Erase Operations
  • RESET Input for Device Initialization
  • Sector Lockdown Support
  • Top/Bottom Boot Block Configuration
  • 128-bit Protection Register
  • Minimum 100,000 Erase Cycles PSRAM
  • 8-Mbit (512K x 16)
  • 2.7V to 3.3V VCC Operating Voltage
  • 70 ns Access Time
  • Fully Static Operation and Tri-state Output
  • ISB0 < 10 µA when Deep Power-Down Device Number Flash Configuration PSRAM Configuration AT52BC1661A(T) 16M (1M x 16) 8M (512K x 16) 16-Mbit Flash + 8-Mbit PSRAM Stack Memory AT52BC1661A AT52BC1661AT Preliminary Rev. 3455A–STKD–11/04

AT52BC1661A(T) [Preliminary] 3455A–STKD–11/04 CBGA Top View Pin Configurations A14 I/O11 A B C D E F G H A15 A10 A19 POE A13 I/O15 I/O13 I/O12 I/O9 CE A12 PWE I/O6 ZZ I/O10 I/O8 GND GND I/O14 I/O4 PVCC I/O2 I/O0 OE NC I/O7 I/O5 VCC I/O3 I/O1 PCS1 NC NC A16 WE PGND NC PLB A18 NC A11 RDY BUSY RESET VPP PUB A17 NC NC NC NC NC NC NC NC Pin Name Function A0 - A18, A19 Common Address Input for 8M PSRAM/Flash, Flash Address Input CE Flash Chip Enable OE/POE Flash/PSRAM, Output Enable WE/PWE Flash/PSRAM, Write Enable VCC Flash Power Supply VPP Optional Flash Power Supply for Faster Program/Erase Operations I/O0-I/O15 Data Inputs/Outputs PCS1 PSRAM Chip Select RDY/BUSY Flash Ready/Busy Output PVCC PSRAM Power Supply GND/PGND Flash/PSRAM GND PUB PSRAM Upper Byte PLB PSRAM Lower Byte NC No Connect RESET Flash Reset ZZ Low-Power Modes

AT52BC1661A(T) [Preliminary] 3455A–STKD–11/04

Description

The AT52BC1661A(T) combines a single 16-Mbit Flash and a 8-Mbit PSRAM: both of the devices are offered in a stacked 66-ball CBGA package. The devices operate at 2.7V to 3.3V in the extended temperature range. Block Diagram Absolute Maximum Ratings *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. All Input Voltages except VPP (including NC Pins) Voltage on VPP All Output Voltages FLASH PSRAM ADDRESS DATA RESET CE RDY/BUSY PCS1 ZZ PUB PLB WE OE PWE POE DC and AC Operating Range AT52BC1661A(T)-70 Operating Temperature (Case) Extended -25°C to 85°C VCC Power Supply 2.7V to 3.3V

AT52BC1661A(T) [Preliminary] 3455A–STKD–11/04 16-Mbit Flash Memory Block Diagram IDENTIFIER REGISTER STATUS REGISTER DATA COMPARATOR OUTPUT MULTIPLEXER OUTPUT BUFFER INPUT BUFFER COMMAND REGISTER DATA REGISTER Y-GATING WRITE STATE MACHINE PROGRAM/ERASE VOLTAGE SWITCH CE WE OE RESET RDY/BUSY VPP VCC GND Y-DECODER X-DECODER INPUT BUFFER ADDRESS LATCH I/O0 - I/O15 A0 - A19 MAIN MEMORY

AT52BC1661A(T) [Preliminary] 3455A–STKD–11/04 16-Mbit Flash The 16-Mbit Flash is organized as 1,048,576 words of 16 bits each. The x16 data appears on I/O0 - I/O15. The memory is divided into 39 sectors for erase operations. The device has CE and OE control signals to avoid any bus contention. This device can be read or reprogrammed using a single power supply, making it ideally suited for in-system programming. The device powers on in the read mode. Command sequences are used to place the device in other operation modes such as program and erase. The device has the capability to protect the data in any sector (see “Sector Lockdown” section). To increase the flexibility of the device, it contains an Erase Suspend and Program Suspend feature. This feature will put the erase or program on hold for any amount of time and let the user read data from or program data to any of the remaining sectors within the memory. The end of a program or an erase cycle is detected by the READY/BUSY pin, Data Polling or by the toggle bit. The VPP pin provides data protection. When the VPP input is below 0.4V, the program and erase functions are inhibited. When VPP is at 0.9V or above, normal program and erase opera- tions can be performed. A six-byte command (Enter Single Pulse Program Mode) sequence to remove the requirement of entering the three-byte program sequence is offered to further improve programming time. After entering the six-byte code, only single pulses on the write control lines are required for writing into the device. This mode (Single Pulse Word Program) is exited by powering down the device, or by pulsing the RESET pin low for a minimum of 500 ns and then bringing it back to VCC. Erase, Erase Suspend/Resume and Program Suspend/Resume commands will not work while in this mode; if entered they will result in data being programmed into the device. It is not recommended that the six-byte code reside in the software of the final product but only exist in external programming code. Device Operation READ: The Flash is accessed like an EPROM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins are asserted on the out- puts. The outputs are put in the high impedance state whenever CE or OE is high. This dual- line control gives designers flexibility in preventing bus contention. COMMAND SEQUENCES: When the device is first powered on, it will be reset to the read or standby mode, depending upon the state of the control line inputs. In order to perform other device functions, a series of command sequences are entered into the device. The command sequences are shown in the “Command Definition in Hex” table on page 13 (I/O8 - I/O15 are don’t care inputs for the command codes). The command sequences are written by applying a low pulse on the WE or CE input with CE or WE low (respectively) and OE high. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Standard microprocessor write timings are used. The address locations used in the command sequences are not affected by entering the command sequences. RESET: A RESET input pin is provided to ease some system applications. When RESET is at a logic high level, the device is in its standard operating mode. A low level on the RESET input halts the present device operation and puts the outputs of the device in a high impedance state. When a high level is reasserted on the RESET pin, the device returns to the read or standby mode, depending upon the state of the control inputs.

AT52BC1661A(T) [Preliminary] 3455A–STKD–11/04 ERASURE: Before a word can be reprogrammed, it must be erased. The erased state of memory bits is a logical “1”. The entire device can be erased by using the Chip Erase com- mand or individual sectors can be erased by using the Sector Erase command. CHIP ERASE: The entire device can be erased at one time by using the six-byte chip erase software code. After the chip erase has been initiated, the device will internally time the erase operation so that no external clocks are required. The maximum time to erase the chip is tEC. If the sector lockdown has been enabled, the chip erase will not erase the data in the sector that has been locked out; it will erase only the unprotected sectors. After the chip erase, the device will return to the read or standby mode. SECTOR ERASE: As an alternative to a full chip erase, the device is organized into 39 sec- tors (SA0 - SA38) that can be individually erased. The Sector Erase command is a six-bus cycle operation. The sector address is latched on the falling WE edge of the sixth cycle while the 30H data input command is latched on the rising edge of WE. The sector erase starts after the rising edge of WE of the sixth cycle. The erase operation is internally controlled; it will automatically time to completion. The maximum time to erase a sector is tSEC. When the sec- tor programming lockdown feature is not enabled, the sector will erase (from the same Sector Erase command). An attempt to erase a sector that has been protected will result in the oper- ation terminating immediately. WORD PROGRAMMING: Once a memory block is erased, it is programmed (to a logical “0”) on a word-by-word basis. Programming is accomplished via the internal device command reg- ister and is a four-bus cycle operation. The device will automatically generate the required internal program pulses. Any commands written to the chip during the embedded programming cycle will be ignored. If a hardware reset happens during programming, the data at the location being programmed will be corrupted. Please note that a data “0” cannot be programmed back to a “1”; only erase operations can convert “0”s to “1”s. Programming is completed after the specified tBP cycle time. The Data Polling feature or the Toggle Bit feature may be used to indicate the end of a program cycle. If the erase/program status bit is a “1”, the device was not able to verify that the erase or program operation was performed successfully. VPP PIN: The circuitry of the device is designed so that it cannot be programmed or erased if the VPP voltage is less that 0.4V. When VPP is at 0.9V or above, normal program and erase operations can be performed. The VPP pin cannot be left floating. PROGRAM/ERASE STATUS: The device provides several bits to determine the status of a program or erase operation: I/O2, I/O3, I/O5, I/O6 and I/O7. The “Status Bit Table” on page 12 and the following four sections describe the function of these bits. To provide greater flexibility for system designers, the Flash contains a programmable configuration register. The configu- ration register allows the user to specify the status bit operation. The configuration register can be set to one of two different values, “00” or “01”. If the configuration register is set to “00”, the part will automatically return to the read mode after a successful program or erase operation. If the configuration register is set to a “01”, a Product ID Exit command must be given after a successful program or erase operation before the part will return to the read mode. It is impor- tant to note that whether the configuration register is set to a “00” or to a “01”, any unsuccessful program or erase operation requires using the Product ID Exit command to return the device to read mode. The default value (after power-up) for the configuration regis- ter is “00”. Using the four-bus cycle Set Configuration Register command as shown in the “Command Definition in Hex” table on page 13, the value of the configuration register can be changed. Voltages applied to the RESET pin will not alter the value of the configuration regis- ter. The value of the configuration register will affect the operation of the I/O7 status bit as described below.

AT52BC1661A(T) [Preliminary] 3455A–STKD–11/04 DATA POLLING: The 16-Mbit Flash features Data Polling to indicate the end of a program cycle. If the status configuration register is set to a “00”, during a program cycle an attempted read of the last word loaded will result in the complement of the loaded data on I/O7. Once the program cycle has been completed, true data is valid on all outputs and the next cycle may begin. During a chip or sector erase operation, an attempt to read the device will give a “0” on I/O7. Once the program or erase cycle has completed, true data will be read from the device. Data Polling may begin at any time during the program cycle. Please see “Status Bit Table” on page 12 for more details. If the status bit configuration register is set to a “01”, the I/O7 status bit will be low while the device is actively programming or erasing data. I/O7 will go high when the device has com- pleted a program or erase operation. Once I/O7 has gone high, status information on the other pins can be checked. The Data Polling status bit must be used in conjunction with the erase/program and VPP status bit as shown in the algorithm in Figures 1 and 2 on page 10. TOGGLE BIT: In addition to Data Polling the device provides another method for determining the end of a program or erase cycle. During a program or erase operation, successive attempts to read data from the memory will result in I/O6 toggling between one and zero. Once the program cycle has completed, I/O6 will stop toggling and valid data will be read. Examin- ing the toggle bit may begin at any time during a program cycle. Please see “Status Bit Table” on page 12 for more details. The toggle bit status bit should be used in conjunction with the erase/program and VPP status bit as shown in the algorithm in Figures 3 and 4 on page 11. ERASE/PROGRAM STATUS BIT: The device offers a status bit on I/O5, which indicates whether the program or erase operation has exceeded a specified internal pulse count limit. If the status bit is a “1”, the device is unable to verify that an erase or a word program operation has been successfully performed. If a program (Sector Erase) command is issued to a pro- tected sector, the protected sector will not be programmed (erased). The device will go to a status read mode and the I/O5 status bit will be set high, indicating the program (erase) opera- tion did not complete as requested. Once the erase/program status bit has been set to a “1”, the system must write the Product ID Exit command to return to the read mode. The erase/program status bit is a “0” while the erase or program operation is still in progress. Please see “Status Bit Table” on page 12 for more details. VPP STATUS BIT: The device provides a status bit on I/O3, which provides information regarding the voltage level of the VPP pin. During a program or erase operation, if the voltage on the VPP pin is not high enough to perform the desired operation successfully, the I/O3 sta- tus bit will be a “1”. Once the VPP status bit has been set to a “1”, the system must write the Product ID Exit command to return to the read mode. On the other hand, if the voltage level is high enough to perform a program or erase operation successfully, the VPP status bit will out- put a “0”. Please see “Status Bit Table” on page 12 for more details. SECTOR LOCKDOWN: Each sector has a programming lockdown feature. This feature pre- vents programming of data in the designated sectors once the feature has been enabled. These sectors can contain secure code that is used to bring up the system. Enabling the lock- down feature will allow the boot code to stay in the device while data in the rest of the device is updated. This feature does not have to be activated; any sector’s usage as a write-protected region is optional to the user.

AT52BC1661A(T) [Preliminary] 3455A–STKD–11/04 At power-up or reset, all sectors are unlocked. To activate the lockdown for a specific sector, the six-bus cycle Sector Lockdown command must be issued. Once a sector has been locked down, the contents of the sector is read-only and cannot be erased or programmed. SECTOR LOCKDOWN DETECTION: A software method is available to determine if program- ming of a sector is locked down. When the device is in the software product identification mode (see “Software Product Identification Entry/Exit” sections on page 23), a read from address location 00002H within a sector will show if programming the sector is locked down. If the data on I/O0 is low, the sector can be programmed; if the data on I/O0 is high, the program lockdown feature has been enabled and the sector cannot be programmed. The software product identification exit code should be used to return to standard operation. SECTOR LOCKDOWN OVERRIDE: The only way to unlock a sector that is locked down is through reset or power-up cycles. After power-up or reset, the content of a sector that is locked down can be erased and reprogrammed. ERASE SUSPEND/ERASE RESUME: The Erase Suspend command allows the system to interrupt a sector or chip erase operation and then program or read data from a different sector within the memory. After the Erase Suspend command is given, the device requires a maxi- mum time of 15 µs to suspend the erase operation. After the erase operation has been suspended, the system can then read data or program data to any other sector within the device. An address is not required during the Erase Suspend command. During a sector erase suspend, another sector cannot be erased. To resume the sector erase operation, the system must write the Erase Resume command. The Erase Resume command is a one-bus cycle command. The device also supports an erase suspend during a complete chip erase. While the chip erase is suspended, the user can read from any sector within the memory that is pro- tected. The command sequence for a chip erase suspend and a sector erase suspend are the same. PROGRAM SUSPEND/PROGRAM RESUME: The Program Suspend command allows the system to interrupt a programming operation and then read data from a different word within the memory. After the Program Suspend command is given, the device requires a maximum of 20 µs to suspend the programming operation. After the programming operation has been suspended, the system can then read data from any other word that is not contained in the sector in which the programming operation was suspended. An address is not required during the program suspend operation. To resume the programming operation, the system must write the Program Resume command. The program suspend and resume are one-bus cycle com- mands. The command sequence for the erase suspend and program suspend are the same, and the command sequence for the erase resume and program resume are the same. PRODUCT IDENTIFICATION: The product identification mode identifies the device and man- ufacturer as Atmel. It may be accessed by hardware or software operation. The hardware operation mode can be used by an external programmer to identify the correct programming algorithm for the Atmel product. For details, see “Operating Modes” on page 16 (for hardware operation) or “Software Product Identification Entry/Exit” sections on page 23. The manufacturer and device codes are the same for both modes. 128-BIT PROTECTION REGISTER: The device contains a 128-bit register that can be used for security purposes in system design. The protection register is divided into two 64-bit blocks. The two blocks are designated as block A and block B. The data in block A is non-changeable and is programmed at the factory with a unique number. The data in block B is programmed by the user and can be locked out such that data in the block cannot be repro- grammed. To program block B in the protection register, the four-bus cycle Program Protection Register command must be used as shown in the “Command Definition in Hex” table on page 13. To lock out block B, the four-bus cycle Lock Protection Register command

AT52BC1661A(T) [Preliminary] 3455A–STKD–11/04 must be used as shown in the “Command Definition in Hex” table. Data bit D1 must be zero during the fourth bus cycle. All other data bits during the fourth bus cycle are don’t cares. To determine whether block B is locked out, the Product ID Entry command is given followed by a read operation from address 80H. If data bit D1 is zero, block B is locked. If data bit D1 is one, block B can be reprogrammed. Please see the “Flash Protection Register Addressing Table” on page 13 for the address locations in the protection register. To read the protection register, the Product ID Entry command is given followed by a normal read operation from an address within the protection register. After determining whether block B is protected or not, or reading the protection register, the Product ID Exit command must be given prior to performing any other operation. RDY/BUSY: For the 16-Mbit Flash, an open-drain READY/BUSY output pin provides another method of detecting the end of a program or erase operation. RDY/BUSY is actively pulled low during the internal program and erase cycles and is released at the completion of the cycle. The open-drain connection allows for OR-tying of several devices to the same RDY/BUSY line. Please see “Status Bit Table” on page 12 for more details. HARDWARE DATA PROTECTION: The Hardware Data Protection feature protects against inadvertent programs to the device in the following ways: (a) VCC sense: if VCC is below 1.8V (typical), the program function is inhibited. (b) VCC power-on delay: once VCC has reached the VCC sense level, the device will automatically time out 10 ms (typical) before programming. (c) Program inhibit: holding any one of OE low, CE high or WE high inhibits program cycles. (d) Program inhibit: VPP is less than VILPP. (e) VPP power-on delay: once VPP has reached 1.65V, program and erase operations are inhibited for 100 ns. INPUT LEVELS: While operating with a 2.7V to 3.3V power supply, the address inputs and control inputs (OE, CE and WE) may be driven from 0 to 5.5V without adversely affecting the operation of the device. The I/O lines can only be driven from 0 to VCC + 0.3V.

AT52BC1661A(T) [Preliminary] 3455A–STKD–11/04 Notes: 1. I/O5 switches to a “1” when a program or an erase operation has exceeded the maximum time limits or when a program or sector erase operation is performed on a protected sector. 2. I/O3 switches to a “1” when the VPP level is not high enough to successfully perform program and erase operations. Status Bit Table Status Bit I/O7 I/O7 I/O6 I/O5(1) I/O3(2) I/O2 RDY/BUSY Configuration Register Programming I/O7 TOGGLE Erasing TOGGLE TOGGLE Erase Suspended & Read Erasing Sector TOGGLE Erase Suspended & Read Non-erasing Sector DATA DATA DATA DATA DATA DATA Erase Suspended & Program Non-erasing Sector I/O7 TOGGLE TOGGLE Erase Suspended & Program Suspended and Reading from Non- suspended Sectors DATA DATA DATA DATA DATA DATA Program Suspended & Read Programming Sector I/O7 TOGGLE Program Suspended & Read Non-programming Sector DATA DATA DATA DATA DATA DATA

AT52BC1661A(T) [Preliminary] 3455A–STKD–11/04 Notes: The DATA FORMAT shown for each bus cycle is as follows; I/O7 - I/O0 (Hex). I/O15 - I/O8 are don’t care. The ADDRESS FORMAT shown for each bus cycle is as follows: A11 - A0 (Hex). Address A19 through A11 are don’t care. Since A11 is a Don’t Care, AAA can be replaced with 2AA. SA = sector address. Any word address within a sector can be used to designate the sector address (see pages 14 - 16 for details). Once a sector is in the lockdown mode, data in the protected sector cannot be changed unless the chip is reset or power cycled. Either one of the Product ID Exit commands can be used. If data bit D1 is “0”, block B is locked. If data bit D1 is “1”, block B can be reprogrammed. The default state (after power-up) of the configuration register is “00”. Bytes of data other than F0 may be used to exit the Product ID mode. However, it is recommended that F0 be used. This fast programming option enables the user to program two words in parallel only when VPP = 12V. The Addresses, Addr1 and Addr2, of the two words, DIN1 and DIN2, must only differ in address A0. This command should be used during manufacturing purposes only. Note: All address lines not specified in the above table must be “0” when accessing the protection register, i.e., A19 - A8 = 0. Command Definition in Hex(1) Command Sequence Bus Cycles 1st Bus Cycle 2nd Bus Cycle 3rd Bus Cycle 4th Bus Cycle 5th Bus Cycle 6th Bus Cycle Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Read Addr DOUT Chip Erase 555 AA AAA(2) 555 555 AA AAA 555 Sector Erase 555 AA AAA 555 555 AA AAA SA(3)(4) Word Program 555 AA AAA 555 Addr DIN Dual Word Program(9) 555 AA AAA 555 Addr1 DIN1 Addr2 DIN2 Enter Single Pulse Program Mode 555 AA AAA 555 555 AA AAA 555 Single Pulse Word Program Addr DIN Sector Lockdown 555 AA AAA(2) 555 555 AA AAA SA(3)(4) Erase/Program Suspend XXX Erase/Program Resume XXX Product ID Entry 555 AA AAA 555 Product ID Exit(5) 555 AA AAA 555 F0(8) Product ID Exit(5) XXX F0(8) Program Protection Register 555 AA AAA 555 Addr DIN Lock Protection Register - Block B 555 AA AAA 555 080 Status of Block B Protection 555 AA AAA 555 DOUT (6) Set Configuration Register 555 AA AAA 555 XXX 00/01(7) CFI Query X55 Flash Protection Register Addressing Table Word Use Block Factory A Factory A Factory A Factory A User B User B User B User B

AT52BC1661A(T) [Preliminary] 3455A–STKD–11/04 Bottom Boot– Sector Address Table Sector Size (Words) x16 Address Range (A19 - A0) SA0 00000 - 00FFF SA1 01000 - 01FFF SA2 02000 - 02FFF SA3 03000 - 03FFF SA4 04000 - 04FFF SA5 05000 - 05FFF SA6 06000 - 06FFF SA7 07000 - 07FFF SA8 32K 08000 - 0FFFF SA9 32K 10000 - 17FFF SA10 32K 18000 - 1FFFF SA11 32K 20000 - 27FFF SA12 32K 28000 - 2FFFF SA13 32K 30000 - 37FFF SA14 32K 38000 - 3FFFF SA15 32K 40000 - 47FFF SA16 32K 48000 - 4FFFF SA17 32K 50000 - 57FFF SA18 32K 58000 - 5FFFF SA19 32K 60000 - 67FFF SA20 32K 68000 - 6FFFF SA21 32K 70000 - 77FFF SA22 32K 78000 - 7FFFF SA23 32K 80000 - 87FFF SA24 32K 88000 - 8FFFF SA25 32K 90000 - 97FFF SA26 32K 98000 - 9FFFF SA27 32K A0000 - A7FFF SA28 32K A8000 - AFFFF SA29 32K B0000 - B7FFF SA30 32K B8000 - BFFFF SA31 32K C0000 - C7FFF SA32 32K C8000 - CFFFF SA33 32K D0000 - D7FFF SA34 32K D8000 - DFFFF SA35 32K E0000 - E7FFF SA36 32K E8000 - EFFFF SA37 32K F0000 - F7FFF SA38 32K F8000 - FFFFF

AT52BC1661A(T) [Preliminary] 3455A–STKD–11/04 Top Boot– Sector Address Table Sector Size (Words) x16 Address Range (A19 - A0) SA0 32K 00000 - 07FFF SA1 32K 08000 - 0FFFF SA2 32K 10000 - 17FFF SA3 32K 18000 - 1FFFF SA4 32K 20000 - 27FFF SA5 32K 28000 - 2FFFF SA6 32K 30000 - 37FFF SA7 32K 38000 - 3FFFF SA8 32K 40000 - 47FFF SA9 32K 48000 - 4FFFF SA10 32K 50000 - 57FFF SA11 32K 58000 - 5FFFF SA12 32K 60000 - 67FFF SA13 32K 68000 - 6FFFF SA14 32K 70000 - 77FFF SA15 32K 78000 - 7FFFF SA16 32K 80000 - 87FFF SA17 32K 88000 - 8FFFF SA18 32K 90000 - 97FFF SA19 32K 98000 - 9FFFF SA20 32K A0000 - A7FFF SA21 32K A8000 - AFFFF SA22 32K B0000 - B7FFF SA23 32K B8000 - BFFFF SA24 32K C0000 - C7FFF SA25 32K C8000 - CFFFF SA26 32K D0000 - D7FFF SA27 32K D8000 - DFFFF SA28 32K E0000 - E7FFF SA29 32K E8000 - EFFFF SA30 32K F0000 - F7FFF SA31 F8000 - F8FFF SA32 F9000 - F9FFF SA33 FA000 - FAFFF SA34 FB000 - FBFFF SA35 FC000 - FCFFF SA36 FD000 - FDFFF SA37 FE000 - FEFFF SA38 FF000 - FFFFF

AT52BC1661A(T) [Preliminary] 3455A–STKD–11/04 Notes: 1. X can be VIL or VIH. 2. Refer to AC programming waveforms on page 21. 4. Manufacturer Code: 001FH, Device Code: 00C0H – Bottom Boot, 00C2H, Top Boot. 5. See details under “Software Product Identification Entry/Exit” on page 23. 6. VIHPP (min) = 0.9V; VIHPP (max) = 3.6V. 7. VILPP (max) = 0.4V. DC and AC Operating Range 16-Mbit Flash-70 Operating Temperature (Case) Extended -25°C to 85°C VCC Power Supply 2.70V to 3.3V Operating Modes Mode CE OE WE RESET VPP Ai I/O Read VIL VIL VIH VIH X Ai DOUT Program/Erase(2) VIL VIH VIL VIH VIHPP (6) Ai DIN Standby/Program Inhibit VIH X(1) X VIH X X High-Z Program Inhibit X X VIH VIH X X VIL X VIH X X X X VIH VILPP (7) Output Disable X VIH X VIH X High-Z Reset X X X VIL X X High-Z Product Identification Hardware VIL VIL VIH VIH A1 - A19 = VIL, A9 = VH (3), A0 = VIL Manufacturer Code(4) A1 - A19 = VIL, A9 = VH (3), A0 = VIH Device Code(4) Software(5) VIH A0 = VIL, A1 - A19 = VIL Manufacturer Code(4) A0 = VIH, A1 - A19 = VIL Device Code(4)

AT52BC1661A(T) [Preliminary] 3455A–STKD–11/04 Note: 1. In the erase mode, ICC is 45 mA. DC Characteristics Symbol Parameter Condition Min Typ Max Units ILI Input Load Current VIN = 0V to VCC µA ILO Output Leakage Current VI/O = 0V to VCC µA ISB VCC Standby Current CMOS CE = VCC - 0.3V to VCC µA ICC (1) VCC Active Read Current f = 5 MHz; IOUT = 0 mA mA ICC1 VCC Programming Current mA IPP1 VPP Input Load Current µA VIL Input Low Voltage 0.6 V VIH Input High Voltage 2.0 V VOL1 Output Low Voltage IOL = 2.1 mA 0.45 V VOL2 Output Low Voltage IOL = 1.0 mA 0.20 V VOH1 Output High Voltage IOH = -400 µA 2.4 V VOH2 Output High Voltage IOH = -100 µA 2.5 V

AT52BC1661A(T) [Preliminary] 3455A–STKD–11/04 AC Read Waveforms(1)(2)(3)(4) Notes: 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC. 2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change without impact on tACC. 3. tDF is specified from OE or CE, whichever occurs first (CL = 5 pF). 4. This parameter is characterized and is not 100% tested. AC Read Characteristics Symbol Parameter 16-Mbit Flash-70 Units Min Max tRC Read Cycle Time ns tACC Address to Output Delay ns tCE (1) CE to Output Delay ns tOE (2) OE to Output Delay ns tDF (3)(4) CE or OE to Output Float ns tOH Output Hold from OE, CE or Address, whichever Occurred First ns tRO RESET to Output Delay 100 ns OUTPUT VALID OUTPUT HIGH Z RESET OE tOE tCE ADDRESS VALID tDF tOH tACC tRO CE ADDRESS tRC

AT52BC1661A(T) [Preliminary] 3455A–STKD–11/04 Input Test Waveforms and Measurement Level tR, tF < 5 ns Output Test Load Note: This parameter is characterized and is not 100% tested. CL (1)

1029 Ohm

1728 Ohm

2.8V = VTM Pin Capacitance f = 1 MHz, T = 25°C(1) Symbol Typ Max Units Conditions CIN pF VIN = 0V COUT pF VOUT = 0V

AT52BC1661A(T) [Preliminary] 3455A–STKD–11/04 AC Word Load Waveforms WE Controlled CE Controlled AC Word Load Characteristics Symbol Parameter Min Max Units tAS, tOES Address, OE Setup Time ns tAH Address Hold Time ns tCS Chip Select Setup Time ns tCH Chip Select Hold Time ns tWP Write Pulse Width (WE or CE) ns tDS Data Setup Time ns tDH, tOEH Data, OE Hold Time ns tWPH Write Pulse Width High ns

AT52BC1661A(T) [Preliminary] 3455A–STKD–11/04 Program Cycle Waveforms Sector or Chip Erase Cycle Waveforms Notes: 1. OE must be high only when WE and CE are both low. 2. For chip erase, the address should be 555. For sector erase, the address depends on what sector is to be erased. (See note 3 under “Command Definitions in Hex” on page 13.) 3. For chip erase, the data should be 10H, and for sector erase, the data should be 30H. Program Cycle Characteristics Symbol Parameter Min Typ Max Units tBP Word Programming Time 200 µs tBPD Word Programming Time in Dual Programming Mode 100 µs tAS Address Setup Time ns tAH Address Hold Time ns tDS Data Setup Time ns tDH Data Hold Time ns tWP Write Pulse Width ns tWPH Write Pulse Width High ns tWC Write Cycle Time ns tRP Reset Pulse Width 500 ns tEC Chip Erase Cycle Time seconds tSEC1 Sector Erase Cycle Time (4K Word Sectors) 3.0 seconds tSEC2 Sector Erase Cycle Time (32K Word Sectors) 5.0 seconds tES Erase Suspend Time µs tPS Program Suspend Time µs OE PROGRAM CYCLE INPUT DATA ADDRESS 555 555 AA AAA tBP tWPH tWP CE WE A0 - A19 DATA tAS tAH tDH tDS 555 AA tWC OE (1) AA Note 3 555 555 Note 2 AA WORD 0 WORD 1 WORD 2 WORD 3 WORD 4 WORD 5 AAA AAA tWPH tWP CE WE A0-A19 DATA tAS tAH tEC tDH tDS 555 tWC

AT52BC1661A(T) [Preliminary] 3455A–STKD–11/04 Notes: 1. These parameters are characterized and not 100% tested. 2. See tOE spec in “AC Read Characteristics” on page 18. Data Polling Waveforms Notes: 1. These parameters are characterized and not 100% tested. 2. See tOE spec in “AC Read Characteristics” on page 18. Toggle Bit Waveforms(1)(2)(3) Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit. The tOEHP specification must be met by the toggling input(s). 2. Beginning and ending state of I/O6 will vary. 3. Any address location may be used but the address should not vary. Data Polling Characteristics(1) Symbol Parameter Min Typ Max Units tDH Data Hold Time ns tOEH OE Hold Time ns tOE OE to Output Delay(2) ns tWR Write Recovery Time ns A0-A19 WE CE OE I/O7 tDH tOEH tOE HIGH Z An An An An An tWR Toggle Bit Characteristics(1) Symbol Parameter Min Typ Max Units tDH Data Hold Time ns tOEH OE Hold Time ns tOE OE to Output Delay(2) ns tOEHP OE High Pulse ns tWR Write Recovery Time ns

AT52BC1661A(T) [Preliminary] 3455A–STKD–11/04 Software Product Identification Entry(1) Software Product Identification Exit(1)(6) Notes: Data Format: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex) Address Format: A11 - A0 (Hex), and A11 - A19 (Don’t Care). A1 - A19 = VIL. Manufacturer Code is read for A0 = VIL; Device Code is read for A0 = VIH. The device does not remain in identification mode if powered down. The device returns to standard operation mode. Manufacturer Code: 001FH(x16) Device Code: 00C0H (x16) - Bottom Boot; 00C2H (x16) - Top Boot. Either one of the Product ID Exit commands can be used. LOAD DATA AA TO ADDRESS 555 LOAD DATA 55 TO ADDRESS AAA LOAD DATA 90 TO ADDRESS 555 ENTER PRODUCT IDENTIFICATION MODE(2)(3)(5) LOAD DATA AA TO ADDRESS 555 LOAD DATA 55 TO ADDRESS AAA LOAD DATA F0 TO ADDRESS 555 EXIT PRODUCT IDENTIFICATION MODE(4) OR LOAD DATA F0 TO ANY ADDRESS EXIT PRODUCT IDENTIFICATION MODE(4) Sector Lockdown Enable Algorithm(1) Notes: Data Format: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex) Address Format: A11 - A0 (Hex), and A11 - A19 (Don’t Care). Sector Lockdown feature enabled. LOAD DATA AA TO ADDRESS 555 LOAD DATA 55 TO ADDRESS AAA LOAD DATA 80 TO ADDRESS 555 LOAD DATA AA TO ADDRESS 555 LOAD DATA 55 TO ADDRESS AAA LOAD DATA 60 TO SECTOR ADDRESS PAUSE 200 µs(2)

AT52BC1661A(T) [Preliminary] 3455A–STKD–11/04 PSRAM The Pseudo-SRAM (PSRAM) is an integrated memory based on a self-refresh DRAM array. The device is offered with a density of 8-Mbit organized as 512,288 words by 16 bits. It is designed to be identical in operation and interface to the standard 6T SRAMS. The device is designed for low standby, low operating current and includes a user configurable low-power mode. Two chip selects (PCS1 and ZZ) and an output enable (POE) is available to allow for easy memory expansion. Byte controls (PUB and PLB) allow the upper and lower bytes to be accessed independently and can also be used to deselect the device. The deep sleep mode reduces standby current drain while not retaining data in the array. PSRAM

  • Fast Cycle Times – TACC < 70 ns
  • Very Low Standby Current – ISB0 < 10 µA @ 3.0V
  • Very Low Operating Current – 1.0 mA at 3.0 and 1 µs (Typical)
  • Memory Expansion with PCS1 and POE
  • TTL Compatible Three-state Output Driver Functional Block Diagram Precharge Circuit Clk Gen PVCC PGND Memory Array Row Addresses I/O Circuit Column select Data Cont Data Cont Column Addresses Data Cont Control Logic OE WE UB LB ZZ I/O8 ~ I/O15 I/O0 ~ I/O7 Row Select PCS1 P P P P

AT52BC1661A(T) [Preliminary] 3455A–STKD–11/04 Note: 1. X means don’t care (must be low or high state). Notes: 1. TA = - 25°C to 85°C, otherwise specified. 2. Overshoot and undershoot are sampled, not 100% tested. 3. Overshoot: PVCC + 1.0V in case of pulse width < 20 ns. 4. Undershoot: -1.0V in case of pulse width < 20 ns. Note: 1. Capacitance is sampled, not 100% tested. Functional Description PCS1 ZZ POE PWE PLB PUB I/O0 - 7 I/O8 - 15 Mode Power H H X(1) X(1) X(1) X(1) High-Z High-Z Deselected Standby X(1) L X(1) X(1) X(1) X(1) High-Z High-Z Deselected Low-power Modes X(1) H X(1) X(1) H H High-Z High-Z Deselected Standby L H H H L X(1) High-Z High-Z Output Disabled Active H H H X(1) L High-Z High-Z Output Disabled Active L H L H L H DOUT High-Z Lower Byte Read Active H L High-Z DOUT Upper Byte Read Active L L DOUT DOUT Word Read Active X(1) L L H DIN High-Z Lower Byte Write Active H L High-Z DIN Upper Byte Write Active L L DIN DIN Word Write Active Recommended DC Operating Conditions(1)(2) Item Symbol Min Max Unit Supply Voltage PVCC 2.7 3.3 V Ground PGND V Input High Voltage VIH

0.8 PVCC

PVCC + 0.2(3) V Input Low Voltage VIL -0.2(4)

0.2 PVCC

V Capacitance(1) (f = 1 MHz, TA = 25°C) Item Symbol Test Condition Min Max Unit Input Capacitance CIN VIN = 0V pF I/O Capacitance CI/O VIN = 0V pF

AT52BC1661A(T) [Preliminary] 3455A–STKD–11/04 DC and Operating Characteristics Item Symbol Test Conditions Min Typ Max Unit Input Leakage Current ILI VIN = PGND to PVCC µA Output Leakage Current ILO PCS1 = VIH, ZZ = VIH, POE = VIH or PWE = VIL, VI/O = PGND to PVCC µA Average Operating Current ICC1 Cycle time = 1 µs, 100% duty, I I/O = 0 mA, PCS1 < 0.2V, ZZ = VIH, VIN < 0.2V or VIN > PVCC - 0.2V mA ICC2 Cycle time = Min, II/O = 0 mA, 100% duty, PCS1 = VIL, ZZ = VIH, VIN = VIL or VIH mA Output Low Voltage VOL IOL = 0.5 mA 0.2 PVCC V Output High Voltage VOH IOH = -0.5 mA 0.8 PVCC V Standby Current (TTL) ISB PCS1 = VIH, ZZ = VIH, other inputs = VIH or VIL 0.3 mA Standby Current (CMOS) ISB1 PCS1 > PVCC -0.2V, ZZ > PVCC - 0.2V, other inputs = 0 ~ PVCC µA Low Power Modes ISB0 ZZ < 0.2V, other inputs = 0 ~ PVCC, no refresh (DPD) µA

AT52BC1661A(T) [Preliminary] 3455A–STKD–11/04 AC Characteristics (PVCC = 2.7V – 3.3V, TA = -25°C to 85°C) Parameter List Symbol Speed Bins Unit 70 ns Min Max Read Read Cycle Time tRC 40K ns Address Access Time tAA ns Chip Select to Output tCO ns Output Enable to Valid Output tOE ns PUB, PLB Access Time tBA ns Chip Select to Low-Z Output tLZ ns PUB, PLB Enable to Low-Z Output tBLZ ns Output Enable to Low-Z Output tOLZ ns Chip Disable to High-Z Output tHZ ns PUB, PLB Disable to High-Z Output tBHZ ns Output Disable to High-Z Output tOHZ ns Output Hold from Address Change tOH ns Write Write Cycle Time tWC 40K ns Chip Select to End of Write tCW ns Address Set-up Time tAS ns Address Valid to End of Write tAW ns PUB, PLB Valid to End of Write tBW ns Write Pulse Width tWP ns Write Recovery Time tWR ns Write to Output High-Z tWHZ ns Data to Write Time Overlap tDW ns Data Hold from Write Time tDH ns End Write to Output Low-Z tOW ns PCS1 High Pulse Width tCP ns

AT52BC1661A(T) [Preliminary] 3455A–STKD–11/04 Power Up Sequence Apply Power. Maintain stable power for a minimum of 200 µs with PCS1 = VIH Standby Mode State Machines Standby Mode Characteristics Mode Memory Cell Data Standby Current (µA) Wait Time (µs) Standby Valid 70 (ISB1) Low Power Modes Invalid 10 (ISB0) 200 Initial State Standby Mode Active Mode Power On PCS1 = VIH (or/and PUB = PLB = VIH) ZZ = VIH PCS1 = VIH PCS1 = VIL, ZZ = VIH PUB or/and PLB = VIL Low Power (Data Invalid) Wait 200 µs PCS1 = VIH, ZZ = VIL PCS1 = VIH, ZZ = VIH ZZ = VIH PCS1 = VIH, ZZ = VIL PCS1 = VlL

AT52BC1661A(T) [Preliminary] 3455A–STKD–11/04 Read Cycle (1) (Address Controlled, PCS1 = POE = VIL, ZZ = PWE = VIH, PUB or/and PLB = VIL) Read Cycle (2) (ZZ = PWE = VIH) Notes: 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ (max) is less than tLZ (min) both for a given device and from device to device interconnection. 3. Do not access device with cycle timing shorter than tRC (tWC) for continuous periods > 40 µs. Address Data Out Previous Data Valid Data Valid A H Address A A E H LZ Z Data Valid High-Z HZ PCS1 PUB, PLB POE Data Out

AT52BC1661A(T) [Preliminary] 3455A–STKD–11/04 Write Cycle (1) (PWE Controlled, ZZ = VIH) Write Cycle (2) (PCS1 Controlled, ZZ = VIH) Write Cycle (3) (PUB, PLB Controlled, ZZ = VIH) Notes: 1. A write occurs during the overlap (tWP) of low PCS1 and PWE. A write begins when PCS1 goes low and PWE goes low with asserting PUB or PLB for single byte operation or simultaneously asserting PUB and PLB for double byte operation. A write ends at the earliest transition when PCS1 goes high and PWE goes high. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the PCS1 going low to end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as PCS1 or PWE going high. 5. Do not access device with cycle timing shorter than tRC (tWC) for continuous periods > 40 µs. Address PCS1 PUB, PLB PWE Data Out C W R W W P S High-Z High-Z Data Undefined Data Valid W W HZ Data In (2) (1) (4) Address PCS1 PUB, PLB PWE Data Out C R W P High-Z High-Z Data Valid W Dat a In W S W (2) (1) (4) Address PCS1 PUB, PLB PWE Data Out C R W P High-Z High-Z Data Valid W Data In W W S (2) (1) (4)

AT52BC1661A(T) [Preliminary] 3455A–STKD–11/04 Deep Power-down Mode Entry/Exit tZZmin PCS1 PUB, PLB PWE C R W P ZZ ZWE Register Write (DPD) Deep Power Down Start Deep Power Down Exit Next Cycle (2) (1) (4) Parameter ZZ low to Write Enable Low µs tR (Deep Power-down Mode Only) Operation Recovery Time 200 µs tZZmin Low Power Mode Time µs

AT52BC1661A(T) [Preliminary] 3455A–STKD–11/04

Ordering Information

tACC (ns) Voltage Range Ordering Code Flash Boot Block PSRAM Size Package Operation Range 2.7V - 3.3V AT52BC1661AT-70CI Top 8-Mbit 66C5 Extended (-25° to 85°C) 2.7V - 3.3V AT52BC1661A-70CI Bottom 8-Mbit 66C5 Extended (-25° to 85°C) Package Type 66C5 66-ball, Plastic Chip-scale Ball Grid Array Package (CBGA)

AT52BC1661A(T) [Preliminary] 3455A–STKD–11/04 Packaging Information 66C5 – CBGA

2325 Orchard Parkway

San Jose, CA 95131 TITLE DRAWING NO. R REV. 66C5, 66-ball (12 x 8 Array), 10 x 8 x 1.2 mm Body, 0.8 mm Ball Pitch Chip-scale Ball Grid Array Package (CBGA) A 66C5 09/19/01 Side View A 0.12 Seating Plane C C Top View Bottom View

0.60 REF

E D A1 Ball Corner Øb Marked A1 Identifier A B C D E F G H

1.20 REF

e e COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE E 9.90 10.00 10.10 8.80 D 7.90 8.00 8.10 5.60 A 1.20 0.25 e

0.80 BSC

Øb 0.40

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