AT48802 ATMEL | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 23
Technical content
Features
- Two Independent PN (Pseudo-Random Noise) Generators
- Programmable R7 (128) to R13 (8,192) PN Sequence Lengths
- Programmable Tau-Dither Amplitude
- Programmable PN Phase Adjustment to 1/16 Chip
- Correlation Acquisition Interface
- Programming Register Control
- Microcontroller Compatible Bus Interface
- Patent-Pending Frequency Diversity
- Low Speed Link Data Path for Supervisory and Setup Functions
Description
The AT48802 Spread-Spectrum Signal Processor (SSSP) chip from Atmel handles all PN code generation, synchronization, and handshaking required for either station (handset or base station) of a time division duplex direct sequence spread-spectrum cordless telephone. The AT48802 supports RF spreading and despreading for the best rejection of interference. In conjunction with a single-chip microcontroller, the circuit performs the following functions:
- Generates a pseudo-random sequence for spreading the transmitted signal.
- Generates a pseudo-random sequence for despreading in the receiver.
- Generates a sliding phase PN for acquiring synchronization with an incoming signal.
- Controls receive signal strength measurement timing for correlation peak detection.
- Operates a tau-dither tracking loop, with adaptive threshold, to maintain synchronization with the incoming signal.
- Controls transmit keying antenna switching for time-division duplexing. (continued) 0624A
64 Lead PQFP
µC * External Components 1000 pF 300K* RC R FLIPSW INTERCOM DC PWR CTRL µC INTERNAL Ckts I/Os Block Diagram
- Controls receive audio or data sampling time and duration.
- Controls wake-up and sleep functionality for remote battery operated handset. The AT48802 unique spread-spectrum architecture capi- talizes on the benefits of long range, signal-to-noise im- provements, multi-path protection, and privacy. This de- sign employs proven analog FM modulation to achieve the lowest possible system cost yet the highest processing gain and sound quality. The chip is a fully static design. Description (Continued) 2-2 AT48802
Name Pin# I/O/T Description AD CE 26 O Chip enable for external A/D converter, true = low. AD DATA 30 I 8 bit serial input for external A/D. AD INTR 29 O Interrupt to controller to read A/D data, true = high. AD SCLK 28 O Clock for A/D converter. ADVANCE 7 I Advance or retard the chip phase. High = advance. AD0 37 I/T General purpose bi-directional port for microcontroller interface. AD1 38 I/T General purpose bi-directional port for microcontroller interface. AD2 39 I/T General purpose bi-directional port for microcontroller interface. AD3 40 I/T General purpose bi-directional port for microcontroller interface. AD4 44 I/T General purpose bi-directional port for microcontroller interface. AD5 45 I/T General purpose bi-directional port for microcontroller interface. AD6 46 I/T General purpose bi-directional port for microcontroller interface. AD7 47 I/T General purpose bi-directional port for microcontroller interface. ALE 36 I Address Latch Enable for port AD. Down edge latches. ATTN DP 8 O Can drive dial pulse relay or other function. AUD T/H 15 O Driver for audio track and hold. BUF CLK 42 O Replica of MCLK high speed clock input, for driving microcontroller clock input. CARRIER 17 O Internal data path, high = carrier present. DC PWR CTRL 48 O Can control a V CC switch to turn on and off the other circuits. DITHER 54 O Indicates whether the tau-dither state is retarded or not retarded. High = retarded. FLIPSW 21 I A programmable transition on this pin will cause the chip to wake-up. GAIN 50 O May be used to control RF receive gain. GND I DC power return = 0 Volts INTERCOM 51 I A programmable transition on this pin will cause the chip to wake-up. MCLK 10 I High speed clock input to chip. ME DIN 23 I Internal data path input from RF module. ME DOUT 20 O Internal data output to RF module. P0.0 2 O General purpose output port. P0.1 3 O General purpose output port. P0.2 4 O General purpose output port. Pin Description (continued) AT48802 2-3
Name Pin# I/O/T Description P0.3 5 O General purpose output port. P0.4 6 O General purpose output port. P0.5 12 O General purpose output port. P0.6 13 O General purpose output port. P0.7 14 O General purpose output port. PA HL 16 O May be used to control a switch which controls the RF transmit power. PN EN 22 T For controlling whether the RF module runs on spread-spectrum or narrowband. R 58 O Low speed clock oscillator for sleep control. RC 31 I Low speed clock oscillator for sleep control. !RD 34 I Read strobe input for port AD, low = true. RINGER 62 O Ring control output. RSSI ID 63 O RSSI integrate/dump control. RX DATA 53 O Internal data path output to microcontroller. RX MUTE 55 O Mute receive audio. SYNC 52 T PN epoch sync for receive, transmit or both. SYS RST 18 I Not a user control. Hold high always. TR SWITCH 19 O Controls state of RF module transmit/receive switch. TX CHOP 60 O Controls switch to disconnect audio from RF module modulation input during receive part of TDD. TX DATA 49 I Internal data path input from microcontroller. TX AUD MUTE 59 O For disconnecting transmit audio when data must be transmitted. TX PWR 56 O Turns on RF module transmit power during transmit part of TDD, and off during receive part of TDD. TX/RX PN 25 T Pseudo-noise sequence to RF module. UPDATE 61 I Causes chip phase control to step the phase. Used in conjunction with ADVANCE pin 7. V CC DC power input = +V CC Volts. !WR 35 I Write strobe for Port AD. Low = true. Pin Description (Continued) 2-4 AT48802
15.360 MHz which is available from the companion RF
Figure 1. Sleep Mode Arrangement be used to shutdown external circuits VCC . power drain is extremely small. if desired, in any one of three ways.
- Time-out from the 4 kHz Oscillator will happen about
- If the INTERCOM input is activated. The edge sense
- If the FLIPSW input is activated. The edge sense is
quences available for R13 PN, and over 300 for R11 PN. sequence by setting feedback tap weights to either 0 or 1. tiplexed precisely by the 50% duty-cycle TX PWR signal. R1 b0-7 for receive, and R4 b0-4 and R3 b0-7 for transmit. SLAVE. This function is set at R0 b6. outline of an acquisition process. with less output filtering and still meet the requirements. CC /2 for 60 ns on every transition. put to the RF module PN input. ing up during the first-time loading after a power up cycle. This is common among multiple feedback PN counters. in the control register (Register 0, bit 1). function at R0 b5 turns on the PN when set. Figure 2. PN Coupling for Spectral Control
Frequency Diversity Improves Signal-to-Noise Ratio Built into the AT48802 is an exclusive frequency diversity function, which enhances protection from PN noise due to imperfect correlation. The chip encodes the PN code se- quence such that when spread, the information is modu- lated and transmitted redundantly in two side lobes. That is, the redundant information is contained in two main lobes with a null at the carrier instead of the classical sin- gle lobe spreading spectra. The spreading bandwidth also doubles, effectively doubling the spreading chip rate. This has the benefit of increased processing gain and greatly reducing the residual PN noise near the carrier after cor- relation. The frequency diversity can be user enabled by setting the BW (Band-Width) bit high in the PN register (Register 2, bit 7 for Receive PN, and Register 4, bit 7 for Transmit PN). The transmit and receive PN generators are set independently. Chip Phase and Tau-Dither Control The chip phase control circuit enables the user to step the chip phase in either direction by amounts from 1/16 to 8/16 chip per update. The size of the step is set in R5 b0-2, the step direction is controlled by the ADVANCE line, and the command to do a step is by pulsing the UPDATE line. The maximum allowed update rate is MCLOCK/32. The tau-dither circuit is used to assist in the tracking a cor- relation peak. This is done as follows. When the locally generated receive PN is a good match to the incoming sig- nal at RF, then the RF signal is accurately despread and the signal energy is gathered into a narrow spectral region around the carrier. If a narrow IF filter is used to filter this signal, then when the chip phase match to the incoming signal is good then the most possible power will get through the narrow IF filter; when the chip phase is ad- vanced or retarded from the best place, then the signal power in a narrow band will fall. The tau-dither circuits, when activated, step the PN chip phase back and forth by a settable amount at a rate of TDD/2. If one looks at the RF module RSSI (receive signal strength indicator) by us- ing the A/D converter interface, then when the PN phase is, on the average, optimum then the alternating output of RSSI will show small variation at a rate of TDD/2. If the peak is not centered, then the RSSI variation at TDD/2 measured through the A/D converter interface, will be- come larger because one phase of tau-dither will produce less RSSI than the other. Now one can track the peak by using the microprocessor to close this control loop which RSSI Interface The purpose of this circuitry is to provide an interface to a serial A/D converter and an integrate/dump filter, if de- sired. The interface is synchronized to TDD. The data from the A/D converter is converted to parallel and loaded to the register at R8 b0-7. The RSSI function provides an in- tegrated/dump command output with timing completely adjustable throughout the TDD cycle and also completely adjustable for pulse width, except the hardware will not al- low the timing of RSSI ID to conflict with the A/D converter command. This allows optimum filtering of the RSSI signal if desired. The adjustable timing is necessary to allow for different RF designs with different amounts of delay in the IF filter. The sense of the RSSI ID output, that is, which way is integrate and which way is dump, is controlled via RC b6-7 RSSI ID timing is set via RC b0-5 for delay and RD b0-5 for pulse width. The smallest step is MCLK/32 = 2 us for a 15.36 MHz clock. The 5 bits allow adjustment over a range of TDD/2. In order to get the other half TDD cycle, one must invert the RSSI ID bits at RC b6-7, which will invert the waveform. Figure 3 shows the A/D converter timing for a converter such as the Linear Technology LTC 1196 National Semi- conductor ADC0831 or similar. has as an input to the RSSI variation at TDD/2 measured through the A/D converter interface and has output using the UPDATE and ADVANCE controls. The control loop should null the TDD/2 signal. The available tau-dither amounts are 1/16 chip peak-to- peak, to 15/16 chip peak-to-peak, set at R5 b3-5. Dither on/off is controlled via R0 b4 (track = high = dither on ). The tau-dither phase is actually only a retard or no retard with respect to the chip phase when tau-dither is off, this is a detail which the control system designer may need. If the tau-dither amplitude is changed it will not take affect until the receive PN code is reloaded. The DITHER output of the chip tells the microprocessor whether the dither phase is retarded (High) or not retarded. High is retarded. AT48802 2-7
Figure 3. A/D Converter Acquisition Timing Diagram 8 data bits before the AD CE goes high again. set always in one state for simplex applications. the RSSI level in best range for chip lock loop function. b5-6 to be either low, high, or three-state high impedance. requirements. This is controlled through R6 b0.
function to be high, low, TDD or inverse TDD. Figure 4. Write Cycle Timing Diagram ate to at least 16 MHz frequency. The bus multiplexes address information as well as data. dress is directly mapped to the low-order address bits.
intended for call setup and control functions. plete the TDE bit should be reset. complete then R6 b5 should be reset. commodate the delays of various RF designs. high state. The timing is shown in Figure 5 below. Figure 5. Read Cycle Timing Diagram
ators start their PN codes, which are called the epochs. for the ASIC port 0 outputs. Table 1. Port bit 0.0 alternate usage:
01 Data path demodulator, receive
10 Data path demodulator, receive
associated with the phase shift keyed data path operation. Table 2. Port bit 0.1 alternate usage:
01 Data path demodulator, phase
10 Data path demodulator,
11 Data path demodulator, carrier
associated with the phase shift keyed data path operation. Table 3. Port bit 0.2 alternate usage:
1 Receive PN Sync Pulse
and can be controlled by register 9 bits 0 and 1. Table 4. Port bit 0.3 alternate usage:
1 Transmit PN Sync
and can be controlled by register 9 bits 0 and 1. 2 through 6 and 12 through 14 of the chip. and detect whether it is being signaled in a very short time. not, it may go back to sleep. this mode is only for very specialized use.
!Standby Master !Slave PN OUT Track/ !Acquire TX audio mute RX audio mute Force Load RE-SYNC 0x01 RX Polynomial RX-P8 RX-P7 RX-P6 RX-P5 RX-P4 RX-P3 RX-P2 RX-P1 0x02 RX Polynomial RX-BW PN EN 1 PN EN 0 RX-P13 RX-P12 RX-P11 RX-P10 RX-P9 0x03 TX Polynomial TX-P8 TX-P7 TX-P6 TX-P5 TX-P4 TX-P3 TX-P2 TX-P1 0x04 TX Polynomial TX-BW Ring Function 1 Ring Function 0 TX-P13 TX-P12 TX-P11 TX-P10 TX-P9 0x05 ACQ and Track Control PH1 PH0 TD2 TD1 TD0 N2 N1 N0 0x06 TX PWR / DPATH / Ring Flip Switch Polarity (Wakeup) TDE RDE RDP Ring Attn Dial PulseTX PWR 1 TX PWR 0 PA HI/LO 0x07 General Purpose Port 0x08 RSSI A/D A/D bit 7 A/D bit 6 A/D bit 5 A/D bit 4 A/D bit 3 A/D bit 2 A/D bit 1 A/D bit 0 0x09 Gain / TDD Rate / Syncs TDD Rate Select 1875/!7500 Soft Reset TR SW 1 TR SW 0 GAIN 1 GAIN 0 Sync Mode (Bin/Tri) Sync Select TX/!RX Register Structure (continued) 2-12 AT48802
RSSI ID 1 RSSI ID 0 TD5 TD4 TD3 TD2 TD1 TD0 0x0D RSSI Width TW4 TW3 TW2 TW1 TW0 0x0E AUD T/H Delay AUD T/H 1 AUD T/H 0 TD5 TD4 TD3 TD2 TD1 TD0 0x0F AUD T/H Width TW4 TW3 TW2 TW1 TW0 0x10 AUX T/H Delay AUX T/H 1 AUX T/H 0 TD5 TD4 TD3 TD2 TD1 TD0 0x11 AUX T/H Width Intercom Polarity (Wakeup) P0.7 mux 0 = Reg 7 1 = Aux T/H TW4 TW3 TW2 TW1 TW0 0x12 Data Path Delays DPATH DUMP 3 DPATH DUMP 2 DPATH DUMP 1 DPATH LO1 DPATH LO0 DPATH CLK2 DPATH CLK1 DPATH CLK0 0x13 Bit Functions P0.3 OPT TXPN Sync P0.2 OPT RX PN Sync P0.1 OPT1 (dpath) P0.1 OPT0 (dpath) P0.0 OPT1 (dpath) P0.0 OPT0 (dpath) TX CHOP 1 TX CHOP 0 0x14 Sleep Mode / Wake Test Mode Sense Intercom Input Line Sense Flip Switch Input Line Wake Intercom sw latch WAKE Flip sw latch Wake Timer time-out latch Register Structure (Continued) AT48802 2-13
Function Register Bit # Description RESYNC 0 0 0 = Normal PN counter operation. 1 = Re-synchronizes RX PN and TX PN generators to the same counting state. Force Load 0 1 0 = No action. 1 = Forces an immediate loading of the TX PN polynomial from the transmit polynomial register into the PN generator and the RX PN polynomial from the receive polynomial register into the RX PN generator. RX Audio Mute 0 2 0 = Sets a logic 0 to the RX MUTE pin 55. 1 = Sets a logic 1 to the RX MUTE pin 55. TX Audio Mute 0 3 0 = Sets a logic 0 to the TX MUTE pin 59. 1 = Sets a logic 1 to the TX MUTE pin 59. Track !Acquire 04 0 = tau-dither on. 1 = tau-dither off. PN OUT 0 5 0 = TX RX PN pin 25 is disabled and always low. 1 = TX RX PN pin 25 is enabled and toggles. Master !Slave 06 0 = Sets the unit to Slave mode of operation (Unit receiving a link setup request). 1 = Master mode operation (Unit originating a link setup request). Operate !Standby 0 7 See section 2.2 RX-P1 through RX-P8 1 0-7 Low-order receive PN polynomial (shift register tap weights). P1 is LSB. RX-P9 through RX-P13 2 0-4 High-order receive PN polynomial (shift register tap weights). P13 is MSB. PN EN 2 5-6 PN EN 0 PN EN 1 PN EN pin 22 000 0 1 Three-state 1 0 Three-state 111 RX-BW 2 7 0 = Disables receive diversity mode. 1 = Enables receive diversity mode. TX-P1 through TX-P8 3 0-7 Low-order transmit PN polynomial. P1 is LSB. TX-P9 through TX-P13 4 0-4 High-order transmit PN polynomial. P13 is MSB. Ring Func 0 4 5-6 Ring F0 Ring F1 Ringer pin 62 Ring Func 1 0 0 0 0 1 Three-state 1 0 1875 Hz 111 Register Functions (continued) 2-14 AT48802
Function Register Bit # Description TX-BW 4 7 0 = Disables transmit diversity mode. 1 = Enables transmit diversity mode. N0, N1, N2 (N0 = LSB) 5 0-2 Chip Phase Control Step Size. N2, N1, N0 Step Size 000 1/16 Chip 001 2/16 Chip 010 3/16 Chip 011 4/16 Chip 100 5/16 Chip 101 6/16 Chip 110 7/16 Chip 111 8/16 Chip TD0, TD1, TD2 (TD0 = LSB) 5 3-5 Tau-Dither Amplitude. TD2, TD1, TD0 Peak-to-Peak Amplitude 000 1/16 Chip 001 3/16 Chip 010 5/16 Chip 011 7/16 Chip 100 9/16 Chip 101 11/16 Chip 110 13/16 Chip 111 15/16 Chip Note: To load a new tau-dither value, it must be followed by the loading of a Receiver PN code to latch in the new Tau-Dither. PH0, PH1 5 6, 7 Selects one of 4 phases of the R11 sync (from the Master’s Tx PN generator) with which to reset the Master’s receive PN Generator when attempting to acquire code lock with the Slave unit. This is useful in acquisition when transitioning from R11 to R13 which is four times as long. This specialized function is used in the Atmel acquisition software. PA HI/LO 6 0 0 = PA HI/LO pin 16 low. 1 = PA HI/LO pin 16 high. Intended for control of RF transmit power to a lower level in narrowband mode. Register Functions (Continued) (continued) AT48802 2-15
Function Register Bit # Description TX PWR 0 TX PWR 1 6 1-2 Turn RF transmitter on or off. TX PWR 0 TX PWR 1 TX PWR pin 56 000
01 T D D
1 0 !TDD 111 Ring Attn or Dial Pulse 63 For attenuating the ring amplitude as heard in the handset, or for controlling an off hook/pulse dial relay in the base station of a telephone. Useful in handset when there is no separate ring transducer from the speaker. 1 sets 1, 0 sets 0 at pin 8. RDP 6 4 Receive data polarity. Inverts or does not invert receive data in the internal data path. RDE TDE 5 5-6 Receive and transmit data enable. 0 = disable, 1 = enable input pins 49 and 53. Flip Switch Polarity 67 Wakeup edge sense polarity for input pin 21 0 = down edge, 1 = up edge sensing. Port 0 7 0-7 Controls general purpose output port at pins 2-6 and 12-14. Non-inverting. RSSI AD 8 0-7 Read only, contains the data from the A to D converter gathered serially from pins 26, 28, 30. Non-inverting. Bit 0 = LSB. Sync Select Sync Mode 9 0-1 These bits control how transmit and receive epoch sync pulses appear on pin 52. Select Mode Sync pin 52
00 Trinary, rec up,
0 1 Binary, rec up
10 Trinary, xmt up,
1 1 Binary, xmt up Gain 0, 1 9 2-3 Intended to control two receive gain states in the RF module. Gain 0 Gain 1 Gain pin 50 000 1 0 !TDD 111 Register Functions (Continued) (continued) 2-16 AT48802
Function Register Bit # Description TR SW 0, 1 9 4-5 Intended to control the transmit-receive switch in the RF module. TR SW 0 TR SW 1 TR SWITCH pin 19 000 1 0 !TDD 111 Soft Reset 9 6 Not a user control. TDD Rate Select 9 7 See Section 2.11, 1 = 1875 Hz, 0 = 7500 Hz. TX PN Mask A 0-7 These set the length of the PN code. Function is the same for transmit and receive. RX PN Mask B 0-7 Shift Register SizeCode Length Mask R13 8192 FF R12 4096 7F R11 2048 3F R10 1024 1F R9 512 0F R8 256 07 R7 128 03 R6 64 01 RSSI Delay C 0-5 RSSI ID pin 63 delay with respect to internal TDD positive edge. 1 LSB = 2.1 µs or 32MCLK. Bit 0 = LSB. Range is TDD/2. The range is increased to TDD by inverting the signal using RSSI I/D bits 6 and 7 (see below). RSSI ID C 6-7 Used in conjunction with RSSI Delay. 0-1 RSSI ID RSSI ID RSSI ID pin 63 000 0 1 TDD, delayed 1 0 !TDD, delayed 111 Intended to be used with an integrate and dump filter; See Section 2.6. RSSI Width D 0-4 Used in conjunction with RSSI Delay. 1 LSB = 2.1µs or 32MCLK. Bit 0 = LSB. AUD TH Delay AUD TH 0-1 AUD TH Width E E F 0-5 6-7 0-4 Same functionality as RSSI above except applies to the AUD TH signal at pin 15. See section 2.8.3. Register Functions (Continued) (continued) AT48802 2-17
Function Register Bit # Description AUX TH Delay AUX TH 0-1 AUX TH Width 0-5 6-7 0-4 Same functionality as RSSI above except applies to the AUX TH signal at pin 14 if so selected by Register 11 bit Port 0 bit 7 Mux 11 6 Controls a multiplexed output pin 14. 0 selects register 7 bit 6 non-inverted. 1 selects AUX TH function, see above. Intercom Polarity 11 7 Wakeup edge sense polarity for input pin 51. 0 = down edge, 1 = up edge sensing. Data Path Delays 12 0-7 These bits set the delays in the various sub-functions of the internal data path receiver. This allows any arbitrary time delay in the RF module design and still optimally detect data. TX CHOP 0, 1 13 0-1 Intended to control an audio switch which disconnects audio from the RF module modulation input during the receive part of TDD. Pin 60. TX CHOP 0 TX CHOP 1 TX CHOP pin 60 000 1 0 !TDD 111 P0.0 OPT 0, 1 13 2-3 Allows internal data path signals to be observed at pin 2 for engineering purposes, to assist in setting the data path delays. P0.0 OPT1 P0.0 OPT0 Port 0.0 muxed function 0 0 Register 7 bit 0
01 RX_CLK
(me_din_smp)
10 Rx_LO
(delay_div512) 1 1 Dump P0.1 OPT 0, 1 13 4-5 Equivalent function to Port 0 bit 0 above, except for Port 0 bit 1, pin 3. P0.1 OPT1 P0.1 OPT0 Port 0.1 muxed function 0 0 Register 7 bit 1
01 Demod, PSK
10 Demod,
Integrator’s LSB
11 Demod, Carrier
Register Functions (Continued) (continued) 2-18 AT48802
Function Register Bit # Description P0.2 OPT 13 6 0 selects register 7 bit 2 to output at pin 4. 1 selects RX PN Sync to output at pin 4. P0.3 OPT 13 7 0 selects register 7 bit 3 to output at pin 5. 1 selects TX PN Sync to output at pin 5. Wake latches 14 0-2 Allows the microcontroller to see why the unit came awake, to allow proper response. Wake 0 Wake 1 Wake 2 Wakeup Cause 0 0 0 power on reset 0 0 1 timer 0 1 0 FLIPSW 0 1 1 timer and FLIPSW 1 0 0 INTERCOM 1 0 1 timer and INTERCOM 1 1 0 FLIPSW and INTERCOM 1 1 1 Everything WAKE bits are cleared (set to 0) upon entering the sleep mode. See section 2.2. Sense FLIPSW 14 4 Direct sense of FLIPSW input pin 21. For example, when the handset is already awake and the user wants to hang up and start a new call, then the microcontroller could sense this by scanning this bit. Not latched. Sense INTERCOM 14 5 Direct sense of INTERCOM pin 51. For example, when the handset is already awake and the user wants to hang up and start an intercom call, then the microcontroller could sense this by scanning this bit. Not latched. Test Mode 14 7 Not a user function. Register Functions (Continued) *NOTICE: Stresses beyond those listed under “Absolute Maxi- mum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indi- cated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute Maximum Ratings* AT48802 2-19
Parameter Conditions Min Max Units VCC , Supply Voltage 4 6 Volts IDD , Supply Current VCC = 5.0V, MCLK = 15.36 MHz Standby Mode TBD TBD mA µA Ambient Temperature 0 70 °C Operating Characteristics Parameter Min Max Units CMOS Input Specifications VIL, Low Level Input Voltage 0.3 V CC Volts VIH, High level Input Voltage 0.7 V CC Volts IIL, Low Level Input Current -1.0 µA IIH, High Level Input Current 1.0 µA CMOS Output Specifications VOL , Low Level Output Voltage 0.4 Volts VOH , High Level Output Voltage 3.5 Volts Output Current Pins 15, 17, 19, 20, 26, 28, 29, 50, 53, 54, 55, 56, 58, 59, 60, 63 2m A Pins 16, 22, 37, 38, 39, 40, 44, 45, 46, 47, 52, 62 4 mA Pins 2, 3, 4, 5, 6, 12, 13, 14, 42 8 mA Pin 48 16 mA Pins 8, 25 24 mA Unless Otherwise Specified, VCC = +5V, 0°C ≤ TA ≤ 70°C Note: 1. Sleep Mode The following pins are functional and active during sleep mode: all VCC and GND; 18, 21, 31, 48, 51, 58. All other inputs are protected so that regardless of source voltage, within normal 0 to VCC limits, and impedance, including floating, no static current larger than normal static current will be drawn from the power supply. All other outputs are three-stated by a special internal control line from the sleep mode control circuits. 2-20 AT48802
tALE , ALE High Pulse Width 50 ns tAV , Address Valid to ALE Low 10 ns tAH , Address Hold After ALE Low 10 ns tAWL , ALE Low to WR Low 20 ns tW , WR Pulse Width 2 T CLK sec tR , RD Pulse Width 2 T CLK sec tDVW , Data Valid to WR Transition 0 ns tDVR , Data Valid to RD Transition 10 ns tH , Data Hold After WR 10 ns tWAH , WR High to ALE High 10 ns tRAH , RD High to ALE High 10 ns tRVD , RD to Valid Data 0 T CLK sec tDH , Data Hold After RD 0 T CLK sec tARL , ALE Low to RD Low 20 ns TCLK = 1/fMCLK AT48802 2-21
Speed(MHz) PowerSupply Ordering Code Package Operation Range 16 5V ± 20% AT48802-16QC 64Q Commercial (0°C to 70°C) AT48802-16QI 64Q Industrial (-40°C to 85°C)
Ordering Information
64Q 64 Lead, Plastic Gull Wing Quad Flatpack (PQFP) AT48802 2-23