AT48801 ATMEL | Alldatasheet

Document overview

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Technical content

Features

  • Compatible with MCS-51 Products
  • 8K bytes of On-Board Program Memory
  • Fully Static Operation: 0 Hz to 16 MHz
  • 256 x 8 Bit Internal RAM
  • 32 Programmable I/O Lines
  • Three 16 Bit Timer/Counters
  • Eight Interrupt Sources
  • Programmable Serial Channel
  • Low Power Idle and Power Down Modes

Description

The AT48801 is a low-power, high-performance CMOS 8 bit microcomputer with 8K bytes on-board program memory. The device is compatible with the industry standard 80C51 and 80C52 instruction set and pinout. The Atmel AT48801 is a powerful micro- computer which provides a highly flexible and cost effective solution to spread-spec- trum applications. The AT48801 provides the following standard features: 8K bytes of program memory, 256-bytes of RAM, 32 I/O lines, three 16 bit timer/counters, a six-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT48801 is designed with static logic for operation down to zero fre- quency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt sys- tem to continue functioning. The Power Down Mode saves the RAM contents but freezes the oscillator, disabling all other chip functions until the next hardware reset. PQFP Pin Configuration 0629A AT48801 1-1

Supply voltage. GND Ground. Port 0 Port 0 is an 8 bit open drain bidirectional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high-im- pedance inputs. Port 0 can also be configured to be the multiplexed low-or- der address/data bus during accesses to external pro- gram and data memory. In this mode, P0 has internal pul- lups. Port 1 Port 1 is an 8 bit bidirectional I/O port with internal pullups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (I IL) because of the internal pullups. In addition, P1.0 and P1.1 can be configured to be the timer/counter 2 external count input (P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX), respectively, as shown in the following table. Port Pin Alternate Functions P1.0 T2 (external count input to Timer/Counter 2), clock-out P1.1 T2EX (Timer/Counter 2 capture/reload trigger and direction control) Port 2 Port 2 is an 8 bit bidirectional I/O port with internal pullups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (I IL) because of the internal pullups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16 bit addresses (MOVX @ DPTR). In this application, Port 2 uses strong internal pullups when emitting 1s. During accesses to external data memory that use 8 bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port 3 Port 3 is an 8 bit bidirectional I/O port with internal pullups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by (continued) the internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (I IL) because of the pullups. Port 3 also serves the functions of various special features of the AT89C51, as shown in the following table. Port Pin Alternate Functions P3.0 RXD (serial input port) P3.1 TXD (serial output port) P3.2 INT0 (external interrupt 0) P3.3 INT1 (external interrupt 1) P3.4 T0 (timer 0 external input) P3.5 T1 (timer 1 external input) P3.6 WR (external data memory write strobe) P3.7 RD (external data memory read strobe) RST Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. ALE Address Latch Enable is an output pulse for latching the low byte of the address during accesses to external mem- ory. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external data memory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no ef- fect if the microcrontroller is in external execution mode. PSEN Program Store Enable is the read strobe to external pro- gram memory. When the AT48801 is executing code from external pro- gram memory, PSEN is activated twice each machine cy- cle, except that two PSEN activations are skipped during each access to external data memory. EA External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external pro- gram memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program execu- tions. AT48801 1-3

internal clock operating circuit. Output from the inverting oscillator amplifier. Function Register (SFR) space is shown in Table 1. Table 1. AT48801 SFR Map and Reset Values cupied addresses may not be implemented on the chip. the new bits will always be 0.

physically separate from SFR space. Timer 2 in 16 bit capture mode or 16 bit auto-reload mode. the six interrupt sources in the IP register. set when either RCLK = 1 or TCLK = 1. interrupt in up/down counter mode (DCEN = 1). TR2 Start/Stop control for Timer 2. TR2 = 1 starts the timer. counter (falling edge triggered). and the timer is forced to auto-reload on Timer 2 overflow. Table 2. T2CON—Timer/Counter 2 Control Register accesses the SFR at location 0A0H (which is P2).

1 X 1 Baud Rate Generator

Table 3. Timer 2 Operating Modes way as Timer 0 and Timer 1 in the AT89C51. Figure 1. Timer 2 in Capture Mode or counter which upon overflow sets bit TF2 in T2CON. for at least one full machine cycle.

RCAP2H and RCAP2L, which are preset by software. 2’s overflow rate according to the following equation. tor frequency). The baud rate formula is given below. Figure 5. Timer 2 in Clock-Out Mode RCAP2L taken as a 16 bit unsigned integer. Timer 2 as a baud rate generator is shown in Figure 4. This figure is valid only if RCLK or TCLK = 1 in T2CON. used as an extra external interrupt. the Timer 2 or RCAP2 registers.

(RCAP2H, RCAP2L), as shown in the following equation. one another since they both use RCAP2H and RCAP2L. rupts are all shown in Figure 6. EA, which disables all interrupts at once. sitions, since they may be used in future AT89 products. Figure 6. Interrupt Sources Enable Bit = 1 enables the interrupt. Enable Bit = 0 disables the interrupt. ET2 IE.5 Timer 2 interrupt enable bit. ES IE.4 Serial Port interrupt enable bit. ET1 IE.3 Timer 1 interrupt enable bit. EX1 IE.2 External interrupt 1 enable bit. ET0 IE.1 Timer 0 interrupt enable bit. EX0 IE.0 External interrupt 0 enable bit. Table 5. Interrupt Enable (IE) Register

The values shown in this table are valid for TA = -40°C to 85°C and VCC = 5.0V ± 20%, unless otherwise noted. Symbol Parameter Condition Min Max Units VIL Input Low Voltage (Except EA) -0.5 0.2 V CC - 0.1 V VIL1 Input Low Voltage (EA) -0.5 0.2 V CC - 0.3 V VIH Input High Voltage (Except XTAL1, RST) 0.2 V CC + 0.9 V CC + 0.5 V VIH1 Input High Voltage (XTAL1, RST) 0.7 V CC VCC + 0.5 V VOL Output Low Voltage (1) (Ports 1,2,3) IOL = 1.6 mA 0.45 V VOL1 Output Low Voltage (1) (Port 0, ALE, PSEN) IOL = 3.2 mA 0.45 V VOH Output High Voltage (Ports 1,2,3, ALE, PSEN) IOH = -60 µA, VCC = 5V ± 10% 2.4 V IOH = -25 µA 0.75 V CC V IOH = -10 µA 0.9 V CC V VOH1 Output High Voltage (Port 0 in External Bus Mode) IOH = -800 µA, VCC = 5V ± 10% 2.4 V IOH = -300 µA 0.75 V CC V IOH = -80 µA 0.9 V CC V IIL Logical 0 Input Current (Ports 1,2,3) VIN = 0.45V -50 µA ITL Logical 1 to 0 Transition Current (Ports 1,2,3) VIN = 2V -650 µA ILI Input Leakage Current (Port 0, EA) 0.45 < VIN < VCC ±10 µA RRST Reset Pulldown Resistor 50 300 k Ω C IO Pin Capacitance Test Freq. = 1 MHz, TA = 25°C 10 pF ICC Power Supply Current Active Mode, 12 MHz 25 mA Idle Mode, 12 MHz 6.5 mA Power Down Mode (2) VCC = 6V 100 µA VCC = 3V 40 µA DC Characteristics Notes: 1. Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL per port pin: 10 mA Maximum IOL per 8 bit port: Port 0: 26 mA Ports 1,2, 3: 15 mA Maximum total IOL for all output pins: 71 mA If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 2. Minimum V CC for Power Down is 2V. Voltage on Any Pin *NOTICE: Stresses beyond those listed under “Absolute Maxi- mum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indi- cated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute Maximum Ratings* 1-12 AT48801

12 MHz Oscillator Variable Oscillator

1/tCLCL Oscillator Frequency 0 16 MHz tLHLL ALE Pulse Width 127 2t CLCL - 40 ns tAVLL Address Valid to ALE Low 28 t CLCL - 13 ns tLLAX Address Hold After ALE Low 48 t CLCL - 20 ns tLLIV ALE Low to Valid Instruction In 233 4t CLCL - 65 ns tLLPL ALE Low to PSEN Low 43 t CLCL - 13 ns tPLPH PSEN Pulse Width 205 3t CLCL - 20 ns tPLIV PSEN Low to Valid Instruction In 145 3t CLCL - 45 ns tPXIX Input Instruction Hold After PSEN 0 0 ns tPXIZ Input Instruction Float After PSEN 59 t CLCL - 10 ns tPXAV PSEN to Address Valid 75 t CLCL - 8 ns tAVIV Address to Valid Instruction In 312 5t CLCL - 55 ns tPLAZ PSEN Low to Address Float 10 10 ns tRLRH RD Pulse Width 400 6t CLCL - 100 ns tWLWH WR Pulse Width 400 6t CLCL - 100 ns tRLDV RD Low to Valid Data In 252 5t CLCL - 90 ns tRHDX Data Hold After RD 0 0 ns tRHDZ Data Float After RD 97 2t CLCL - 28 ns tLLDV ALE Low to Valid Data In 517 8t CLCL - 150 ns tAVDV Address to Valid Data In 585 9t CLCL - 165 ns tLLWL ALE Low to RD or WR Low 200 300 3t CLCL - 50 3t CLCL + 50 ns tAVWL Address to RD or WR Low 203 4t CLCL - 75 ns tQVWX Data Valid to WR Transition 23 t CLCL - 20 ns tQVWH Data Valid to WR High 433 7t CLCL - 120 ns tWHQX Data Hold After WR 33 t CLCL - 20 ns tRLAZ RD Low to Address Float 0 0 ns tWHLH RD or WR High to ALE High 43 123 t CLCL - 20 t CLCL + 25 ns External Program and Data Memory Characteristics Under operating conditions, load capacitance for Port 0, ALE, and PSEN = 100 pF; load capacitance for all other outputs = 80 pF. AC Characteristics AT48801 1-13

External Data Memory Read Cycle External Program Memory Read Cycle 1-14 AT48801

Symbol Parameter Min Max Units 1/tCLCL Oscillator Frequency 0 16 MHz tCLCL Clock Period 62.5 ns tCHCX High Time 15 ns tCLCX Low Time 15 ns tCLCH Rise Time 20 ns tCHCL Fall Time 20 ns External Clock Drive External Clock Drive Waveforms External Data Memory Cycle AT48801 1-15

Shift Register Mode Timing Waveforms AC Testing Input/Output Waveforms (1) Note: 1. AC Inputs during testing are driven at VCC - 0.5V for a logic 1 and 0.45V for a logic 0. Timing meas- urements are made at VIH min. for a logic 1 and VIL max. for a logic 0. The values in this table are valid for VCC = 5.0V ± 20% and Load Capacitance = 80 pF. Symbol Parameter

12 MHz Osc Variable Oscillator

tXLXL Serial Port Clock Cycle Time 1.0 12t CLCL µs tQVXH Output Data Setup to Clock Rising Edge 700 10t CLCL - 133 ns tXHQX Output Data Hold After Clock Rising Edge 50 2t CLCL - 33 ns tXHDX Input Data Hold After Clock Rising Edge 0 0 ns tXHDV Clock Rising Edge to Input Data Valid 700 10t CLCL - 133 ns Serial Port Timing: Shift Register Mode Test Conditions Float Waveforms (1) Note: 1. For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when a 100 mV change from the loaded V OH /VOL level occurs. 1-16 AT48801

Speed(MHz) PowerSupply Ordering Code Package Operation Range 16 5V ± 20% AT48801-16QC 44Q Commercial (0°C to 70°C) AT48801-16QI 44Q Industrial (-40°C to 85°C)

Ordering Information

44Q 44 Lead, Plastic Gull Wing Quad Flatpack (PQFP) AT48801 1-17