AT43USB353M

AT43USB353M_04 ATMEL | Alldatasheet

Document overview

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Technical content

Features

• AVR® 8-bit RISC Microcontroller with 41.5 or 83 ns Instruction Cycle Time  USB Hub with One Attached and Two External Ports  USB Function with Three Programmable End-points  24 KB Program Memory, 1 KB Data SRAM  32 x 8 General-purpose Working Registers  15 Programmable I/O Port Pins  12-channel 10-bit ADC  One 8-bit Timer/Counter with Separate Pre-scaler  One 16-bit Timer/Counter with Separate Pre-scaler and Two PWMs  External and Internal Interrupt Sources  Programmable Watchdog Timer  6 MHz Oscillator with On-chip PLL  5V Operation with On-chip 3.3V Power Supply  48-lead LQFP Package

Description

The Atmel AT43USB353M is an 8-bit microcontroller based on the AVR RISC archi- tecture. By executing powerful instructions in a single clock cycle, the A T43USB353M achieves throughputs approaching 24 MIPS. The AVR core combines a rich instruc- tion set with 32 general-purpose working registers. All 32 registers are directly connected to the ALU allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code effi- cient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The AT43USB353M features an on-chip 24-Kbyte of masked ROM program memory and 1-Kbyte of data memory. It is supported by a standard set of peripherals such as timer/counter modules, watchdog timer and internal and external interrupt sources. The major peripheral included in the A T43USB353M is a full-speed USB 2.0 Hub with an embedded function and a 12-channel Analog-to-Digital Converter (ADC) for use in applications such as game controllers. The A T43USB353M is binary compatible with the A T43USB355. Program develop- ment and debugging for the AT43USB353M uses the AT43DK355, including all its tools and libraries. Pin Configuration Figure 1. AT43USB353M 48-lead LQFP

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3307B–USB–4/04 Pin Assignment Pin# Signal Type Pin# Signal Type

1 PD1 Bi-directional 25 ADC8 Input

2 PD0 Bi-directional 26 ADC7 Input

3 DP3 Bi-directional 27 ADC6 Input

4 DM3 Bi-directional 28 ADC5 Input

5 DP2 Bi-directional 29 ADC4 Input

6 DM2 Bi-directional 30 ADC3 Input

7 DP0 Bi-directional 31 ADC2 Input

8 DM0 Bi-directional 32 ADC1 Input

9 CEXT1 Power Supply/Ground 33 ADC0 Input

10 VCC1 Power Supply/Ground 34 VCCA Power Supply/Ground

11 VSS1 Power Supply/Ground 35 CEXTA Power Supply/Ground

12 P A7 Bi-directional 36 VSSA Power Supply/Ground

13 P A6 Bi-directional 37 XTAL1 Input

14 P A5 Bi-directional 38 XTAL2 Output

15 P A4 Bi-directional 39 LFT Output

16 P A3 Bi-directional 40 CEXT2 Power Supply/Ground

17 P A2 Bi-directional 41 VCC2 Power Supply/Ground

18 P A1 Bi-directional 42 VSS2 Power Supply/Ground

19 P A0 Bi-directional 43 CPUSEL Input

20 RESETN Input 44 PD6 Bi-directional

21 TEST Input 45 PD5 Bi-directional

22 ADC11 Input 46 PD4 Bi-directional

23 ADC10 Input 47 PD3 Bi-directional

24 ADC9 Input 48 PD2 Bi-directional

3307B–USB–4/04 Signal Description Name Type Function VCC1, 2 Power Supply/Ground 5V Digital Power Supply VCCA Power Supply/Ground 5V Power Supply for the ADC VSS1, 2 Power Supply/Ground Digital Ground VSSA Power Supply/Ground Ground for the ADC CEXT1, 2 Power Supply/Ground External Capacitors for Power Supplies – High quality 2.2 µF capacitors must be connected to CEXT1 and 2 for proper operation of the chip. CEXT A Power Supply/Ground External Capacitor for Analog Power Supply – A high quality 0.33 µF capacitor must be connected to CEXT A for proper operation of the chip. XT AL1 Input Oscillator Input – Input to the inverting oscillator amplifier. XT AL2 Output Oscillator Output – Output of the inverting oscillator amplifier. CPUSEL Input CPU Speed Select – This pin selects the CPU clock frequency. If high, the CPU runs at 12 MHz, if low it runs at 24 MHz. LFT Input PLL Filter – For proper operation of the PLL, this pin should be connected through a 0.01 µF capacitor in parallel with a 100Ω resistor in series with a 0.1 µF capacitor to ground (VSS). Both capacitors must be high quality ceramic. DPO Bi-directional Upstream Plus USB I/O – This pin should be connected to CEXT1 through an external 1.5 kΩ. DMO Bi-directional Upstream Minus USB I/O DP[2,3] Bi-directional Downstream Plus USB I/O – Each of these pins should be connected to VSS through an external 15 kΩ resistor. DP[2,3] and DM[2,3] are the differential signal pin pairs to connect downstream USB devices. DM[2,3] Bi-directional Downstream Minus USB I/O – Each of these pins should be connected to VSS through an external 15 kΩ resistor. P A[0:7] Bi-directional Port A[0:7] – Bi-directional 8-bit I/O port with 2 mA drive strength and a programmable pull-up resistor. PD[0:6] Bi-directional Port D[0:6] – Bi-directional I/O ports with 2 mA drive strength and a programmable pull-up resistor. PortD[2,3,5,6] have dual functions as shown below: Port Pin Alternate Function PD2 INT0, External Interrupt 0 PD3 INT1, External Interrupt 1 PD4 ICP , Timer/Counter/Input Capture PD5 OC1A Timer/Counter1 Output Compare A PD6 OC1B Timer/Counter1 Output Compare B ADC[0:11] Input ADC Input[0:11] – 12-bit input pins for the ADC. TEST Input Test Pin – This pin should be tied to ground. RESETN Input Reset – Active Low.

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Figure 2. The AT43USB353M Enhanced RISC Architecture chips are used. Refer to Table 3 on page 8 for the differences between these two devices.

15 GPIO

two independent USB devices, each having its own device addresses and control end-points. cies of the various modules of the AT43USB353M is summarized in Table 1. Note: Refer to page 15 for details of the on chip oscillator and PLL. the operation is executed, and the result is stored back in the register file – in one clock cycle. tion registers are the 16-bit X-, Y- and Z-registers. shows the AT43USB353M AVR Enhanced RISC microcontroller architecture. the Data Space locations following those of the register file, $20 - $5F. instruction is being executed, the next instruction is pre-fetched from the program memory. a downloadable SRAM or a mask programmed ROM. Table 1. Module Clock Frequencies

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With the relative jump and call instructions, the whole 24K address space is directly accessed. tains a 16- or 32-bit instruction. interrupts are executed). The 10-bit SP is read/write accessible in the I/O space. supported in the AVR architecture. between two registers or on a single register apply to the entire register file. Table 2. AVR CPU General-purpose Working Register

3307B–USB–4/04 As shown in Table 2, each register is also assigned a data memory address, mapping them directly into the first 32 locations of the user Data Space. Although not being physically imple- mented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y-, and Z-registers can be set to index any register in the file. X-, Y- and Z- Registers Registers R26..R31 contain some added functi ons to their general-purpose usage. These reg- isters are address pointers for indirect addressing of the Data Space. The three indirect address registers X, Y, and Z are defined as: In the different addressing modes these address registers have functions as fixed displace- ment, automatic increment and decrement (see the descriptions for the different instructions). ALU – Arithmetic Logic Unit The high-performance AVR ALU operates in direct connection with all 32 general-purpose working registers. Within a single clock cycle, ALU operations between registers in the register file are executed. The ALU operations are divided into three main categories – arithmetic, log- ical and bit-functions. Program Memory The AT43USB353M contains 24K bytes on-chip masked programmable ROM program mem- ory. Since all instructions are 16- or 32-bit words, the program memory is organized as 12K x 16. The AT43USB353M Program Counter (PC) is 14 bits wide, thus addressing the 12,288 program memory addresses. Constant tables can be allocated within the entire program memory address space (see the LPM - Load Program Memory instruction description). Where the functions overlap, the AT43USB353M and the AT43USB355 are binary compati- ble. A firmware written for the AT43USB355 will work unaltered on the AT43USB353M as long as the functions are supported by the AT43USB353M. The only functional difference between the two devices are listed in Table 3. X-register 15 XH XL 0 70 70 Y -register 15 YH YL 0 70 70 Z-register 15 ZH ZL 0 70 70

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Data Memory locations address the Register file, the I/O Memory and the internal data SRAM. pointer registers. Direct addressing reaches the entire data space. address given by the Y- or Z-register. ment, the address registers X, Y, and Z are decremented and incremented. SRAM in the AT43USB353M are all accessible through these addressing modes. overview of these registers. Table 3. Functional Difference Between AT43USB355 and AT43USB353M

Table 4. SRAM Organization

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Table 5. USB Hub and Function Registers

Table 5. USB Hub and Function Registers (Continued)

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Table 6. USB Hub and Function Registers

Table 7. I/O Memory Space

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throughout this document are shown with the SRAM address in parentheses. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. used is strictly defined by the firmware of the AT43USB353M and can vary from 0 to 2. permanently attached ports as long as the Hub Descriptor identifies them as such. OUT or bulk IN or OUT end-points. Figure 3. USB Hardware

3307B–USB–4/04 Functional Description On-chip Power Supply The AT43USB353M contains three on-chip power supplies that generate 3.3V with a capacity of 30 mA each from the 5V power input. The on-chip power supplies are intended to supply the AT43USB353M internal circuit and the 1.5K pull-up resistor only and should not be used for other purposes. External 2.2 µF filter capacitors are required at the power supply outputs, CEXT1 and CEXT2, and a 0.33 µF capacitor at CEXTA. The internal power supplies can be disabled as described in the next paragraph. The user should be careful when the GPIO pins are required to supply high-load currents. If the application requires that the GPIO supply curre nts beyond the c apability of the on-chip power supply, the AT43USB353M should be supplied by an external 3.3V power supply. In this case, the 5V V CC power supply pin should be left unconnected and the 3.3V power supplied to the chip through the CEXT1, CEXT2 and CEXTA pins. I/O Pin Characteristics The I/O pins of the AT43USB353M should not be directly connected to voltages less than V SS or more than the voltage at the CEXTx pins. If it is necessary to violate this rule, insert a series resistor between the I/O pin and the source of the external signal source that limits the current into the I/O pin to less than 2 mA. Under no circumstance should the external voltage exceed 5.5V. To do so will put the chip under excessive stress. Oscillator and PLL All clock signals required to operate the AT43US B353M are derived from an on-chip oscillator. To reduce EMI and power dissipation, the oscillator is designed to operate with a 6 MHz crys- tal. An on-chip PLL generates the high frequency for the clock/data separator of the Serial Interface Engine. In the suspended state, the oscillator circuitry is turned off. The oscillator of the AT43USB353M is a special, low-drive type, designed to work with most crystals without any external components. The crystal must be of the parallel resonance type requiring a load capacitance of about 10 pF. If the crystal requires a higher value capacitance, external capacitors can be added to the two terminals of the crystal and ground to meet the required value. To assure quick start-up, a crystal with a high Q, or low ESR, should be used. To meet the USB hub frequency accuracy and stability requirements for hubs, the crystal should have an accuracy and st ability of better than 100 PPM. The use of a ceramic resonator in place of the crystal is not recommended because a resonator would not have the necessary frequency accuracy and stability. The clock can also be externally sourced. In this case, connect the clock source to the XTAL1 pin, while leaving XTAL2 pin floating. The switching level at the OSC1 pin can be as low as 0.47V and a CMOS device is required to drive this pin to maintain good noise margins at the low switching level. For proper operation of the PLL, an external RC filter consisting of a series RC network of 100Ω and 0.1 µF in parallel with a 0.01 µF capacitor must be connected from the LFT pin to V SS. Use only high-quality ceramic capacitors.

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Figure 4. Oscillator and PLL register in order to enable the interrupt.

6.000 MHz

Table 8. Reset and Interrupt Vectors

3307B–USB–4/04 The most typical and general program setup for the Reset and Interrupt Vector Addresses are: USB related interrupt events are routed to reset vectors 13 and 2 through a separate set of interrupt, interrupt enable and interrupt mask registers that are mapped to the data SRAM space. These interrupts must be enabled though their control register bits. In the event an interrupt is generated, the source of the interrupt is identified by reading the interrupt registers. The USB frame and transaction related interrupt events, such as Start of Frame interrupt, are grouped in one set of registers: USB Interrupt Flag Register, USB Interrupt Enable Register and USB Interrupt Mask Register. The USB Bus reset and suspend/resume are grouped in another set of registers: Suspend/Resume Register, Suspend/Resume Interrupt Enable Reg- ister and Suspend/Resume Interrupt Mask Register. Some applications may include firmware routines lasting periods that cannot be interrupted. At the same time, other less critical events may need attention after the critical routine is com- pleted. The AT43USB353M solves this problem by having interrupt mask registers in addition to the interrupt enable registers of the USB related interrupts. The difference between the mask and enable registers is:  The enable register enables the interrupt so it is captured into the interrupt register. If it is not enabled and an interrupt occurs, the interrupt will be lost.  The mask register merely masks the interrupt from interrupting the CPU. Upon unmasking, the pending interrupt is triggered. Address Labels Code Comments $000 jmp RESET ; Reset Handler $004 jmp EXT_INT1 ; IRQ1 Handler $00E jmp TIM0_OVF ; Timer0 Overflow Handler $018 jmp USB_HW ; USB Handler $00d MAIN: ldi r16, high (RAMEND) ; Main Program start $00e out SPH, r16 $00f ldi r16, low (RAMEND) $010 out SPL, r16 $011 <instr> xxx

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Figure 5. AT43USB353M Interrupt Structure microcontroller lasts for 24 oscillator periods. – Resets not separated: A USB bus reset will also reset the microcontroller. SPRSMSK register, is also set.

be placed at these locations. The circuit diagram in Figure 6 shows the reset logic. Figure 6. Reset Logic Power-on Reset period can be extended. starts the MCU after the Time-out period t TOUT has expired. Figure 7. External Reset During Operation

1 MHz Clock

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the falling edge of this pulse, the delay timer starts counting the Time-out period t TOUT. Figure 8. Watchdog Reset During Operation Interrupt Mask Register) and TIMSK (Timer/Counter Interrupt Mask Register). set (one) when a Return from Interrupt instruction, RETI, is executed. bit is set (one), and will be executed by order of priority. as the interrupt condition is active.

1 XTAL Cycle

3307B–USB–4/04 General Interrupt Mask Register – GIMSK  Bit 7 – INT1: External Interrupt Request 1 Enable When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control1 bits 1/0 (ISC11 and ISC10) in the MCU general Control Register (MCUCR) defines whether the external interrupt is acti- vated on rising or fa lling edge of the INT1 pin or level sensed. Activity on the pin will cause an interrupt request even if INT1 is configured as an output. The corresponding interrupt of Exter- nal Interrupt Request 1 is executed from program memory address $004. See also “External Interrupts” on page 24.  Bit 6 – INT0: Interrupt Request 0 (Suspend/Resume Interrupt) Enable When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the MCU general Control Register (MCUCR) defines whether the external interrupt is acti- vated on rising or fa lling edge of the INT0 pin or level sensed. Activity on the pin will cause an interrupt request even if INT0 is configured as an output. The corresponding interrupt of Inter- rupt Request 0 is executed from program memory address $002. See also “External Interrupts” on page 24.  Bits 5..0 – Res: Reserved Bits These bits are reserved bits in the AT43USB353M and always read as zero. General Interrupt Flag Register – GIFR  Bit 7 – INTF1: External Interrupt Flag1 When an event on the INT1 pin triggers an interrupt request, INTF1 becomes set (one). If the I-bit in SREG and the INT1 bit in GIMSK are set (one), the MCU will jump to the interrupt vec- tor at address $004. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.  Bit 6 – INTF0: Interrupt Flag0 (Suspend/Resume Interrupt Flag) When an event on the INT0 (that is, a USB event-related interrupt) triggers an interrupt request, INTF0 becomes set (one). If the I-bit in SREG and the INT0 bit in GIMSK are set (one), the MCU will jump to the interrupt vector at address $002. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.  Bits 5..0 – Res: Reserved Bits These bits are reserved bits in the AT43USB353M and always read as zero. B i t 7 6 5 4 3 210 Read/Write R/W R/W R R R R R R Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Read/Write R/W R/W R R R R R R Initial Value 0 0 0 0 0 0 0 0

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3307B–USB–4/04 Timer/Counter Interrupt Mask Register – TIMSK  Bit 7 – TOIE1: Timer/Counter1 Overflow Interrupt Enable When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Overflow interrupt is enabled. The corresponding interrupt (at vector $006) is executed if an overflow in Timer/Counter1 occurs, i.e., when the TOV1 bit is set in the Timer/Counter Interrupt Flag Register (TIFR).  Bit 6 – OCE1A: Timer/Counter1 Output CompareA Match Interrupt Enable When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareA Match interrupt is enabled. The corresponding interrupt (at vector $004) is executed if a CompareA match in Timer/Counter1 occurs, i.e., when the OCF1A bit is set in the TIFR.  Bit 5 – OCIE1B: Timer/Counter1 Output CompareB Match Interrupt Enable When the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareB Match interrupt is enabled. The corresponding interrupt (at vector $005) is executed if a CompareB match in Timer/Counter1 occurs, i.e., when the OCF1B bit is set in the TIFR.  Bit 4 – Res: Reserved Bit This bit is a reserved bit in the AT43USB353M and always reads zero.  Bit 3 – TICIE1: Timer/Counter1 Input Capture Interrupt Enable When the TICIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Input Capture Event Interrupt is enabled. The corresponding interrupt (at vec- tor $003) is executed if a capture-triggering event occurs on pin 31, ICP, i.e., when the ICF1 bit is set in the TIFR.  Bit 2 – Res: Reserved Bit This bit is a reserved bit in the AT43USB353M and always reads zero.  Bit 1 – TOIE0: Timer/Counter0 Overflow Interrupt Enable When the TOIE0 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt (at vector $007) is executed if an overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the TIFR.  Bit 0 – Res: Reserved Bit This bit is a reserved bit in the AT43USB353M and always reads zero. Bit 7 6 5 4 3 2 1 0 $39 ($59) TOIE1 OCIE1A OCIE1NB – TICIE1 – TOIE0 – TIMSK Read/Write R/W R/W R/W R R/W R R/W R Initial Value 0 0 0 0 0 0 0 0

3307B–USB–4/04 Timer/Counter Interrupt Flag Register – TIFR  Bit 7 – TOV1: Timer/Counter1 Overflow Flag The TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by the hardware when executing the corresponding interrupt handling vector. Alternatively, TOV1 is cleared by writing a logic one to the flag. When the I-bit in SREG, and TOIE1 (Timer/Counter1 Overflow Interrupt Enable), and TOV1 are set (one), the Timer/Counter1 Overflow Interrupt is executed. In PWM mode, this bit is set when Timer/Counter1 changes counting direction at $0000.  Bit 6 – OCF1A: Output Compare Flag 1A The OCF1A bit is set (one) when compare ma tch occurs between the Timer/Counter1 and the data in OCR1A - Output Compare Register 1A. OCF1A is cleared by the hardware when exe- cuting the corresponding interrupt handling vector. Alternatively, OCF1A is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1A (Timer/Counter1 Compare match InterruptA Enable), and the OCF1A are set (one), the Timer/Counter1 Compare A match Inter- rupt is executed.  Bit 5 – OCF1B: Output Compare Flag 1B The OCF1B bit is set (one) when compare ma tch occurs between the Timer/Counter1 and the data in OCR1B - Output Compare Register 1B. OCF1B is cleared by the hardware when exe- cuting the corresponding interrupt handling vector. Alternatively, OCF1B is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1B (Timer/Counter1 Compare match InterruptB Enable), and the OCF1B are set (one), the Timer/Counter1 Compare B match Inter- rupt is executed.  Bit 4 – Res: Reserved Bit This bit is a reserved bit in the AT43USB353M and always reads zero.  Bit 3 – ICF1: - Input Capture Flag 1 The ICF1 bit is set (one) to flag an input capture event, indicating that the Timer/Counter1 value has been transferred to the input capture register - ICR1. ICF1 is cleared by the hard- ware when executing the corresponding interrupt handling vector. Alternatively, ICF1 is cleared by writing a logic one to the flag. When the SREG I-bit, and TICIE1 (Timer/Counter1 Input Capture Interrupt Enable), and ICF1 are set (one), the Timer/Counter1 Capture Interrupt is executed.  Bit 2 – Res: Reserved Bit This bit is a reserved bit in the AT43USB353M and always reads zero.  Bit 1 – TOV: Timer/Counter0 Overflow Flag The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by the hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG I- bit, and TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set ( one), the Timer/Counter0 Overflow interrupt is executed.  Bit 0 – Res: Reserved Bit This bit is a reserved bit in the AT43USB353M and always reads zero. B i t 7 6 543 2 1 0 $38 ($58) TOV1 OCF1A OCIFB – ICF1 – TOV0 – TIFR Read/Write R/W R/W R/W R R/W R R/W R Initial Value 0 0 0 0 0 0 0 0

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3307B–USB–4/04 External Interrupts The external interrupts are triggered by the INT0 and INT1 pins. Observe that, if enabled, the INT0/INT1 interrupt will trigger even if the INT0/INT1 pin is configured as an output. This fea- ture provides a way of generating a software interrupt. The external interrupts can be triggered by a falling or rising edge or a low level. This is set up as indicated in the specification for the MCU Control Register (MCUCR) and the Interr upt Sense Control R egister (ISCR). When INT0/INT1 is enabled and is configured as level triggered, the interrupt will trigger as long as the pin is held low. INT0/INT1 is set up as described in the specification for the MCU Control Register (MCUCR). Interrupt Response Time The interrupt execution response for all the enabled AVR interrupts is 4 clock cycles minimum. 4 clock cycles after the interrupt flag has been set, the program vector address for the actual interrupt handling routine is executed. During this 4 clock cycle period, the Program Counter (2 bytes) is pushed onto the Stack, and the Stack Pointer is decremented by 2. The vector is nor- mally a jump to the interrupt routine, and this jump takes 3 clock cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed before the interrupt is served. A return from an interrupt handling routine (same as for a subroutine call routine) takes 4 clock cycles. During these 4 clock cycles, the Program Counter (2 bytes) is popped back from the Stack, the Stack Pointer is incremented by 2, and the I flag in SREG is set. When the AVR exits from an interrupt, it will always return to the main program and execute one more instruc- tion before any pending interrupt is served.

is selected as Sleep Mode. When SM is set (1), Power Down mode is selected as sleep mode. when entering the Sleep Mode. that activate the interrupt are defined in Table 10. that activate the interrupt are defined in Table 10. Table 9. INT1 Sense Control 0 0 The low level of INT1 generates an interrupt request. 1 0 The falling edge of INT1 generates an interrupt request. 1 1 The rising edge of INT1 generates an interrupt request. Table 10. INT1 Sense Control 0 0 The low level of INT0 generates an interrupt request. 1 0 The falling edge of INT0 generates an interrupt request. 1 1 The rising edge of INT0 generates an interrupt request.

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The USB interrupts are described below. in an interrupt acknowledge register. Table 11. USB Interrupt Sources number is stored in the two Frame Number Registers. EOF2 Activated whenever the hub's frame timer reaches its EOF2 time point. Function EP0 Interrupt See “Control Transfers at Control End-point EP0” on page 58 for details. be written by new data from the microcontroller. be written by new data from the microcontroller. be written by new data from the microcontroller. Hub EP0 Interrupt See “Control Transfers at Control End-point EP0” on page 58 for details. place the embedded function in the suspend state. function out of the suspended state. required. Be very careful when using this feature.

This bit is asserted after the USB hardware receives a valid SOF packet. This bit is asserted 10 clocks before the expected start of a frame. This bit is reserved and always reads as zero.

1. RX OUT Packet is set (control and OUT end-points)
2. TX Packet Ready is cleared AND TX Complete is set (control and IN end-points)
3. RX SETUP is set (control end-points only)

Table 12. USB End-point Interrupt Sources

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3307B–USB–4/04 USB Interrupt Mask Register – UIMSKR  Bit 7 – SOF IMSK: Start of Frame Interrupt Mask When the SOF IMSK bit is set (1), the Start of Frame Interrupt is masked.  Bit 6 – EOF2 IMSK: EOF2 Interrupt Mask When the EOF2 IMSK bit is set (1), the EOF2 Interrupt is masked.  Bit 5 – Res: Reserved bit This bit is reserved and always read as zero.  Bit 4 – FEP3 IMSK: Function End-point 3 Interrupt Mask When the FE3 IMSK bit is set (1), the Function End-point 3 Interrupt is masked.  Bit 3 – HEP0 IMSK: End-point 0 Interrupt Mask When the HEP0 IMSK bit is set (1), the Hub End-point 0 Interrupt is masked.  Bit 2 – FEP2 IMSK: End-point 2 Interrupt Mask When the FE2 IMSK bit is set (1), the Function End-point 2 Interrupt is masked.  Bit 1 – FEP1 IMSK: End-point 1 Interrupt Mask When the FE1 IMSK bit is set (1), the Function End-point 1 Interrupt is masked.  Bit 0 – FEP0 IMSK: End-point 0 Interrupt Mask When the FE0 IMSK bit is set (1), the Function End-point 0 Interrupt is masked. Bit 7 6 5 4 3 2 1 0 $1FF6 SOF IMSK EOF2 IMSK – FEP3 IMSK HEP0 IMSK FEP2 IMSK FEP1 IMSK FEP0 IMSK UIMSKR Read/Write R/W R/W R R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0

3307B–USB–4/04 USB Interrupt Acknowledge Register – UIAR  Bit 7 – SOF INTACK: Start of Frame Interrupt Acknowledge The microcontroller firmware writes a 1 to this bit to clear the SOF INT bit.  Bit 6 – EOF2 INTACK: EOF2 Interrupt Acknowledge The microcontroller firmware writes a 1 to this bit to clear the EOF2 INT bit.  Bit 5 – Res: Reserved bit This bit is reserved and is always read as zero.  Bit 4 – FEP3 INTACK: Function End-point 3 Interrupt Acknowledge The microcontroller firmware writes a 1 to this bit to clear the FEP3 INT bit.  Bit 3 – HEP0 INTACK: Hub End-point 0 Interrupt Acknowledge The microcontroller firmware writes a 1 to this bit to clear the HEP0 INT bit.  Bit 2 – FEP2 INTACK: Function End-point 2 Interrupt Acknowledge The microcontroller firmware writes a 1 to this bit to clear the FEP2 bit.  Bit 1 – FEP1 INTACK: Function End-point 1 Interrupt Acknowledge The microcontroller firmware writes a 1 to this bit to clear the FEP1 bit.  Bit 0 – FEP0 INTACK: Function End-point 0 Interrupt Acknowledge The microcontroller firmware writes a 1 to this bit to clear the FEP0 INT bit. B i t 7654 3 2 1 0 $1FF5 SOF INTACK EOF2 INT ACK – FEP3 INTACK HEP0 INTACK FEP2 IMSK FEP1 INT ACK FEP0 INTACK UIAR Read/Write W W R W W W W W Initial Value 0 0 0 0 0 0 0 0

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3307B–USB–4/04 USB Interrupt Enable Register – UIER  Bit 7 – SOF IE: Enable Start of Frame Interrupt When the SOF IE bit is set (1), the Start of Frame Interrupt is enabled.  Bit 6 – EOF2 IE: Enable EOF2 Interrupt When the EOF2 IE bit is set (1), the EOF2 Interrupt is enabled.  Bit 5 – Res: Reserved bit This bit is reserved and always read as zero.  Bit 4 – FEP3 IE: Enable Function End-point 3 Interrupt When the FE3 IE bit is set (1), the Function End-point 3 Interrupt is enabled.  Bit 3 – HEP0 IE: Enable End-point 0 Interrupt When the HEP0 IE bit is set (1), the Hub End-point 0 Interrupt is enabled.  Bit 2 – FEP2 IE: Enable End-point 2 Interrupt When the FE2 IE bit is set (1), the Function End-point 2 Interrupt is enabled.  Bit 1 – FEP1 IE: Enable End-point 1 Interrupt When the FE1 IE bit is set (1), the Function End-point 1 Interrupt is enabled.  Bit 0 – FEP0 IE: Enable End-point 0 Interrupt When the FE0 IE bit is set (1), the Function End-point 0 Interrupt is enabled. Suspend/Resume Register – SPRSR  Bit 7..4 – Res: Reserved Bits These bits are reserved and are always read as zeros.  Bit 3 – BUS INT: USB Bus Interrupt When the USB reset separation feature is enabled (SPRSIE and SPRSMSK bits 3 are set to 1) the BUS INT bit is set when USB bus reset is detected by the USB hardware.  Bit 2 – FRWUP: Function Remote Wakeup The USB hardware sets this bit to signal that External Interrupt 1 is detected indicating remote wakeup. An interrupt is generated if the FRWUP IE bit of the SPRSIE register is set.  Bit 1 – RSM: Resume The USB hardware sets this bit when a USB resume signaling is detected at any of its port except Port 1. An interrupt is generated if the RSM IE bit of the SPRSIE register is set.  Bit 0 – GLB SUSP: Global Suspend The USB hardware sets this bit when a USB gl obal suspend signaling is detected. An interrupt is generated if the GLBSUSP IE bit of the SPRSIE register is set. B i t 7 654 32 1 0 $1FF3 SOF IE EOF2 IE – FEP3 IE HEP0 IE FEP2 IE FEP1 IE FEP0 IE UIER Read/Write R/W R/W R R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 B i t 7 6543 2 1 0 $1FFA – – – – BUS INT FRWUP RSM GLB SUSP SPRSR Read/Write R R R R R/W R R R Initial Value 0 0 0 0 0 0 0 0

3307B–USB–4/04 Suspend/Resume Interrupt Enable Register – SPRSIE  Bit 7..4 – Res: Reserved Bits These bits are reserved and are always read as zeros.  Bit 3 – BUS INT EN: USB Reset Interrupt Enable When the BUS INT EN bit is set, the USB and microcontroller resets are separated. A USB bus reset (SE0 for longer than 3 ms) will reset the USB hardware only and not the microcon- troller. However, an interrupt to the microcontroller will be generated and bit 3 of SPRSR is set.  Bit 2 – FRWUP IE: Function Remote Wakeup Interrupt Enable Setting the FRWUP IE bit will initiate an interrupt whenever the FRWUP bit of SPRSR is set.  Bit 1 – RSM IE: Resume Interrupt Enable Setting the RSM IE bit will initiate an interrupt whenever the RSM bit of SPRSR is set.  Bit 0 – GLB SUSP IE: Global Suspend Interrupt Enable Setting the GLB SUSP IE bit will initiate an interrupt whenever the GLB SUSP bit of SPRSR is set. Suspend/Resume Interrupt Mask Register – SPRSMSK The bits of the Suspend/Resume Mask Register are used to make an interrupt caused by an event in the Suspend/Resume Register visible to the microcontroller. The Suspend/Resume Interrupt Enable Register bits enable the interrupt while the Suspend/Resume Interrupt Mask Register allows the microcontroller to control when it wants visibility to an interrupt. 1 = Enable Mask, 0 = Disable Mask.  Bit 7..4 – Res: Reserved Bits These bits are reserved and are always read as zeros.  Bit 3 – BUS INT MSK: USB Reset Interrupt Mask  Bit 2 – FRWUP MSK: Function Remote Wakeup Interrupt Mask  Bit 1 – RSM MSK: Resume Interrupt Mask  Bit 0 – GLB SUSP MSK: Global Suspend Interrupt Enable Bit 7 6 5 4 3 2 1 0 $1FF9 – – – – BUS INT FRWUP RSM GLB SUSP SPRSIE Read/Write R R R R R/W R R R Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 $1FF8 – – – – BUS INT MSK FRWUP MSK RSM GLB SUSP SPRSMSK Read/Write R R R R W W W W Initial Value 0 0 0 0 0 0 0 0

32 AT43USB353M

3307B–USB–4/04 AVR Register Set Status Register and Stack Pointer Status Register – SREG B i t 7 – I: Global Interrupt Enable The global interrupt enable bit must be set (one) for the interrupts to be enabled. The individ- ual interrupt enable control is then performed in separate control registers. If the global interrupt enable bit is cleared (zero), none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by the hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. B i t 6 – T: Bit Copy Storage The bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T bit as source and des- tination for the operated bit. A bit from a register in the register file can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the register file by the BLD instruction. B i t 5 – H: Half Carry Flag The half carry flag H indicates a half carry in some arithmetic operations. See the Instruction Set Description for detailed information. B i t 4 – S: Sign Bit, S = N⊕V The S-bit is always an exclusive or between the negative flag N and the two's complement overflow flag V. See the Instruction Set Description for detailed information. B i t 3 – V: Two's Complement Overflow Flag The two's complement overflow flag V supports two's complement arithmetics. See the Instruction Set Description for detailed information. B i t 2 – N: Negative Flag The negative flag N indicates a negative result after the different arithmetic and logic opera- tions. See the Instruction Set Description for detailed information. B i t 1 – Z: Zero Flag The zero flag Z indicates a zero result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information. B i t 0 – C: Carry Flag The carry flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set Description for detailed information. Note that the status register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt routine. This must be handled by software. B i t7 6543 2 1 0 $3F ($5F) ITHSV N Z C S R E G Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0

3307B–USB–4/04 Stack Pointer Register – SP The Stack Pointer points to the data SRAM stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The stack pointer must be set to point above $60. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when an address is pushed onto the Stack with subroutine calls and interrupts. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction and it is incremented by two when an address is popped from the Stack with return from subroutine RET or return from interrupt RETI. Sleep Modes To enter the sleep modes, the SE bit in MCUCR must be set (one) and a SLEEP instruction must be executed. If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU awakes, executes the interrupt routine, and resumes execution from the instruction following SLEEP. The contents of the register file, SRAM and I/O memory are unaltered. If a reset occurs during sleep mode, the MCU wakes up and executes from the Reset vector. Power Down Mode When the SM bit is set (one), the SLEEP instruction forces the MCU into the Power Down Mode. In this mode, the external oscillator is stopped, while the external interrupts continue operating. Only an external reset, an external level interrupt on INT0 or INT1, can wake up the MCU. Note that when a level triggered interrupt is used for wake-up from power down, the low level must be held for a time longer than the reset delay time-out period t TOUT. Otherwise, the MCU will fail to wake up. Bit 15 14 13 12 11 10 9 8 $3E ($5E) I T H S V N Z C SPH $3D ($5D) SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL 76 5 4 3 2 10 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 00 0 0 0 0 00

34 AT43USB353M

inputs like those of the AT43USB355. stop, can be selected as clock sources. the Timer/Counter is always 12 MHz. Figure 9. Timer/Counter Prescaler

stopped as described in the specification for the Timer/Counter0 Control Register (TCCR0). Figure 10. Timer/Counter0 Block Diagram

36 AT43USB353M

These bits are reserved bits in the AT43USB355 and always read as zero. The Clock Select0 bits 2, 1 and 0 define the prescaling source of Timer/Counter0. are scaled directly from the CK 12 MHz clock. ing in the clock cycle following the write operation. Table 13. 12 MHz Clock Prescale Select

001 C K

010 C K / 8

011 C K / 6 4

100 C K / 2 5 6

101 C K / 1 0 2 4

Figure 11. Timer/Counter1 Block Diagram

38 AT43USB353M

tings for Timer/Counter1 are found in the Timer/Counter Interrupt Mask Register (TIMSK). the ICP function is shared with port D pin, PD4. monitored over 4 samples, and all 4 must be equal to activate the capture flag. Figure 12. ICP Pin Schematic Diagram

match in Timer/Counter1. Any output pin actions affect pin OC1A (Output CompareA) pin 1. set (one) to control the output pin. The control configuration is shown in Table 14.

1. In PWM mode, these bits have a different function. Refer to Table 18 for a detailed

These bits are reserved bits in the AT43USB353M and always read zero. These bits select PWM operation of Timer/Counter1 as specified in Table 15. Table 14. Compare 1 Mode Select (2) Table 15. PWM Mode Select 0 0 PWM operation of Timer/Counter1 is disabled. 0 1 Timer/Counter1 is an 8-bit PWM. 1 0 Timer/Counter1 is a 9-bit PWM. 1 1 Timer/Counter1 is a 10-bit PWM.

40 AT43USB353M

Timer/Counter1 contents are transferred to the ICR1 on the rising edge of the ICP. These bits are reserved bits in the AT43USB353M and always read zero. In PWM mode, this bit has no effect. The Clock Select1 bits 2, 1 and 0 define the prescaling source of Timer/Counter1. Table 16. Clock 1 Prescale Select 0 0 0 Stop, the Timer/Counter1 is stopped.

3307B–USB–4/04 The Stop condition provides a Timer Enable/Disable function. The CK down divided modes are scaled directly from the 12 MHz input clock. Timer/Counter1 – TCNT1H and TCNT1L This 16-bit register contains the prescaled value of the 16-bit Timer/Counter1. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary register (TEMP). This tem- porary register is also used when accessing OCR1A, OCR1B and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be dis- abled during access from the main program and from interrupt routines if interrupts are allowed from within interrupt routines.  TCNT1 Timer/Counter1 Write: When the CPU writes to the high byte TCNT1H, the written data is placed in the TEMP regis- ter. Next, when the CPU writes the low byte TCNT1L, this byte of data is combined with the byte data in the TEMP register, and all 16 bits are written to the TCNT1 Timer/Counter1 regis- ter simultaneously. Consequently, the high byte TCNT1H must be accessed first for a full 16- bit register write operation.  TCNT1 Timer/Counter1 Read: When the CPU reads the low byte TCNT1L, the data of the low byte TCNT1L is sent to the CPU and the data of the high byte TCNT1H is placed in the TEMP register. When the CPU reads the data in the high byte TCNT1H, the CPU receives the data in the TEMP register. Consequently, the low byte TCNT1L must be accessed first for a full 16-bit register read operation. The Timer/Counter1 is realized as an up or up/down (in PWM mode) counter with read and write access. If Timer/Counter1 is written to and a clock source is selected, the Timer/Counter1 continues counting in the timer clock cycle after it is preset with the written value. Bit 15 14 13 12 11 10 9 8 76 5 4 3 2 10 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 00 0 0 0 0 00

42 AT43USB353M

3307B–USB–4/04 Timer/Counter1 Output Compare Register – OCR1AH and OCR1AL Timer/Counter1 Output Compare Register – OCR1BH and OCR1BL The output compare registers ar e 16-bit read/write registers. The Timer/Counter1 Output Compare Registers contain the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Con- trol and Status register.A compare match does only occur if Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR1B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the com- pare event. Since the Output Compare Registers OCR1A and OCR1B are 16-bit registers, a temporary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the data is tempo- rarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL or OCR1BL, the TEMP register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program and from in terrupt routines if interrupts are allowed from within interrupt routines. Bit 15 14 13 12 11 10 9 8 76 5 4 3 2 10 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 00 0 0 0 0 00 B i t 1 5 1 41 31 21 1 1 0 9 8 7 6543 2 1 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W I n i t i a l V a l u e 0 0000 0 0 0 0 0000 0 0 0

The input capture register is a 16-bit read-only register. data is sent to the CPU and the data of the high byte ICR1H is placed in the TEMP register. allowed from within interrupt routines. free and phase correct PWM with outputs on the PD5 (OC1A) and OC1B pins. Table 17. Timer TOP Values and PWM Frequency

44 AT43USB353M

unsynchronized OCR1A/OCR1B write. See Figure 13 for an example. Figure 13. Effects on Unsynchronized OCR1 Latching COM1B1/COM1B0. This is shown in Table 19. Table 18. Compare1 Mode Select in PWM Mode down-counting (non-inverted PWM).

time the counter reaches the TOP value, making a one-period PWM pulse. enabled. This also applies to the Timer Output Compare1 flags and interrupts. Watchdog Timer The Watchdog Timer is clocked from a 1 MHz clock derived from the 6 MHz on chip oscillator. and executes from the reset vector. Figure 14. Watchdog Timer Table 19. PWM Outputs OCR1X = $0000 or Top

10 T O P H

11 T O P L

46 AT43USB353M

These bits are reserved bits in the AT43USB355 and will always read as zero. description of the WDE bit for a watchdog disable procedure.

1. In the same operation, write a logical one to WDTOE and WDE. A logical one must be

written to WDE even though it is set to one before the disable operation starts.

1. Within the next four clock cycles, write a logical 0 to WDE. This disables the watchdog.

Periods are shown in Table 20. abled or reset before changing the Watchdog Timer Prescale Select. Table 20. Watchdog Timer Prescale Select

conversion. A block diagram of the ADC is shown in Figure 15. The reference voltage of the ADC is internally connected to the CEXTA voltage regulator. Figure 15. Analog-to-digital Converter Block Schematic

48 AT43USB353M

selects between the two available modes. in progress, the ADC will finish the current conversion before performing the channel change. before ADCH is read, neither register is updated and the result from the conversion is lost. Then ADCH is read, ADC access to the ADCH and ADCL register is re enabled. will trigger even if the result is lost. Figure 16. ADC Prescaler

prescaler, which divides the CK of 2 MHz clock input, to an acceptable ADC clock frequency. set and is continuously reset when ADEN is low. following rising edge of the ADC clock cycle. The actual sample-and-hold takes place 1.5 ADC clock cycles after the start of a conversion. When a conversion is complete, the result is written to the ADC data registers and ADIF is set. gives the lowest conversion time with a maximum resolution, 12 µs, equivalent to 83 kSPS. For a summary of conversion times, see Table 21. Figure 17. ADC Timing Diagram, Extended Conversion (Single Conversion Mode)

50 AT43USB353M

Figure 18. ADC Timing Diagram, Single Conversion Figure 19. ADC Timing Diagram, Free Running Conversion Table 21. ADC Conversion Time

These bits are reserved bits in the AT43USB353M and always read as zero. The value of these three bits selects which analog input ADC11..0 is connected to the ADC. version is complete (ADIF in ADCSR is set). Table 22. Input Channel Selections

0000 ADC0

0001 ADC1

0010 ADC2

0011 ADC3

0100 ADC4

0101 ADC5

0110 ADC6

0111 ADC7

1000 ADC8

1001 ADC9

1010 ADC10

1011 ADC11

52 AT43USB353M

3307B–USB–4/04 ADC Control and Status Register – ADCSR B i t 7 – ADEN: ADC Enable Writing a logical “1” to this bit enables the ADC. By clearing this bit to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress will terminate this conversion. B i t 6 – ADSC: ADC Start Conversion In Single Conversion Mode, a logical “1” must be written to this bit to start each conversion. In Free Running Mode, a logical “1” must be written to this bit to start the first conversion. The first time ADSC has been written after the ADC has been enabled or if ADSC is written at the same time as the ADC is enabled, an extended conversion will precede the initiated conver- sion. This extended conversion performs initialization of the ADC. ADSC will read as one as long as a conversion is in progress. When the conversion is com- plete, it returns to zero. When a extended conversion precedes a real conversion, ADSC will stay high until the real conversion completes. Writing a “0” to this bit has no effect. B i t 5 – ADFR: ADC Free Running Select When this bit is set (one), the ADC operates in Free Running Mode. In this mode, the ADC samples and updates the data registers continuously. Clearing this bit (zero) will terminate Free Running Mode. B i t 4 – ADIF: ADC Interrupt Flag This bit is set (one) when an ADC conversion completes and the data registers are updated. The ADC Conversion Complete interrupt is executed if the ADIE bit and the I-bit in SREG are set (one). ADIF is cleared by the hardware when executing the corresponding interrupt han- dling vector. Alternatively, ADIF is cleared by writing a logical “1” to the flag. Beware that if doing a read-modify-write on ADCSR, a pending interrupt can be disabled. This also applies if the SBI and CBI instructions are used. B i t 3 – ADIE: ADC Interrupt Enable When this bit is set (one) and the I-bit in SREG is set (one), the ADC Conversion Complete interrupt is activated.  Bits 2..0 – ADPS2..ADPS0: ADC Prescaler Select Bits These bits determine the division factor between the 12 MHz system clock frequency and the input clock to the ADC. B i t 7 6543 2 1 0 $07 ($27) ADEN ADSC ADFR ADIF ADIE ADPS2 ADPS1 ADPS0 ADCSR Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0

Mode, it is essential that both registers are read, and that ADCL is read before ADCH. triggers, the next conversion has already started and the old setting is used. Table 23. ADC Prescaler Selections

54 AT43USB353M

3307B–USB–4/04 ADC Characteristics I/O-Ports All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies for changing drive value if configured as output or enabling/disabling of pull-up resistors if config- ured as input. Port A Port A is an 8-bit bi-directional I/O port. The Port A output buffers can sink or source 2 mA. Three I/O memory address locations are allocated for the Port A, one each for the Data Regis- ter PORTA, $1B($3B), Data Direction Register (DDRA), $1A($3A) and the Port A Input Pins (PINA) $19($39). The Port A Input Pins address is read only, while the Data Register and the Data Direction Register are read/write. All port pins have individually selectable pull-up resistors. When pins PA0 to PA7 are used as inputs and are externally pulled low, they will source current if the internal pull-up resistors are activated. Port A Data Register – PORTA Port A Data Direction Register – DDRA Symbol Parameter Condition Min Typ Max Units Resolution 10 Bits Integral Non-linearity V REF = VCEXT A 4 LSB Differential Non-linearity V REF = VCEXT A 4 LSB Zero Error (Offset) -2 2 LSB Full Scale Error -4 4 LSB V REF input resistance 25 °C1 2 1 8 2 4 k Ω Analog Input Resistance 100 M Ω Conversion Time 12 768 µs Clock Frequency at 50% duty cycle 1 MHz Bit 7 6 5 4 3 2 1 0 $1B ($3B) PORTA7 PORTA6 PORTA5 PORTA4 PORTA3 PORTA2 PORTA1 PORTA0 PORTA Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 B i t7 65432 1 0 $1A ($3A) DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 DDRA Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0

when reading PINA, the logical values present on the pins are read. All 8 pins in Port A have equal functionality when used as digital I/O pins. when a reset condition becomes active, even if the clock is not active. Note: n: 7,6...0, pin number. Port D Port D is a 7-bit bi-directional I/O port. Its output buffers can sink or source 2 mA. Data Direction Register are read/write. Some Port D pins have alternate functions as shown in Table 25. according to the alternate function description. Table 24. DDAn Effects on Port A Pins 0 1 Input P An will source current if ext. pulled low. Table 25. Port D Alternate Functions

56 AT43USB353M

when reading PIND, the logical values present on the pins are read. when a reset condition becomes active, even if the clock is not active. Note: n: 7, 6...0, pin number. Table 26. DDDn Bits on Port D Pins 0 1 Input PDn will source current if ext. pulled low.

3307B–USB–4/04 Programming the USB Module The USB hardware consists of two devices, hub and function, each with their own device address and end-points. Its operation is controlled through a set of memory mapped registers. The exact configuration of the USB device is defined by the software and it can be pro- grammed to operate as a compound device, or as a hub only or as a function only. The hub has the required control and interrupt end-point s. The number of external downstream ports is programmable as 1 or 2. The DP and DM pins of the unused port(s) must be connected to ground. The USB function has one control end-point and 3 programmable end-points. All the end-points have their own FIFO. Function end-points 1 and 2 FIFOs are 64 bytes deep and function end-point 3 has an 8-byte FIFO. If the hub is disabled, one extra end-point becomes available to the function. The USB Function The USB function hardware is designed to operate in the single packet mode and to manage the USB protocol layer. It consists of a Serial Interface Engine (SIE), end-point FIFOs and a Function Interface Unit (FIU). The SIE performs the following tasks: USB signaling detec- tion/generation, data serialization/de-serialization, data encoding/decoding, bit stuffing and un- stuffing, clock/data separati on, and CRC generation/checking. It also decodes and manages all packet data types and packet fields. The end-point FIFO buffers the data to be sent out or data received. The FIU manages the flow of data between the SIE, FIFO and the internal microcontroller bus. It controls the FIFO and monitors the status of the transactions and interfaces to the CPU. It initiates interrupts and acts upon commands sent by the firmware. The USB function hardware of the AT43USB353M makes the physical interface and the proto- col layer transparent to the user. To start the process, the firmware must first enable the end- points and which place them in receive mode by default. The device address by default is address 0. The USB function hardware then waits for a SETUP token from the host. When a valid the SETUP token is received, it automatically stores the DATA packet in end-point 0 FIFO and responds with an ACK. It then notifies the microcontroller through an interrupt. The microcontroller reads the FIFO and parses the request. Transactions for the non-control end-points are even simpler. Once the end-point is enabled, it waits for an IN or an OUT token depending whether it is programmed as an IN or OUT end- point. For example, if it is an IN end-point, the microcontroller simply loads the data into the end-point's FIFO and sets a bit in the control and status register. The USB hardware will assemble the data in a USB packet and waits for an IN token. When it receives one, it auto- matically responds by transmitting the DATA packet and completes the transaction by waiting for the host's ACK. When one is received, the USB hardware will signal the microcontroller that the transaction has been completed successfully. Retries and data toggles are performed automatically by the USB hardware. When the IN end-point is not ready to send data, in the case where the microcontroller has not filled the FIFO, it will automatically respond with a NAK. Similarly, an OUT end-point will wait for an OUT token. When one is received, it will store the data in the FIFO, completes the transaction and interrupt the microcontroller, which then reads the FIFO and enables the end-point for the next packet. If the FIFO is not cleared, the USB hardware will responds with a NAK. A detailed description of how USB transactions are handled is described in the following sec- tions. First for a control end-point and then for non-control end-points.

58 AT43USB353M

3307B–USB–4/04 Control Transfers at Control End-point EP0 The description given below is for the function control end-point, but applies to the hub control end-point as well if the proper registers are used. The following illustration describes the three possible types of control transfers – Control Write, Control Read and No-data control: The following state diagram shows how the various state transitions are triggered. Additional decision making may take place within the response states to determine the next expected state. Unmarked arcs represent transitions that trigger immediately following completion of the response state processing. Stable states, those requiring an interrupt to exit having no unmarked arcs as exit paths, are shown in bold. Setup Data Status Stage Stage Stage Control Write DATA0 DATA1 DATA0 DATA0/1 DATA1(0) Control Read DATA0 DATA1 DATA0 DATA0/1 DATA1(0) Setup Status Stage Stage No-data Control DATA0 DATA1(0) SETUP(0) SETUP(0) OUT(1) OUT(0) OUT(0/1)… IN(1)IN(1) SETUP(0) IN(1) IN(1) OUT(1)IN(0) IN(0/1)… Legend: DATAn Data packet with PID’s data toggle bit equal to n DATA1(0) Zero length DATA1 packet Idle Setup Response No-data Status Response Control Read Status Response Control Write Status Response RX_SETUP_INT RX_OUT_INT TX_COMPLETE_INT TX_COMPLETE_INT TX_COMPLETE_INT RX_OUT_INT Control Read Data Response TX_COMPLETE_INT Control Write Data ResponseRX_OUT_INT (ANY STABLE STATE)

3307B–USB–4/04 The following information describes how the AT43USB355’s USB hardware and firmware operates during a control transfer between the host and the hub’s or function’s control end- point. Idle State This is the default state from power-up. Setup Response State The Function Interface Unit (FIU) receives a SETUP token with 8 bytes of data from the Host. The FIU stores the data in the FIFO, sends an ACK back to the host and asserts an RX_SETUP interrupt. Legend: DA TA1/DA T A0 = DA T A packet with DA T A1 or DA TA2 PID DA TA1(0) = Zero length DAT A1 packet Hardware Firmware 1. SETUP token, DATA from Host 2. ACK to Host 3. Store data in FIFO 4. Set RX SETUP → INT 5. Read UISR 6. Read CSR0 7. Read Byte Count 8. Read FIFO 9. Parse command data 10. Write to H/FCAR0: a. If Control Read: set DIR, clear RX SETUP , fill FIFO, set TX Packet Ready in CAR0 b. If Control Write: clear DIR in CAR0 c. If no Data Stage: set Data End, clear DIR, set Force STALL in CAR0 11. Set UIAR[EP0 INTACK] to clear the interrupt source

60 AT43USB353M

3307B–USB–4/04 No-data Status Response State The Function Interface Unit receives an IN token from the Host. The FIU responds with a zero length DATA1 packet until receiving an ACK from the host, then asserts a TX_COMPLETE interrupt. Control Read Data Response State The Function Interface Unit receives an IN token from the Host. The FIU responds with NAKs until TX_PACKET_READY is set. The FIU then sends the data in the FIFO upstream, retrying until it successfully receives an ACK from the host. Finally, the FIU clears the TX_PACKET_READY bit and asserts a TX_COMPLETE interrupt. Hardware Firmware 1. IN token from Host 2. Send DATA1(0) 3. ACK from Host 4. Set TX COMPLETE → INT 5. Read UISR 6. Read CSR0 7. If SET ADDRESS, program the new Address, set ADD_EN bit 8. Clear TX_COMPLETE, clear Data End, set Force STALL in CAR0 9. Set UIAR[EP0 INT ACK] Hardware Firmware 1. IN token from Host 2. a. If TX Packet Ready = 1, send DATA0/DATA1 b. If TX Packet Ready = 0, send NAK 3. ACK from Host 4. Clear TX Packet Ready Set TX Complete → INT 5. Read UISR 6. Read CSR0 7. Clear TX COMPLETE in CAR0: a. If more data: fill FIFO, set TX Packet Ready, set DIR in CAR0 b. If no more data: set Force STALL, set DAT A END in CAR0 8. Set UIAR[EP0 INTACK] to clear interrupt source Repeat steps 1 through 8

3307B–USB–4/04 Control Read Status Response State The Function Interface Unit receives an OUT token from the Host with a zero length DATA1 packet. The FIU responds with a NAK until TX_COMPLETE is cleared. The FIU will then ACK the retried OUT token from the Host and assert an RX_OUT interrupt. Control Write Data Response State The Function Interface Unit receives an OUT token from the Host with a DATA packet. The FIU places the incoming data into the FIFO, issues an ACK to the host, and asserts an RX_OUT interrupt. Hardware Firmware 1. OUT token from Host 2. DA TA1(0) from Host 3. TX Complete = 0 ? a. If yes, ACK to Host Set RX OUT → INT b. If no, NAK to Host 4. Read UISR 5. Read CSR0 6. Clear RX OUT, set Data End, set Force Stall in H/FCAR0. Note: A SETUP token will clear Data End, therefore, it is not cleared by FW in case Host retries. 7. Set UIAR[EP0 INTACK] to clear interrupt source Hardware Firmware 1. OUT token from Host 2. Put DATA0/DATA1 into FIFO 3. ACK to Host 4. Set RX OUT → INT 5. Read UISR 6. Read CSR0 7. Read FIFO 8. Clear RX OUT If last DAT A packet, set Force STALL, set DA TA END. 9. Set UIAR[EP0 INTACK] to clear the interrupt source Repeat steps 1 through 9 until last DAT A Packet:

62 AT43USB353M

3307B–USB–4/04 Control Write Status Response State The Function Interface Unit receives an IN token from the Host. The FIU responds with a zero length DATA1 packet, retrying until it receives an ACK back from the Host. The FIU then asserts a TX_COMPLETE interrupt. Hardware Firmware 1. IN token from Host 2. Send DATA1(0) 3. ACK from Host 4. Set TX Complete → INT 5. Read UISR 6. Read CSR0 7. Clear TX COMPLETE, clear Data End, set Force STALL in CAR0 8. Set UIAR[EP0 INTACK] to clear the interrupt source

3307B–USB–4/04 Interrupt/Bulk IN Transfers at Function End-point The firmware must first condition the end-point through the End-point Control Register, FEND- P1/2/3_CNTR: Set end-point direction: set EPDIR Set interrupt or bulk: EPTYPE = 11 or 10 Enable end-point: set EPEN The Function Interface Unit receives an IN token from the Host. The FIU responds with NAKs until TX_PACKET_READY is set. The FIU then sends the data in the FIFO upstream, retrying until it successfully receives an ACK from the host. Finally, the FIU clears the TX_PACKET_READY bit and asserts a TX_COMPLETE interrupt. 1. Read UISR 2. Read FCSR1/2/3 3. Clear TX_COMPLETE If more data: fill FIFO, set TX Packet Ready Wait for TX_COMPLETE interrupt If no more data: set DATA END in FCAR1/2/3 4. Set UIAR[FEP1/2/3 INTACK] to clear the interrupt source Interrupt/Bulk OUT Transfers at Function End-point EP1, 2 and 3 The firmware must first condition the end-point through the End-point Control Register, FEND- P1/2/3_CNTR: Set end-point direction: clear EPDIR Set interrupt or bulk: EPTYPE = 11 or 10 Enable end-point: set EPEN The Function Interface Unit receives an OUT token from the Host with a DATA packet. The FIU places the incoming data into the FIFO, issues an ACK to the host, and asserts an RX_OUT interrupt. 1. Read UISR 2. Read FCSR1/2/3 3. Read FIFO 4. Clear RX_OUT If more data: Wait for RX_OUT interrupt If no more data: set DATA END 5. Set UIAR[FEP1/2/3 INTACK] to clear the interrupt source

64 AT43USB353M

3307B–USB–4/04 USB Registers The following sections describe the registers of the AT43USB353M’s USB hub and function units. Reading a bit for which the microcontroller does not have read access will yield a zero value result. Writing to a bit for which the microcontroller does not have write access has no effect. Hub Address Register – HADDR The USB hub contains an address register that contains the hub address assigned by the host. This Hub Address Register must be programmed by the microcontroller once it has received a SET_ADDRESS re quest from the host. The USB hardware uses the new address only after the status phase of the transaction is completed when the microcontroller has enabled the new address by setting bit 0 of the Global State Register. After power-up or reset, this register will contain the value of 0x00. Hub Address Register – HADDR  Bit 7 – SAEN: Single Address Enable The Single Address Enable bit allows the microcontroller to configure the AT43USB353M into a single address or a composite device. Once this capability is enabled, the Hub End-point 0 (HEP0) is converted from a control end-point to a programmable function end-point FEP3; all the end-points would then operate on the single address. Function Address Register – FADDR The USB function contains an address register that contains the function address assigned by the host. This Function Address Register must be programmed by the microcontroller once it has received a SET_ADDRESS request from the host and completed the status phase of the transaction. After power up or reset, this register will contain the value of 0x00. Function Address Register – FADDR  Bit 7 – FEN: Function Enable The Function Enable bit (FEN) allows the firmware to enable or disable the function end- points. The firmware will set this bit after receipt of a reset through the hub, SetPortFea- ture[PORT_RESET]. Once this bit is set, the USB hardware passes to and from the host. When the Single Address bit is set, the condition of FEN is ignored. B i t7 6543 2 1 0 $1FEF SAEN HADD6 HADD5 HADD4 HADD3 HADD2 HADD1 HADD0 HADDR Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 B i t7 6543 2 1 0 $1FEE FEN FADD6 FADD5 FADD4 FADD3 FADD2 FADD1 FADD0 FADDR Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0

3307B–USB–4/04 End-point Registers Hub End-point 0 Control Register – HEND-P0_CR Function End-point 0 Control Register – FEND-P0_CR  Bit 7 – EPEN: End-point Enable 0 = Disable end-point 1 = Enable end-point  Bit 6..4 – Reserved These bits are reserved in the AT43USB353M and will read as zero.  Bit 3 – DTGLE: Data Toggle Identifies DATA0 or DATA1 packets. This bit will automatically toggle and requires clearing by the firmware only in certain special circumstances.  Bit 2 – EPDIR: End-point Direction 0 = Out 1 = In  Bit 1, 0 – EPTYPE: End-point Type These bits must be programmed as 0, 0. Function End-point 1..3 Control Register – FEND-P1..3_CR  Bit 7 – EPEN: End-point Enable 0 = Disable end-point 1 = Enable end-point  Bit 6..4 – Reserved These bits are reserved in the AT43USB353M and will read as zero.  Bit 3 – DTGLE: Data Toggle B i t 7 65432 1 0 $1FE7 EPEN – – – DTGLE EPDIR EPTYPE1 EPTYPE0 HEND-P0_CR $24 ($44) EPEN – – – DTGLE EPDIR EPTYPE1 EPTYPE0 FEND-P0_CR Read/Write R/W R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 B i t 7654 3 2 1 0 $1FE4 EPEN – – – DTGLE EPDIR EPTYPE1 EPTYPE0 FEND- P1_CR $1FE3 EPEN – – – DTGLE EPDIR EPTYPE1 EPTYPE0 FEND- P2_CR $1FE2 DTGLE EPDIR EPTYPE1 EPTYPE0 FEND- P3_CR Read/Write R/W R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0

66 AT43USB353M

3307B–USB–4/04 Identifies DATA0 or DATA1 packets. This bit will automatically toggle and requires clearing by the firmware only in certain special circumstances.  Bit 2 – EPDIR: End-point Direction 0 = Out 1 = In  Bit 1, 0 – EPTYPE: End-point Type These bits programs the type of end-point. Hub End-point 0 Data Register – HDR0 Function End-point 0..3 Data Register – FDR0..3 This register is used to read data from or to write data to the Hub End-point 0 FIFO.  Bit 7..0 – FDAT7..0: FIFO Data Hub End-point 1 has a single byte data register instead of a FIFO. This data register contains the hub and port status change bitmap. This data register is automatically updated by the USB hardware and is not accessible by the firmware. The bits in this register when read by the host will be:  Bit 7...4 – Reserved These bits are reserved in the AT43USB353M and will read as zero.  Bit 3 – P3 SC: Port 3 Status Change  Bit 2 – P2 SC: Port 2 Status Change  Bit 1 – P1 SC: Port 1 Status Change  Bit 0 – H SC: Hub Status Change Bit1 Bit0 Type 0 1 Isochronous

10 B u l k

$1FD7 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 HDR0 $1FD5 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 FDR0 $1FD4 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 FDR1 $1FD3 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 FDR2 $1FD2 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 FDR3 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 $ – – – – P3 SC P2 SC P1 SC H SC HDR1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0

3307B–USB–4/04 Hub End-point 0 Byte Count Register – HBYTE_CNT0 Function End-point 0..3 Byte Count Register – FBYTE_CNT0..3 The contents of these registers stores the number of bytes to be sent or that was received by USB Hub and Function end-points. This count in cludes the 16-bit CRC. To get the actual byte count of the data, subtract the count in the register by 2. The hub EP0 and function EP3 have 8 byte FIFOs while function EP1 and EP2 have 64 byte FIFOs. Hub End-point 1 has no byte count register.  Bit 7..6 – Reserved These bits are reserved in the AT43USB353M and will read as zero.  Bit 5..0 – BYTCT5..0: Byte Count – Length of End-point DATA Packet B i t 7 654321 0 Hub EP0 $1FCF – – BYTCT5 BYTCT4 BYTCT3 BYTCT2 BYTCT1 BYTCT0 HBYTE_CNT0 Function EP0 $1FCD – – BYTCT5 BYTCT4 BYTCT3 BYTCT2 BYTCT1 BYTCT0 FBYTE_CNT0 Function EP1 $1FCC – BYTCT6 BYTCT5 BYTCT4 BYTCT3 BYTCT2 BYTCT1 BYTCT0 FBYTE_CNT1 Function EP2 $1FCB – BYTCT6 BYTCT5 BYTCT4 BYTCT3 BYTCT2 BYTCT1 BYTCT0 FBYTE_CNT2 Function EP3 $1FCA – – BYTCT5 BYTCT4 BYTCT3 BYTCT2 BYTCT1 BYTCT0 FBYTE_CNT3 Read/Write R R R R/W R/W R/W R/W R/W I n i t i a l V a l u e 0 000000 0

68 AT43USB353M

3307B–USB–4/04 Hub End-point 0 Service Routine Register – HCSR0 Function End-point 0 Service Routine Register – FCSR0  Bit 7..4 – Reserved These bits are reserved in the AT43USB353M and will read as zero.  Bit 3 – STALL SENT The USB hardware sets this bit after a STALL has been sent to the host. The firmware uses this bit when responding to a Get Status[End-point] request. It is a read only bit and that is cleared indirectly by writing a one to the STALL_SENT_ACK bit of the Control and Acknowl- edge Register.  Bit 2 – RX SETUP: Setup Packet Received This bit is used by control end-points only to signal to the microcontroller that the USB hard- ware has received a valid SETUP packet and that the data portion of the packet is stored in the FIFO. The hardware will clear all other bits in this register while setting RX SETUP. If inter- rupt is enabled, the microcontroller will be interrupted when RX SETUP is set. After the completion of reading the data from the FIFO, firmware should clear this bit by writing a one to the RX_SETUP_ACK bit of the Control and Acknowledge Register.  Bit 1 – RX OUT PACKET The USB hardware sets this bit after it has stored the data of an OUT transaction in the FIFO. While this bit is set, the hardware will NAK all OUT tokens. The USB hardware will not over- write the data in the FIFO except for an early set-up. RX OUT Packet is used for the following operations: 1. Control write transactions by a control end-point. 2. OUT transaction with DA TA1 PID to complete the status phase of a control end-point. Setting this bit causes an interrupt to the microcontroller if the interrupt is enabled. FW clears this bit after the FIFO contents have been read by writing a one to the RX_OUT_PACKET_ACK bit of the Control and Acknowledge Register.  Bit 0 – TX COMPL: Transmit Completed This bit is used by a control end-point hardware to signal to the microcontroller that it has suc- cessfully completed certain transactions. TX Complete is set at the completion of a: 1. Control read data stage. 2. Status stage without data stage. 3. Status stage after a control write transaction. This bit is read only and is cleared indirectly by writing a one to the TX_COMPLETE_ACK bit of the Control and Acknowledge Register. B i t 7654 3 2 1 0 Function EP0 $1FDF – – – – STALL SENT RX SETUP RX OUT PACKET TX COMPLETE HCSR0 Function EP0 $1FDD – – – – STALL SENT RX SETUP RX OUT PACKET TX COMPLETE FCSR0 Read/Write R R R R R R R R Initial Value 0 0 0 0 0 0 0 0

3307B–USB–4/04 Hub End-point 0 Control and Acknowledge Register – HCAR0 Function End-point 0 Control and Acknowledge Register – FCAR0 B i t 7 – DIR: Control transfer direction It is set by the microcontroller firmware to indicate the direction of a control transfer to the USB hardware. The FW writes to this bit location after it receives an RX SETUP interrupt. The hard- ware uses this bit to determine the status phase of a control transfer. 0 = control write or no data stage 1 = control read B i t 6 – DATA END When set to 1 by firmware, this bit indicate that the microcontroller has either placed the last DATA packet in FIFO, or that the microcontroller has processed the last DATA packet it expects from the Host. This bit is used by control end-points only together with bit 4 (TX Packet Ready) to signal the USB hardware to go to the STATUS phase after the packet cur- rently residing in the FIFO is transmitted. After the hardware completes the STATUS phase it will interrupt the microcontroller without clearing this bit. B i t 5 – FORCE STALL This bit is set by the microcontroller to indicate a stalled end-point. The hardware will send a STALL handshake as a response to the next IN or OUT token, or whenever there is a control transfer without a Data Stage. The microcontroller sets this bit if it wants to force a STALL. A STALL is sent if any of the fol- lowing condition is encountered: 1. An unsupported request is received. 2. The host continues to ask for data after the data is exhausted. 3. The control transfer has no data stage. B i t 4 – TX PACKET READY: Transmit Packet Ready When set by the firmware, this bit indicates that the microcontroller has loaded the FIFO with a packet of data. This bit is cleared by the hardware after the USB Host acknowledges the packet. For ISO end-points, this bit is cleared unconditionally after the data is sent. This bit is used for the following operations: 1. Control read transactions by a control end-point. 2. IN transactions with DATA1 PID to complete the status phase for a control end-point, when this bit is zero but Data End set high (bit 4). 3. By a BULK IN or ISO IN or INT IN end-point. The microcontroller should write into the FIFO only if this bit is cleared. After it has completed writing the data, it should set this bit. This data can be of zero length. Bit 7 6 5 4 3 2 1 0 Hub EP0 $1FA7 DIR DATA END FORCE STALL TX PACKET READY STALL_ SENT_ ACK RX_ SETUP_ ACK RX_OUT_ PACKET_ ACK TX_ COMPLETE_ ACK HCAR0 Function EP0 $1FDD DIR DATA END FORCE STALL TX PACKET READY STALL_ SENT_ ACK RX_ SETUP_ ACK RX_OUT_ PACKET_ ACK TX_ COMPLETE_ ACK FCAR0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0

70 AT43USB353M

3307B–USB–4/04 Hardware clears this bit after it receives an ACK. If the interrupt is enabled and if the TX Com- plete bit is set, clearing the TX Packet Ready bit by the hardware causes an interrupt to the microcontroller. B i t 3 – STALL_SENT_ACK: Acknowledge Stall Sent Interrupt Firmware sets this bit to clear STALL SENT, CSR bit 3. The 1 written in the CSRACK3 bit is not actually stored and thus does not have to be cleared. B i t 2 – RX_SETUP_ACK: Acknowledge RX SETUP Interrupt Firmware sets this bit to clear RX SETUP, CSR bit2. The 1 written in the CSRACK2 bit is not actually stored and thus does not have to be cleared. B i t 1 – RX_OUT_PACKET_ACK: Acknowledge RX OUT PACKET Interrupt Firmware sets this bit to clear RX OUT PACKET, CSR bit1. The 1 written in the CSRACK1 bit is not actually stored and thus does not have to be cleared. B i t 0 – TX_COMPLETE_ACK: Acknowledge TX COMPLETE Interrupt Firmware sets this bit to clear TX COMPLETE, CSR bit0. The 1 written in the CSRACK0 bit is not actually stored and thus does not have to be cleared. Function End-point 0..3 Service Routine Register – FCSR0..3  Bit 7..4 – Reserved These bits are reserved in the AT43USB353M and will read as zero.  Bit 3 – STALL SENT The USB hardware sets this bit after a STALL has been sent to the host. The firmware uses this bit when responding to a Get Status[End-point] request. It is a read only bit and that is cleared indirectly by writing a one to the STALL_SENT_ACK bit of the Control and Acknowl- edge Register.  Bit 2 – Reserved This bit is reserved in the AT43USB353M and will read as zero.  Bit 1 – RX OUT PACKET The USB hardware sets this bit after it has stored the data of an OUT transaction in the FIFO. While this bit is set, the hardware will NAK all OUT tokens. The USB hardware will not over- write the data in the FIFO except for an early set-up. RX OUT Packet is used by a BULK OUT or ISO OUT or INT OUT end-point. Setting this bit causes an interrupt to the microcontroller if the interrupt is enabled. FW clears this bit after the FIFO contents have been read by writing a one to the RX_SETUP_ACK bit of the Control and Acknowledge Register.  Bit 0 – TX COMPLETE: Transmit Completed This bit is used by the end-point hardware to signal to the microcontroller that the IN transac- tion was completed successfully. This bit is read only and is cleared indirectly by writing a one to the TX_COMPLETE_ACK bit of the Control and Acknowledge Register. B i t 7 6 5 432 1 0 Function EP1 $1FDC – – – – STALL SENT – RX OUT PACKET TX COMPLETE FCSR1 Function EP2 $1FDB – – – – STALL SENT – RX OUT PACKET TX COMPLETE FCSR2 Function EP3 $1FDA – – – – STALL SENT – RX OUT PACKET TX COMPLETE FCSR3 Read/Write R R R R R R R R Initial Value 0 0 0 0 0 0 0 0

3307B–USB–4/04 Function End-point 0..3 Control and Acknowledge Register – FCAR0..3  Bit 7 – Reserved This bit is reserved in the AT43USB353M and will read as zero.  Bit 6 – DATA END When set to 1 by firmware, this bit indicate that the microcontroller has either placed the last DATA packet in FIFO, or that the microcontroller has processed the last DATA packet it expects from the Host.  Bit 5 – FORCE STALL This bit is set by the microcontroller to indicate a stalled end-point. The hardware will send a STALL handshake as a response to the next IN or OUT token. The microcontroller sets this bit if it wants to force a STALL. A STALL is send if the host continues to ask for data after the data is exhausted.  Bit 4 – TX PACKET RDY: Transmit Packet Ready When set by the firmware, this bit indicates that the microcontroller has loaded the FIFO with a packet of data. This bit is cleared by the hardware after the USB Host acknowledges the packet. For ISO end-points, this bit is cleared unconditionally after the data is sent. The microcontroller should write into the FIFO only if this bit is cleared. After it has completed writing the data, it should set this bit. This data can be of zero length. The hardware clears this bit after it receives an ACK. If the interrupt is enabled and if the TX Complete bit is set, clearing the TX Packet Ready bit by the hardware causes an interrupt to the microcontroller.  Bit 3 – STALL_SENT_ACK: Acknowledge Stall Sent Interrupt Firmware sets this bit to clear STALL SENT, CSR bit 3. The 1 written in the CSRACK3 bit is not actually stored and thus does not have to be cleared.  Bit 2 – Reserved This bit is reserved in the AT43USB353M and will read as zero.  Bit 1 – RX_OUT_PACKET_ACK: Acknowledge RX OUT PACKET Interrupt Firmware sets this bit to clear RX OUT PACKET, CSR bit1. The 1 written in the CSRACK1 bit is not actually stored and thus does not have to be cleared.  Bit 0 – TX_COMPLETE_ACK: Acknowledge TX COMPLETE Interrupt Firmware sets this bit to clear TX COMPLETE, CSR bit0. The 1 written in the CSRACK0 bit is not actually stored and thus does not have to be cleared. Bit 7 6 5 4 3 2 1 0 Function EP1 $1FA4 – DAT A END FORCE STALL TX PACKET RDY STALL_SENT -ACK – RX_OUT_PACKET_ ACK TX_COMPLETE_ ACK FCAR1 Function EP2 $1FA3 – DAT A END FORCE STALL TX PACKET RDY STALL_SENT -ACK – RX_OUT_PACKET_ ACK TX_COMPLETE- ACK FCAR2 Function EP3 $1FA2 – DAT A END FORCE STALL TX PACKET RDY STALL_SENT -ACK – RX_OUT_PACKET_ ACK TX_COMPLETE- ACK FCAR3 Read/Write R R/W R/W R/W R/W R R/W R/W Initial Value 0 0 0 0 0 0 0 0

72 AT43USB353M

3307B–USB–4/04 USB Hub The hub in a USB system provides for the electrical interface between USB devices and the host. The major functions that the hub must supports are:  Connectivity  Power management  Device connect and disconnect  Bus fault detection and recovery  Full speed and low speed device support A hub consists of two major components: a hub repeater and a hub controller. The hub repeater is responsible for:  Providing upstream connectivity between the selected device and the Host  Managing connectivity setup and tear-down  Handling bus fault detection and recovery  Detecting connect/disconnect on each port The Hub Controller is responsible for:  Hub enumeration  Providing configuration information to the host  Providing status of each port to the host  Controlling each port per host command The first two tasks of the Hub Controller are similar to that of a USB function and will not be described in detail in the following section. The descriptions will cover the features of the AT43USB353M's hub and how to program it to make a USB-compliant hub. Control transactions for the Hub Control End-point proceed exactly the same way as those described for the embedded function. The operation of the Hub's End-point 1 is fully imple- mented in the hardware and does not need any firmware support. Any status changes within the hub will automatically update Hub End-point 1, which will be sent to the host at the next IN token that is addressed to it. If no change has occurred, the interrupt end-point will respond with a NAK.

3307B–USB–4/04 Hub General Registers Global State Register – GLB_STATE  Bit 7...5 – Reserved Bits These bits are reserved in the AT43USB353M and will read as zeros. B i t 4 – SUSP FLG: Suspend Flag This bit is set to 1 while the USB hardware is in the suspended state. This bit is a firmware read only bit. It is set and cleared by the USB hardware. B i t 3 – RESUME FLGL Resume Flag When the USB hardware receives a resume signal from the upstream device it sets this bit. This bit will stay set until the USB hardware completes the downstream resume signaling. This bit is a firmware read only bit. It is set and cleared by the USB hardware. B i t 2 – RMWUPE: Remote Wakeup Enable This bit is set if the host enables the hub's remote wakeup feature. B i t 1 – CONFG: Configured This bit is set by firmware after a valid SET_CONFIGURATION request is received. It is cleared by a reset or by a SET_CONFIGURATION with a value of 0. B i t 0 – HADD EN: Hub Address Enabled This bit is set by firmware after the status phase of a SET_ADDRESS request transaction so the hub will use the new address starting at the next transaction. Bit 7 6 5 4 3 2 1 0 $1FFB – – – SUSP FLG RESUME FLG RMWUPE CONFG HADD EN GLB_STATE Read/Write R R R R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0

74 AT43USB353M

3307B–USB–4/04 Hub Status Register In the AT43USB353M overcurrent detection and port power switch control output processing is done in firmware. The hardware is designed so that various types of hubs are possible just through firmware modifications. 1. Hub local power status, bits 0 and 2, are optional features and apply to hubs that report on a global basis. If this feature is not used, both these bits should be programmed to 0. To use this feature, the firmware needs to know the status of the local power supply, which requires an input pin and extra internal or external circuitry. 2. Hub overcurrent status, bits 1 and 3, apply to self powered hubs with bus powered SIE only, or hubs that are programmable as self/bus powered. The firmware should clear these two bits to 0. The firmware uses bits 1 and 3 to generate bit 0 of the Hub and Port Status Change Bitmap which is transmitted through the Hub End-point1 Data Register. Bit 0 of this register is a 1 whenever bit 1 or 3 of HSTATR is a 1. Hub Status Register – HSTR  Bit 7..4 – Reserved These bits are reserved in the AT43USB355 and w ill read as zero.  Bit 3 – OVLSC: Overcurrent Status Change 0 = No change has occurred on Overcurrent Indicator 1 = Overcurrent Indicator has changed  Bit 2 – LPSC: Hub Local Power Status Change 0 = No change has occurred on Local Power Status 1 = Local Power Status has changed  Bit 1 – OVI: Overcurrent Indicator 0 = All power operations normal 1 = An overcurrent exist on a hub wide basis  Bit 0 – LPS: Hub Local Power Status 0 = Local power supply is good 1 = Local power supply is lost (inactive) B i t 7 6543 2 1 0 $1FC7 – – – – OVLSC LPSC OVI LPS HSTR Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0

3307B–USB–4/04 Hub Port Control Register – HPCON B i t 7 – Reserved This bits is reserved in the AT43USB353M and will read as zero.  Bit 6..4 – HPCON2..0: Hub Port Control Command These bits are written by firmware to control the port states upon receipt of a Host request. Disable Port = ClearPortFeature(PORT_ENABLE) Action: USB hardware places addressed port in disabled state. Port 1 is placed in disabled state by firmware. Enable Port = SetPort Feature(PORT_ENABLE) Action: USB hardware places addressed port in enabled state. Firmware is responsible for placing Port 1 in enabled state. Reset and Enable Port = SetPort Feature(PORT_RESET) Action: USB hardware drives reset signaling through addressed port. USB hardware and firmware resets their embedded function registers to the default state. Suspend Port = SetPortFeature(PORT_SUSPEND) Action: USB hardware places port in idle state and stops propagating traffic through the addressed port. Firmware places Port 1 in suspend state by disabling its end-points and plac- ing the peripheral function in its low power state. Resume Port = ClearPortFeature(PORT_SUSPEND) Action: USB hardware sends resume signaling to addressed port and then enables port. Firmware takes the embedded function out of the suspend state and enables Port 1's end- points. B i t 3 – Reserved This bits is reserved in the AT43USB353M and will read as zero.  Bit 2..0 – HPCON2..0: Hub Port Address B i t 7 654 3 2 10 $1FC5 – HPCON2 HPCON1 HPCON0 – HPADD2 HPADD1 HPADD0 HPCON Read/Write R R/W R/W R/W R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit6 Bit5 Bit4 Action 0 0 0 Disable port 0 0 1 Enable port 0 1 0 Reset and enable port 0 1 1 Suspend port 1 0 0 Resume port

76 AT43USB353M

3307B–USB–4/04 These bits define which port is being addressed for the command defined by bits [2:0]. Selective Suspend and Resume The host can selectively suspend and resume a port through the Set Port Feature (PORT_SUSPEND) and Clear Port Feature (PORT_SUSPEND). A port enters the suspend state after the microcontroller interprets the suspend request and sets the appropriate bits of the Hub Port Control Register, HPCON. From this point on he hub repeater hardware is responsible for proper actions in placing Ports 2:3 in the suspend mode. For Port 1, the embedded function port, the hardware will stop responding to any normal bus traffic, but the microcontroller firmware must place all external circuitry associated with the function in the low-power state. A port exits from the suspend state when the hub receives a Clear Port Feature (PORT_SUSPEND) or Set Port Feature (PORT_RESET). If the Clear Port Feature (PORT_SUSPEND) is directed towards Ports 2:3, the USB hardware drives a “K” downstream for at least 20 ms followed by a low speed EOP. It then places the port in the enabled state. A Clear Port Feature (PORT_SUSPEND) to Port 1 (the embedded function) causes the firmware to wait 20 ms, take the embedded function out of the suspended state and then enable the port. The ports can also exit from the suspended state through a remote wakeup if this feature is enabled. For Ports 2:3, this means detection of a connect/disconnect or an upstream directed J to K signaling. Remote wakeup for the embedded function is initiated through an external interrupt at INT0. Bit2 Bit1 Bit0 Port addresses

011 P o r t 3

010 P o r t 2

3307B–USB–4/04 Hub Port Status Register The bits in this register are used by the microcontroller firmware when reporting a port's status through the Port Status Field, wPortStatus . Bits 3 (POCI) and 5 (PPSTAT) are used by the USB hardware and are the only two bits that the firmware should set or clear. All other bits should not be modified by the firmware. Hub Port Status Register – HPSTAT2, 3  Bit 7 – Reserved This bit is reserved in the AT43USB353M and will read as zero.  Bit 6 – LSP: Low-speed Device Attached 0 = Full-speed device attached to this port 1 = Slow-speed device attached to this port Set to 0 for Port 1 (full-speed only). Set and cleared by the hardware upon detection of device at EOF2.  Bit 5 – PPSTAT: Port Power Status 0 = Port is powered OFF 1 = Port is powered ON Set to 1 for Port 1. Set and cleared based on present status of port power.  Bit 4 – PRSTAT: Port Reset Status 0 = Reset signaling not asserted 1 = Reset signaling asserted Set and cleared by the hardware as a result of initiating a port reset by Port Control Register.  Bit 3 – POCI: Port Overcurrent Indicator 0 = Power normal 1 = Overcurrent exist on port Set to 0 for Port 1. Set and cleared by firmware upon detection of an overcurrent or removal of an overcurrent.  Bit 2 – PSSTAT: Port Suspend Status 0 = Port not suspended 1 = Port suspended Set and cleared by the hardware as controlled through Port Control Register.  Bit 1 – PESTAT: Port Enable Status 0 = Port is disabled 1 = Port is enabled Set and cleared by the hardware as controlled through Port Control register. Bit 7 6 5 4 3 2 1 0 Port1 $1FB8 – LSP PPSTAT PRSTAT POCI PSSTAT PESTAT PCSTAT HPSTAT1 Port2 $1FB9 – LSP PPSTAT PRSTAT POCI PSSTAT PESTAT PCSTAT HPSTAT2 Port3 $1FBA – LSP PPSTAT PRSTAT POCI PSSTAT PESTAT PCSTAT HPSTAT3 Read/Write R R R/W R R/W R R R Initial Value 0 0 0 0 0 0 0 0

78 AT43USB353M

3307B–USB–4/04  Bit 0 – PCSTAT: Port Connect Status 0 = No device on this port 1 = Device present on this port Set to 1 for Port 1. Set and cleared by the hardware after sampling of connect status at EOF2. Overcurrent Detect Register – UOVCER Bits 3, 2 in this register enable overcurrent detection while the hub is in the suspend state.  Bit 7..4 – Reserved These bits are reserved in the AT43USB353M and will read as zero. B i t 3 – OVC3 Setting this bit enables the hub to detect an overcurrent on a port while the hub is in the sus- pend state. The overcurrent condition is signaled by a 1 to 0 transition at PD1. B i t 2 – OVC2 Setting this bit enables the hub to detect an overcurrent on a port while the hub is in the sus- pend state. The overcurrent condition is signaled by a 1 to 0 transition at PD0.  Bit 1..0 – Reserved These bits are reserved in the AT43USB353M and will read as zero. Hub Port State Register – HPSTAT2, 3 These registers contain the state of the ports’ DP and DM pins, which will be sent to the host upon receipt of a GetBusState request.  Bit 7..2 – Reserved These bits are reserved in the AT43USB353M and will read as zero. B i t 1 – DPSTATE: DPlus State Value of DP at last EOF. Set and cleared by hardware at EOF2. Set to 1 for Port 1. B i t 0 – DMSTATE: DMinus State Value of DM at last EOF. Set and cleared by hardware at EOF2. Set to 0 for Port 1. Bit 7 6543 2 1 0 Read/Write R R R R R/W R/W R R Initial Value 0 0 0 0 0 0 0 0 B i t 7 6543 2 1 0 Port2 $1FA9 – – – – – – DPSTATE DMSTATE PSTATE2 Port3 $1FAA – – – – – – DPSTATE DMSTATE PSTATE3 Read/Write R R R R R R R R Initial Value 0 0 0 0 0 0 0 0

3307B–USB–4/04 Hub Port Status Change Register – PSCR1..3 The microcontroller firmware uses the bits in this register to monitor when a port status change has occurred, which then gets reported to the host through the Port Change Field wPortChange. Except for bit 3, the Port Overcurrent Indicator Change, the bits in this register are set by the USB hardware. Otherwise, the firmware should only clear these bits.  Bit 7..5 – Reserved These bits are reserved in the AT43USB353M and will read as zero.  Bit 4 – RSTSC: Port Reset Status Change 0 = No change 1 = Reset complete This bit is set by the USB hardware after it completes RESET signaling which is initiated when the Reset and Enable Port command is detected at the Port Control Register, HPCON. The firmware sends this command when it decodes a SetPortFeature(PORT_RESET) request from the host. At EOF2 after the hardware completes the port reset, the hardware sets the Port Enable Sta- tus bit and clears the Port Reset Status bit of the Hub Port Status Register, HPSTAT. Cleared by firmware, ClearPortFeature(PORT_RESET).  Bit 3 – POCIC: Port Overcurrent Indicator Change 0 = No change has occurred on Overcurrent Indicator 1 = Overcurrent Indicator has changed This bit is relevant to hubs with individual overcurrent reporting only. The firmware sets this bit as a result of detecting overcurrent at the ports OVC# pin. The firmware clears bit through ClearPortFeature(PORT_OVER_CURRENT). For Port 1, this bit is always cleared.  Bit 2 – PSSC: Port Suspend Status Change 0 = No change 1 = Resume completed Port 2, 3 set by hardware upon completion of firmware initiated resume process. Port 1 set by firmware 20 ms after the next EOF2 after completion of resume process. RESUME signaling is initiated through global resume, selective resume and remote wakeup. Cleared by firmware via host request ClearPortFeature(PORT_SU SPEND).  Bit 1 – PESC: Port Enable/Disable Status Change 0 = No change has occurred on Port Enable/Disable Status 1 = Port Enable/Disable status has changed B i t 7 6 543 2 1 0 Port1 $1FB0 – – – RSTSC POCIC PSSC PESC PCSC PSCR1 Port2 $1FB1 – – – RSTSC POCIC PSSC PESC PCSC PSCR2 Port3 $1FB2 – – – RSTSC POCIC PSSC PESC PCSC PSCR3 Read/Write R R R R R R R R Initial Value 0 0 0 0 0 0 0 0

80 AT43USB353M

3307B–USB–4/04 Set by hardware due to babble, physical disconnect or overcurrent except for Port 1 in which case it is set by hardware at EOF2 due to hardware events. Cleared by firmware via Host request ClearPortFeature(PORT_ENABLE).  Bit 0 – PCSC: Port Connect Status Change 0 = No change has occurred on Current Connect Status 1 = Current Connect Status has changed This bit is set by hardware at EOF2 after it detects a connect or disconnect at a port, except for Port 1. Hardware sets this bit for Port 5 after a hub reset. Cleared by firmware via Host request ClearPortFeature(PORT_CONNECTION). Hub and Port Power Management Overcurrent protection and power switching is required for the external downstream ports only. In the AT43USB353M, these tasks are completely programmable. This means that any type of hub is achievable with the AT43USB353M: self-powered or bus-powered hubs, per port or global overcurrent protection, individual or ganged port power switching. The use of the MCU's GPIO pins are required to interface to the external power supply moni- toring and switching. The on-chip hardware of the AT43USB353M contains the circuitry to handle all the possible combinations of port power management tasks. The firmware defines the exact configuration. Overcurrent Sensing The AT43USB353M is capable of detecting overcu rrent during active operation only, or during any condition even when the hub is in the suspended state. When overcurrent in the active state only is desired, any GPIO pin of the AT43USB353M can be used to sense and the over- current condition. Control of the condition must be performed by the firmware. If overcurrent detection under any condition is desired, then specific GPIO pins must be used to sense the overcurrent and the proper bit(s) of UOVCER set. In Global Overcurrent Protection mode, overcurrent sensing must be routed to GPIO PD0. In Individual Port Overcurrent Protection mode Port2 and Port 3 overcurrent sensing must be assigned to GPIO PD0 and PD1. In the following description, it is assumed that overcurrent protection is required under any condition. 1. Global Overcurrent Protection – In this mode, the Port Overcurrent Indicator and Port Overcurrent Indicator Change should be set to 0's. For the AT43USB353M an external solid state switch, such as the Micrel MIC2025-2, is required to switch power to the external USB ports. The FLG output of the switch should be connected to PD0. When an overcurrent occurs, FLG is asserted and the firmware should set the Hub Overcurrent Indicator and Hub Overcurrent Indicator Change and switch off power to all external downstream ports. The hub status change is reported on the next IN token through the hub's interrupt endpoint, Endpoint1. 2. Individual Port Overcurrent Protection – The Hub Overcurrent Indicator and Hub Overcurrent Indicator Change bits should be set to 0's. One MIC2026-2 is required for the two USB ports. The FLG output of the MIC2026-2 associated with Port2 should be connected to GPIO PD0 and the other FLG output to PD1. An overcurrent is indicated by assertion of FLG. The firmware sets the corresponding port's Overcurrent Indicator and the Overcurrent Indicator Change bits and switches off power to the port. At the next IN token from the Host, the AT43USB353M reports the port status change through the hub's Endpoint1.

82 AT43USB353M

3307B–USB–4/04 Global Resume Global resume is signaled by a J to K state change on Port0. The USB hardware enables the oscillator/PLL, propagates the RESUME signaling, and sets the RSM bit of the SPRSR, which generates an interrupt. The microcontroller starts executing where it left off and services the interrupt. As part of the ISR, the firmware clears the GLB_SUSP bit. Remote Wakeup While the AT43USB353M is in global suspend, resume signaling is also possible through remote wakeup if the remote wakeup feature is enabled. Remote wakeup is defined as a port connect, port disconnect or resume signaling received at a downstream port or, in case of the embedded function, through an external interrupt. A remote wakeup initiated at a downstream port is similar in many respects to a global resume. The USB hardware enables the oscillator/PLL, propagates the RESUME signaling, and sets the RSM bit of the SPRSR which generates an interrupt. The microcontroller starts executing where it left off and services the interrupt. As part of the ISR, the firmware clears the GLB_SUSP bit. A remote wakeup from the embedded function is initiated through INT0 or the external inter- rupt, INT1, which enables the oscillator/PLL and the USB hardware. The USB hardware drives RESUME signaling and sets the FRMWUP and RSM bits of SPRSR which generates an inter- rupt to the microcontroller. The microcontroller starts executing where it left off and services the interrupt. As part of the ISR, the firmware clears the GLB SUSP bit. At completion of RESUME signaling, the USB hardware sets the Port Suspend Status Change bits of the Hub Port Status Change Registers. Selective Suspend and Resume See section on Hub Port Control Register, HPCON. Suspend and Resume Process Global Suspend The Host stops sending packets, the hardware detects this as global suspend signaling and stops all downstream signaling. Finally, the hardware asserts the GLB_SUSP interrupt. Hardware Firmware 1.Host stops sending packets 2. Global suspend signaling detected 3. Stop downstream signaling 4. Set GBL SUS bit → interrupt 5. Shut down any peripheral activity 6. Set Sleep Enable and Sleep Mode bits of MCUCR 7. Set GPIO to low power state if required 8. Set UOVCER bit 2 9. Execute SLEEP instruction 10. SLEEP bit detected 11. Shut off oscillator

3307B–USB–4/04 Global Resume The Host resumes signaling, the hardware detects this as global resume and propagates this signaling to all downstream ports. Finally, the hardware enables the oscillator and asserts the RSM interrupt. Remote Wake-up, Downstream Ports The hardware detects a connect/disconnect/port resume and propagates resume signaling upstream. Finally, the hardware enables the oscillator and asserts the RSM interrupt. Remote Wake-up, Embedded Function The hardware detects an INT0/INT1 and propagates resume signaling upstream. Finally, the hardware enables the oscillator and asserts the RSM and FRWUP interrupts. Hardware Firmware 1.Host resumes signaling 2. Resume signaling detected 3. Propagate signaling downstream 4. Enable oscillator 5. Set RSM bit → interrupt 6. Reset RSM and GBL SUSP bits 7. Restore GPIO states if required 8. Clear UOVCER bit 2 9. Enable peripheral activity Hardware Firmware 1. Connect/disconnect/port resume detected 2. Propagate resume signaling 3. Enable Oscillator 4. Set RSM bit → interrupt 5. Reset RSM and GBL SUSP bits 6. Restore GPIO states if required 7. Clear UOVCER bit 2 8. Enable peripheral activity Hardware Firmware 1.External event activates INT0/INT1 2. Propagate resume signaling 3. Enable Oscillator 4. Set RSM and FRMWUP bits → interrupt 5. Clear GLB SUSP , RSM, FRMWUP bits 6. Restore GPIO states if required 7. Clear UOVCER bit 2 8. Enable peripheral activity

84 AT43USB353M

3307B–USB–4/04 Selective Suspend, Downstream Ports Selective Suspend, Embedded Function Selective Resume, Embedded Function Hardware Firmware 1. Set or Clear Port Feature PORT_SUSPEND decoded 2. Write HPCON[2:0] and HP ADD[2:0] bits 3. Suspend or resume port per command Hardware Firmware 1. Set Port Feature PORT_SUSPEND decoded 2. Disable Port 1’s end-points 3. Set GPIO to low power state if required Hardware Firmware 1. Clear Port Feature PORT_SUSPEND decoded 2. Clear Port 1 suspend status bit 3. Restore GPIO states if required 4. Wait 23 ms, then set enable status bit and suspend change bit 5. Enable Port 1 end-points 6. Send updated port status at next IN to end-point1

sure to absolute maximum rating conditions for extended periods may affect device reliability. Note: VCEXT is the voltage of CEXT1, CEXT2 and CEXTA. Table 27. Absolute Maximum Ratings Table 28. Power Supply Table 29. USB Signals: DPx, DMx

86 AT43USB353M

Note: VCEXT is the voltage of CEXT1, CEXT2 and CEXTA. Note: XT AL2 must not be used to drive other circuitry. Note: 1. With external 27 Ω series resistor. Table 30. PA and PD Table 31. Oscillator Signals: XTAL1, XTAL2 Table 32. USB Driver Characteristics, Full Speed Operation

Figure 21. Full-speed Load Figure 22. Low-speed Downstream Port Load Table 33. USB Driver Characteristics, Low-speed Operation

1.5 K Ohm

88 AT43USB353M

Note: 1. With 6.000 MHz, 100 ppm crystal. Table 34. USB Source Timings, Full-speed Operation

90 AT43USB353M

Table 35. Hub Timings, Full-speed Operation Table 36. Hub Timings, Low-speed Operation Table 37. Hub Event Timings

92 AT43USB353M

3307B–USB–4/04 Packaging Information 48AA – LQFP

2325 Orchard Parkway

San Jose, CA 95131 TITLE DRAWING NO. R REV. 48AA, 48-lead, 7 x 7 mm Body Size, 1.4 mm Body Thickness, 0.5 mm Lead Pitch, Low Profile Plastic Quad Flat Package (LQFP) C48AA 10/5/2001 PIN 1 IDENTIFIER 0˚~7˚ PIN 1 L C A1 A2 A D e E1 E B COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE Notes: 1. This package conforms to JEDEC reference MS-026, Variation BBC. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.08 mm maximum. A – – 1.60 A1 0.05 – 0.15 A2 1.35 1.40 1.45 D 8.75 9.00 9.25 D1 6.90 7.00 7.10 Note 2 E 8.75 9.00 9.25 E1 6.90 7.00 7.10 Note 2 B 0.17 – 0.27 C 0.09 – 0.20 L 0.45 – 0.75 e 0.50 TYP

3307B–USB–4/04 Errata Sheet Errata (All Date Codes): Missed Watchdog Timer Reset Problem There is a synchronization problem between the watchdog clock and the AVR clock. Even though the clock inputs to both the watchdog timer and the AVR core are generated through the same crystal, the two clock sources are not going through the same PLL. The AVR is clocked at 12 MHz and the watchdog timer is clocked at 1MHz. The WDR (Watchdog Reset) instruction is a one-clock-cycle instruction. As such, when a watchdog timer reset occurs due to a WDR, the watchdog timer may miss the reset. This happens frequently if the AVR is clocked much faster than the watchdog timer. Fix/Workaround A workaround is to invoke the WDR repetitively to ensure that the wa tchdog timer will be able to receive the reset signal. If the AVR runs at 12 MHz, the WDR command must be invoked fourteen times back to back. The following is the sample code for resetting and arming the watchdog timer, assuming the AVR is running at 12 MHz: asm ( "ldi r16,15\\n WDR\\n WDR\\n WDR\\n WDR\\n WDR\\n WDR\\n WDR\\n WDR\\n WDR\\n WDR\\n WDR\\n WDR\\n WDR\\n out 0x21,r16 " ); To disarm and disable the watchdog, do the following: asm ( "ldi r16,0x18\\nldi r17,0x10\\n\\n out 0x21,r16\\n out 0x21,r17 " ); Please note that if the AVR runs at 24 MHz, the WDR should be invoked twenty-six times.

94 AT43USB353M

3307B–USB–4/04 Change Log Doc. Rev. Comments 3302D  Data Correction: timeout period data in Table 20 on page 46.  Additions: Added an “Errata Sheet” on page 93 and a “Change Log” on page 94.

Printed on recycled paper. 3307B–USB–4/04 xM Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standar d warranty which is detailed in Atmel’s T erms and Conditions located on the Company’s web site. The Company assumes no responsibi lity for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time wi thout notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not aut horized for use as critical components in life support devices or systems. Atmel Corporation Atmel Operations San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza

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