AT43USB320A

AT43USB320A_04 ATMEL | Alldatasheet

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Datasheet sections

Features

• AVR® 8-bit RISC Microcontroller with 83 ns Instruction Cycle Time  USB Hub with One Attached and Four External Ports  USB Function with Two Programmable Endpoints  External Program Memory, 512-byte Data SRAM  32 x 8 General Purpose Working Registers  32 Programmable I/O Port Pins  Programmable Serial UART  Master/Slave SPI Serial Interface  One 8-bit Timer/Counter with Separate Pre-scaler  One 16-bit Timer/Counter with Separate Pre-scaler and Two PWMs  External and Internal Interrupt Sources  Programmable Watchdog Timer  6 MHz Oscillator with On-chip PLL  5V Operation with On-chip 3.3V Power Supply  100-lead LQFP Package

Description

The Atmel A T43USB320A is an 8-bit microcontroller based on the AVR RISC architec- ture. By executing powerful instructions in a single clock cycle, the AT43USB320A achieves throughputs approaching 12 MIPS. The AVR core combines a rich instruc- tion set with 32 general-purpose working registers. All 32 registers are directly connected to the ALU allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code effi- cient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The AT43USB320A features an on-chip 512-byte of data memory. It is supported by a standard set of peripherals such as timer/counter modules, watchdog timer and inter- nal and external interrupt sources. The major peripheral included in the AT43USB320A is the USB Hub with an embedded function for use in peripherals such as monitor with remote control as shown in Figure 1. Note: There are two versions of the AT43USB320A. They are indicated by the internal part numbers 55618D and 55618E. The only difference between the two versions is in the polarity of the SUSPEND pin. The 55618D SUSPEND pin is active low, while the 55618E SUSPEND pin is active high. Full-speed USB Microcontroller with an Embedded Hub AT43USB320A Rev. 1443E–USB–4/04

2 AT43USB320A

Figure 1. Application Example

1443E–USB–4/04 Pin Assignment T ype: I = Input O = Output B = Bi-directional V = Power Supply, Ground Pin Number Signal Type 1P D 2B 2P D 3B 3P D 4B 4P D 5B 5P D 6B 6P D 7B 76 / 1 2 N I 8L F TO 9X T A L 1 I

10 XT AL2 O

11 VSS V

12 TESTN I

13 A0 B

14 A1 B

15 A2 B

16 A3 B

17 A4 B

18 A5 B

19 A6 B

20 A7 B

21 VSS V

22 A8 B

23 A9 B

24 A10 B

25 NC –

26 NC –

27 A11 B

28 A12 B

29 A13 B

30 A14 B

31 A15 B

32 VCC V

33 VSS V

34 CEXT1 O

35 SUSPEND O

36 D0 I

37 D1 I

38 D2 I

39 D3 I

40 D4 I

41 D5 I

42 D6 I

43 D7 I

44 VSS V

45 D8 I

46 D9 I

47 D10 I

48 D11 I

49 NC –

50 NC –

51 D12 I

52 D13 I

53 D14 I

54 D15 I

55 VSS V

56 ICP V

57 DP0 B

58 DM0 B

59 DP1 B

60 DM1 B

61 VCC V

62 VSS V

4 AT43USB320A

1443E–USB–4/04

63 CEXT2 O

64 DP2 B

65 DM2 B

66 DP3 B

67 DM3 B

68 DP4 B

69 DM4 B

70 PA0 B

71 PA1 B

72 PA2 B

73 PA3 B

74 PA4 B

75 VSS V

76 NC –

77 PA5 B

78 PA6 B

79 PA7 B

80 PB0 B

81 PB1 B

82 PB2 B

83 PB3 B

84 VSS V

85 PB4 B

86 PB5 B

87 PB6 B

88 PB7 B

89 PC0 B

90 PC1 B

91 PC2 B

92 PC3 B

93 PC4 B

94 PC5 B

95 PC6 B

96 PC7 B

97 PD0 B

98 PD1 B

99 VSS V

100 NC –

1443E–USB–4/04 Signal Description Name Type Function VCC Power Supply/Ground 5V Power Supply VSS Power Supply/Ground Ground CEXT1, 2 Power Supply/Ground External Capacitors for Power Supplies – High quality 0.33 µF capacitors must be connected to CEXT1 and 2 for proper operation of the chip. XT AL1 Input Oscillator Input – Input to the inverting oscillator amplifier. XT AL2 Output Oscillator Output – Output of the inverting oscillator amplifier. LFT Input PLL Filter – For proper operation of the PLL, this pin should be connected through a 0.01 µF capacitor in parallel with a 100 Ω resistor in series with a 0.22 µF capacitor to ground (VSS). Both capacitors must be high quality ceramic. DPO Bi-directional Upstream Plus USB I/O – This pin should be connected to CEXT1 through an external 1.5 kΩ. DMO Bi-directional Upstream Minus USB I/O DP[1:4] Bi-directional Downstream Plus USB I/O – Each of these pins should be connected to VSS through an external 15 kΩ resistor. DP[1:4] and DM[1:4] are the differential signal pin pairs to connect downstream USB devices. DM[1:4] Bi-directional Downstream Minus USB I/O – Each of these pins should be connected to VSS through an external 15 kΩ resistor. P A[0:7] Bi-directional Port A[0:7] – Bi-directional 8-bit I/O port with 4 mA drive strength. PB[0:7] Bi-directional Port B[0:7] – Bi-directional 8-bit I/O port with 4 mA drive. PB[0,1,4:7] have dual functions as shown below: Port Pin Alternate Function PB0 T0, Timer/Counter0 External Input PB1 T1, Timer/Counter1 External Input PB4 SSN, SPI Slave Port Select or SCL, I2C Serial Bus Clock PB5 MOSI, SPI Slave Port Select Input PB6 MISO, SPI Master Data In, Slave Data Out PB7 SCK, SPI Master Clock Out, Slave Clock In PC[0:7] Bi-directional Port C[0:7] – Bi-directional 8-bit I/O port with 4 mA drive strength. PD[0:7] Bi-directional Port D[0:7] – Bi-directional I/O ports with 4 mA drive strength. PD[0:3,5] have dual functions as shown below: Port Pin Alternate Function PD0 RXD, Serial Input Port PD1 TXD, Serial Input Port PD2 INT0, External Interrupt 0 PD3 INT1, External Interrupt 1 PD5 OC1A Timer/Counter1 Output Compare A TESTN Input Test Pin – This pin should be tied to ground. SUSPEND Output Suspend – This pin is asserted when the A T43USB320A enters the Suspend status. In the 55618D, it is active low and in the 55618E and later versions, it is active high.

6 AT43USB320A

Figure 2. The AT43USB320A Enhanced RISC Architecture

32 GPIO

1443E–USB–4/04 Architectural Overview The peripherals and features of the AT43USB320A microcontroller are similar to those of the AT90S8515, with the exception of the following modifications:  External Program Memory  No EEPROM  No external data memory accesses  No Analog Comparation  Idle mode not supported  USB Hub with attached function  No internal pull-ups in the general-purpose I/O pin PA, PB, PC, PD The embedded USB hardware of the AT43USB320A is a compound device, consisting of a 5 port hub with a permanently attached function on one port. The hub and attached function are two independent USB devices, each having its own device addresses and control endpoints. The hub has its dedicated interrupt endpoint, while the USB function has 2 additional program- mable endpoints with separate 8-byte FIFOs. The microcontroller always runs from a 12 MHz clock that is generated by the USB hardware. While the nominal and average period of this clock is 83.3 ns, it may have single cycles that deviate by ±20.8 ns during a phase adjustment by the SIE's clock/data separator of the USB hardware. The microcontroller shares most of the control and status registers of the megaAVR ™ Micro- controller Family. The registers for managing the USB operations are mapped into its SRAM space. The I/O section on page 16 summarizes the available I/O registers. The “AVR Register Set” on page 36 covers the AVR registers. Please refer to the Atmel AVR manual for more information. The fast-access register file concept contains 32 x 8-bit general-purpose working registers with a single clock cycle access time. This means that during one single clock cycle, one Arith- metic Logic Unit (ALU) operation is executed. Two operands are output from the register file, the operation is executed, and the result is stored back in the register file – in one clock cycle. Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing - enabling efficient address calculations. One of the three address pointers is also used as the address pointer for look-up tables in program memory. These added func- tion registers are the 16-bit X-, Y- and Z-registers. The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations are also executed in the ALU. Figure 2 on page 6 shows the AT43USB320A AVR Enhanced RISC microcontroller architecture. In addition to the register operation, the conventional memory addressing modes can be used on the register file as well. This is enabled by the fact that the register file is assigned the 32 lowest Data Space addresses ($00 - $1 F), allowing them to be accessed as though they were ordinary memory locations. The I/O memory space contains 64 addresses for CPU peripheral functions as Control Regis- ters, Timer/Counters, and other I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations following those of the register file, $20 - $5F. The AVR uses a Harvard architecture concept – with separate memories and buses for pro- gram and data. The program memory is executed with a single-level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is a downloadable SRAM or a mask programmed ROM. With the relative jump and call instructions, the whole 24K address space is directly accessed. Most AVR instructions have a single 16-bit word format. Every program memory address con- tains a 16- or 32-bit instruction.

8 AT43USB320A

interrupts are executed). The 10-bit SP is read/write accessible in the I/O space. supported in the AVR architecture. between two registers or on a single register apply to the entire register file. registers, as the X-, Y-, and Z-registers can be set to index any register in the file. Table 1. AVR CPU General Purpose Working Register

1443E–USB–4/04 X-, Y- and Z- Registers Registers R26..R31 contain some added functi ons to their general-purpose usage. These reg- isters are address pointers for indirect addressing of the Data Space. The three indirect address registers X, Y, and Z are defined as: In the different addressing modes these address registers have functions as fixed displace- ment, automatic increment and decrement (see the descriptions for the different instructions). ALU – Arithmetic Logic Unit The high-performance AVR ALU operates in direct connection with all 32 general purpose working registers. Within a single clock cycle, ALU operations between registers in the register file are executed. The ALU operations are divided into three main categories – arithmetic, log- ical and bit-functions. Program Memory The AT43USB320A operates from an external program memory. Since all instructions are 16- or 32-bit words, the program memory is organized as X16. The AT43USB320A Program Counter (PC) is 16 bits wide, thus addressing the 64K program memory addresses. Constant tables can be allocated within the entire program memory address space (see the LPM - Load Program Memory instruction description). X-register 15 XH XL 0 70 70 Y -register 15 YH YL 0 70 70 Z-register 15 ZH ZL 0 70 70

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1443E–USB–4/04 SRAM Data Memory Table 3 summarizes how the AT43USB320A SRAM Memory is organized. The lower 608 Data Memory locations address the Register file, the I/O Memory and the internal data SRAM. The first 96 locations address the Register File + I/O Memory, and the next 512 locations address the internal data SRAM. The five different addressing modes for the data memory cover: Direct, Indirect with Displacement, Indirect, Indirect with Pre-decrement and Indirect with Post-increment. In the register file, registers R26 to R31 feature the indirect addressing pointer registers. Direct addressing reaches the entire data space. The Indirect with Displacement mode features 63 address locations that reach from the base address given by the Y- or Z-register. When using register indirect addressing modes with automatic pre-decrement and post-incre- ment, the address registers X, Y, and Z are decremented and incremented. The 32 general purpose working registers, 64 I/O registers and the 1024 bytes of internal data SRAM in the AT43USB320A are all accessible through these addressing modes. To manage the USB hardware, a special set of registers is assigned. These registers are mapped to SRAM space between addresses $1F00 and 1FFF. Table 3 and Table 4 give an overview of these registers.

Table 2. SRAM Organization

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Table 3. USB Hub and Function Registers

Table 3. USB Hub and Function Registers (Continued)

14 AT43USB320A

Table 4. USB Hub and Function Registers

Table 4. USB Hub and Function Registers (Continued)

16 AT43USB320A

Table 5. I/O Memory Space

1443E–USB–4/04 All AT43USB320A I/O and peripherals, except for the USB hardware registers, are placed in the I/O space. The I/O locations are accessed by the IN and OUT instructions transferring data between the 32 general purpose working registers and the I/O space. I/O registers within the address range $00 – $1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instruc- tions. Refer to the instruction set documentations of the AVR for more details. When using the I/O specific commands, IN and OUT, the I/O address $00 – $3F must be used. When address- ing I/O registers as SRAM, $20 must be added to this address. All I/O register addresses throughout this document are shown with the SRAM address in parentheses. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. USB Hub A block diagram of the USB hardware of the AT43USB320A is shown in Figure 3. The USB hub of the AT43USB320A has 5 downstream ports. The embedded function is permanently attached to Port 5. Ports 1 through 4 are available as external ports. The actual number of ports used is strictly defined by the firmware of the AT43USB320A and can vary from 0 to 4. Because the exact configuration is defined by firmware, ports 1 to 4 may even function as per- manently attached ports as long as the Hub Descriptor identifies them as such. USB Function The embedded USB function has its own device address and has a default endpoint plus 2 other programmable endpoints with 8-byte FIFOs. Endpoints 1 - 3 can be programmed as interrupt IN or OUT or bulk IN or OUT endpoints.

18 AT43USB320A

Figure 3. USB Hardware

1443E–USB–4/04 Functional Description On-chip Power Supply The AT43USB320A contains two on-chip power supplies that generate 3.3V with a capacity of 30 mA each from the 5V power input. The on-chip power supplies are intended to supply the AT43USB320A internal circuit and the 1.5K pull-up resistor only and should not be used for other purposes. External 0.33 µF filter capacitors are required at the power supply outputs, CEXT1 and 2. The internal power supplies can be disabled as described in the next paragraph. The user should be careful when the GPIO pins are required to supply high-load currents. If the application requires that the GPIO suppl y currents beyond the c apability of the on-chip power supply, the AT43USB320A should be suppli ed by an external 3.3V power supply. In this case, the 5V V CC power supply pin should be left unconnected and the 3.3V power supplied to the chip through the CEXT1 and 2 pins. I/O Pin Characteristics The I/O pins of the AT43USB320A should not be directly connected to voltages less than V SS or more than the voltage at the CEXT pins. If it is necessary to violate this rule, insert a series resistor between the I/O pin and the source of the external signal source that limits the current into the I/O pin to less than 2 mA. Under no circumstance should the external voltage exceed 5.5V. To do so will put the chip under excessive stress. Oscillator and PLL All clock signals required to operate the AT43USB320A are derived from an on-chip oscillator. To reduce EMI and power dissipation, the oscillator is designed to operate with a 6 MHz crys- tal. An on-chip PLL generates the high frequency for the clock/data separator of the Serial Interface Engine. In the suspended state, the oscillator circuitry is turned off. The oscillator of the AT43USB320A is a special, low-drive type, designed to work with most crystals without any external components. The crystal must be of the parallel resonance type requiring a load capacitance of about 10 pF. If the crystal requires a higher value capacitance, external capacitors can be added to the two terminals of the crystal and ground to meet the required value. To assure quick start-up, a crystal with a high Q, or low ESR, should be used. To meet the USB hub frequency accuracy and stability requirements for hubs, the crystal should have an accuracy and stability of better than 100 PPM. The use of a ceramic resonator in place of the crystal is not recommended because a resonator would not have the necessary frequency accuracy and stability. The clock can also be externally sourced. In this case, connect the clock source to the XTAL1 pin, while leaving XTAL2 pin floating. The switching level at the OSC1 pin can be as low as 0.47V and a CMOS device is required to drive this pin to maintain good noise margins at the low switching level. For proper operation of the PLL, an external RC filter consisting of a series RC network of 100Ω and 0.22 µF in parallel with a 0.01 µF capacitor must be connected from the LFT pin to V SS. Use only high-quality ceramic capacitors.

20 AT43USB320A

Figure 4. Oscillator and PLL register in order to enable the interrupt.

6.000 MHz

Table 6. Reset and Interrupt Vectors

1443E–USB–4/04 The most typical and general program setup for the Reset and Interrupt Vector Addresses are: USB related interrupt events are routed to reset vectors 13 and 2 through a separate set of interrupt, interrupt enable and interrupt mask registers that are mapped to the data SRAM space. These interrupts must be enabled though their control register bits. In the event an interrupt is generated, the source of the interrupt is identified by reading the interrupt registers. The USB frame and transaction related interrupt events, such as Start of Frame interrupt, are grouped in one set of registers: USB Interrupt Flag Register and USB Interrupt Enable Regis- ter. The USB Bus reset and suspend/resume are grouped in another set of registers: Suspend/Resume Register and Suspend/Resume Interrupt Enable Register. Address Labels Code Comments $000 jmp RESET ; Reset Handler $004 jmp EXT_INT1 ; IRQ1 Handler $00E jmp TIM0_OVF ; Timer0 Overflow Handler $018 jmp USB_HW ; USB Handler $00d MAIN: ldi r16, high (RAMEND) ; Main Program start $00e out SPH, r16 $00f ldi r16, low (RAMEND) $010 out SPL, r16 $011 <instr> xxx

22 AT43USB320A

Figure 5. AT43USB320A Interrupt Structure and microcontroller lasts for 24 oscillator periods. tor cycles used for each time-out is shown in Table 7.

Figure 6. Reset Logic Power-on Reset period can be extended. Table 7. Number of Watchdog Oscillator Cycles

24 AT43USB320A

starts the MCU after the Time-out period t TOUT has expired. Figure 7. External Reset During Operation the falling edge of this pulse, the delay timer starts counting the Time-out period t TOUT. Figure 8. Watchdog Reset During Operation Interrupt Mask Register) and TIMSK (Timer/Counter Interrupt Mask Register). set (one) when a Return from Interrupt instruction, RETI, is executed.

1 XTAL Cycle

1443E–USB–4/04 If an interrupt condition occurs when the corresponding interrupt enable bit is cleared (zero), the interrupt flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. If one or more interrupt conditions occur when the global interrupt enable bit is cleared (zero), the corresponding interrupt flag(s) will be set and remembered until the global interrupt enable bit is set (one), and will be executed by order of priority. Note that external level interrupt does not have a flag, and will only be remembered for as long as the interrupt condition is active.

26 AT43USB320A

1443E–USB–4/04 General Interrupt Mask Register – GIMSK  Bit 7 – INT1: External Interrupt Request 1 Enable When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control1 bits 1/0 (ISC11 and ISC10) in the MCU general Control Register (MCUCR) defines whether the external interrupt is acti- vated on rising or falling edge of the INT1 pin or level sensed. Activity on the pin will cause an interrupt request even if INT1 is configured as an output. The corresponding interrupt of Exter- nal Interrupt Request 1 is executed from program memory address $004. See also “External Interrupts” on page 29.  Bit 6 – INT0: Interrupt Request 0 (Suspend/Resume Interrupt) Enable When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the MCU general Control Register (MCUCR) defines whether the external interrupt is acti- vated on rising or falling edge of the INT0 pin or level sensed. Activity on the pin will cause an interrupt request even if INT0 is configured as an output. The corresponding interrupt of Inter- rupt Request 0 is executed from program memory address $002. See also “External Interrupts” on page 29.  Bits 5..0 – Res: Reserved Bits These bits are reserved bits in the AT43USB320A and always read as zero. General Interrupt Flag Register – GIFR  Bit 7 – INTF1: External Interrupt Flag1 When an event on the INT1 pin triggers an interrupt request, INTF1 becomes set (one). If the I-bit in SREG and the INT1 bit in GIMSK are set (one), the MCU will jump to the interrupt vec- tor at address $004. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.  Bit 6 – INTF0: Interrupt Flag0 (Suspend/Resume Interrupt Flag) When an event on the INT0 (that is, a USB event-related interrupt) triggers an interrupt request, INTF0 becomes set (one). If the I-bit in SREG and the INT0 bit in GIMSK are set (one), the MCU will jump to the interrupt vector at address $002. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.  Bits 5..0 – Res: Reserved Bits These bits are reserved bits in the AT43USB320A and always read as zero. B i t 7 6 5 4 3 210 Read/Write R/W R/W R R R R R R Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Read/Write R/W R/W R R R R R R Initial Value 0 0 0 0 0 0 0 0

1443E–USB–4/04 Timer/Counter Interrupt Mask Register – TIMSK  Bit 7 – TOIE1: Timer/Counter1 Overflow Interrupt Enable When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Overflow interrupt is enabled. The corresponding interrupt (at vector $006) is executed if an overflow in Timer/Counter1 occurs, i.e., when the TOV1 bit is set in the Timer/Counter Interrupt Flag Register (TIFR).  Bit 6 – OCE1A: Timer/Counter1 Output CompareA Match Interrupt Enable When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareA Match interrupt is enabled. The corresponding interrupt (at vector $004) is executed if a CompareA match in Timer/Counter1 occurs, i.e., when the OCF1A bit is set in the TIFR.  Bit 5 – OCIE1B: Timer/Counter1 Output CompareB Match Interrupt Enable When the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareB Match interrupt is enabled. The corresponding interrupt (at vector $005) is executed if a CompareB match in Timer/Counter1 occurs, i.e., when the OCF1B bit is set in the TIFR.  Bit 4 – Res: Reserved Bit This bit is a reserved bit in the AT43USB320A and always reads zero.  Bit 3 – TICIE1: Timer/Counter1 Input Capture Interrupt Enable When the TICIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Input Capture Event Interrupt is enabled. The corresponding interrupt (at vec- tor $003) is executed if a capture-triggering event occurs on pin 31, ICP, i.e., when the ICF1 bit is set in the TIFR.  Bit 2 – Res: Reserved Bit This bit is a reserved bit in the AT43USB320A and always reads zero.  Bit 1 – TOIE0: Timer/Counter0 Overflow Interrupt Enable When the TOIE0 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt (at vector $007) is executed if an overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the TIFR.  Bit 0 – Res: Reserved Bit This bit is a reserved bit in the AT43USB320A and always reads zero. Bit 7 6 5 4 3 2 1 0 $39 ($59) TOIE1 OCIE1A OCIE1NB – TICIE1 – TOIE0 – TIMSK Read/Write R/W R/W R/W R R/W R R/W R Initial Value 0 0 0 0 0 0 0 0

28 AT43USB320A

1443E–USB–4/04 Timer/Counter Interrupt Flag Register – TIFR  Bit 7 – TOV1: Timer/Counter1 Overflow Flag The TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by the hardware when executing the corresponding interrupt handling vector. Alternatively, TOV1 is cleared by writing a logic one to the flag. When the I-bit in SREG, and TOIE1 (Timer/Counter1 Overflow Interrupt Enable), and TOV1 are set (one), the Timer/Counter1 Overflow Interrupt is executed. In PWM mode, this bit is set when Timer/Counter1 changes counting direction at $0000.  Bit 6 – OCF1A: Output Compare Flag 1A The OCF1A bit is set (one) when compare ma tch occurs between the Timer/Counter1 and the data in OCR1A - Output Compare Register 1A. OCF1A is cleared by the hardware when exe- cuting the corresponding interrupt handling vector. Alternatively, OCF1A is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1A (Timer/Counter1 Compare match InterruptA Enable), and the OCF1A are set (one), the Timer/Counter1 Compare A match Inter- rupt is executed.  Bit 5 – OCF1B: Output Compare Flag 1B The OCF1B bit is set (one) when compare ma tch occurs between the Timer/Counter1 and the data in OCR1B - Output Compare Register 1B. OCF1B is cleared by the hardware when exe- cuting the corresponding interrupt handling vector. Alternatively, OCF1B is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1B (Timer/Counter1 Compare match InterruptB Enable), and the OCF1B are set (one), the Timer/Counter1 Compare B match Inter- rupt is executed.  Bit 4 – Res: Reserved Bit This bit is a reserved bit in the AT43USB320A and always reads zero.  Bit 3 – ICF1: - Input Capture Flag 1 The ICF1 bit is set (one) to flag an input capture event, indicating that the Timer/Counter1 value has been transferred to the input capture register - ICR1. ICF1 is cleared by the hard- ware when executing the corresponding interrupt handling vector. Alternatively, ICF1 is cleared by writing a logic one to the flag. When the SREG I-bit, and TICIE1 (Timer/Counter1 Input Capture Interrupt Enable), and ICF1 are set (one), the Timer/Counter1 Capture Interrupt is executed.  Bit 2 – Res: Reserved Bit This bit is a reserved bit in the AT43USB320A and always reads zero.  Bit 1 – TOV: Timer/Counter0 Overflow Flag The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by the hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG I- bit, and TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set ( one), the Timer/Counter0 Overflow interrupt is executed.  Bit 0 – Res: Reserved Bit This bit is a reserved bit in the AT43USB320A and always reads zero. B i t 7 6 543 2 1 0 $38 ($58) TOV1 OCF1A OCIFB – ICF1 – TOV0 – TIFR Read/Write R/W R/W R/W R R/W R R/W R Initial Value 0 0 0 0 0 0 0 0

1443E–USB–4/04 External Interrupts The external interrupts are triggered by the INT0 and INT1 pins. Observe that, if enabled, the INT0/INT1 interrupt will trigger even if the INT0/INT1 pins are configured as outputs. This fea- ture provides a way of generating a software interrupt. The external interrupts can be triggered by a falling or rising edge or a low level. This is set up as indicated in the specification for the MCU Control Register (MCUCR) and the Interrupt Sense Control Register (ISCR). When the external interrupt is enabled and is configured as level triggered, the interrupt will trigger as long as the pin is held low. The external interrupts are set up as described in the specification for the MCU Control Register (MCUCR). Interrupt Response Time The interrupt execution response for all the enabled AVR interrupts is 4 clock cycles minimum. 4 clock cycles after the interrupt flag has been set, the program vector address for the actual interrupt handling routine is executed. During th is 4 clock cycle period, the Program Counter (2 bytes) is pushed onto the Stack, and the Stack Pointer is decremented by 2. The vector is nor- mally a jump to the interrupt routine, and this jump takes 3 clock cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed before the interrupt is served. A return from an interrupt handling routine (same as for a subroutine call routine) takes 4 clock cycles. During these 4 clock cycles, the Program Counter (2 bytes) is popped back from the Stack, the Stack Pointer is incremented by 2, and the I flag in SREG is set. When the AVR exits from an interrupt, it will always return to the main program and execute one more instruc- tion before any pending interrupt is served.

30 AT43USB320A

is selected as Sleep Mode. When SM is set (1), Power Down mode is selected as sleep mode. Table 8. INT1 Sense Control 0 0 The low level of INT1 generates an interrupt request. 1 0 The falling edge of INT1 generates an interrupt request. 1 1 The rising edge of INT1 generates an interrupt request. Table 9. INT1 Sense Control 0 0 The low level of INT1 generates an interrupt request. 1 0 The falling edge of INT1 generates an interrupt request. 1 1 The rising edge of INT1 generates an interrupt request.

The USB interrupts are described below. in an interrupt acknowledge register. Table 10. USB Interrupt Sources frame number is stored in the two Frame Number Registers. embedded function out of the suspended state.

32 AT43USB320A

This bit is asserted after the USB hardware receives a valid SOF packet. This bit is asserted 10 clocks before the expected start of a frame. These bits are reserved and always read as zero.

1. RX OUT Packet is set (control and OUT endpoints)
2. TX Packet Ready is cleared AND TX Complete is set (control and IN endpoints)
3. RX SETUP is set (control endpoints only)

Table 11. USB Endpoint Interrupt Sources

1443E–USB–4/04 USB Interrupt Acknowledge Register – UIAR  Bit 7 – SOF INTACK: Start of Frame Interrupt Acknowledge The microcontroller firmware writes a 1 to this bit to clear the SOF INT bit.  Bit 6 – EOF2 INTACK: EOF2 Interrupt Acknowledge The microcontroller firmware writes a 1 to this bit to clear the EOF2 INT bit.  Bit 5, 4 – Res: Reserved bits These bits are reserved and always read as zero.  Bit 3 – HEP0 INTACK: Hub Endpoint 0 Interrupt Acknowledge The microcontroller firmware writes a 1 to this bit to clear the HEP0 INT bit.  Bit 2 – FEP2 INTACK: Function Endpoint 2 Interrupt Acknowledge The microcontroller firmware writes a 1 to this bit to clear the FEP2 bit.  Bit 1 – FEP1 INTACK: Function Endpoint 1 Interrupt Acknowledge The microcontroller firmware writes a 1 to this bit to clear the FEP1 bit.  Bit 0 – FEP0 INTACK: Function Endpoint 0 Interrupt Acknowledge The microcontroller firmware writes a 1 to this bit to clear the FEP0 INT bit. B i t 7654 3 2 1 0 $1FF5 SOF INTACK EOF2 INT ACK – – HEP0 INTACK FEP2 IMSK FEP1 INT ACK FEP0 INTACK UIAR Read/Write W W R W W W W W Initial Value 0 0 0 0 0 0 0 0

34 AT43USB320A

1443E–USB–4/04 USB Interrupt Enable Register – UIER  Bit 7 – SOF IE: Enable Start of Frame Interrupt When the SOF IE bit is set (1), the Start of Frame Interrupt is enabled.  Bit 6 – EOF2 IE: Enable EOF2 Interrupt When the EOF2 IE bit is set (1), the EOF2 Interrupt is enabled.  Bit 5, 4 – Res: Reserved bit These bits are reserved and always read as zero.  Bit 3 – HEP0 IE: Enable Endpoint 0 Interrupt When the HEP0 IE bit is set (1), the Hub Endpoint 0 Interrupt is enabled.  Bit 2 – FEP2 IE: Enable Endpoint 2 Interrupt When the FE2 IE bit is set (1), the Function Endpoint 2 Interrupt is enabled.  Bit 1 – FEP1 IE: Enable Endpoint 1 Interrupt When the FE1 IE bit is set (1), the Function Endpoint 1 Interrupt is enabled.  Bit 0 – FEP0 IE: Enable Endpoint 0 Interrupt When the FE0 IE bit is set (1), the Function Endpoint 0 Interrupt is enabled. Suspend/Resume Register – SPRSR  Bit 7..3 – Res: Reserved Bits These bits are reserved and are always read as zeros.  Bit 2 – FRWUP: Function Remote Wakeup The USB hardware sets this bit to signal that External Interrupt 1 is detected indicating remote wakeup. An interrupt is generated if the FRWUP IE bit of the SPRSIE register is set.  Bit 1 – RSM: Resume The USB hardware sets this bit when a USB resume signaling is detected at any of its port except Port 1. An interrupt is generated if the RSM IE bit of the SPRSIE register is set.  Bit 0 – GLB SUSP: Global Suspend The USB hardware sets this bit when a USB gl obal suspend signaling is detected. An interrupt is generated if the GLBSUSP IE bit of the SPRSIE register is set. B i t 7 654 32 1 0 $1FF3 SOF IE EOF2 IE – – HEP0 IE FEP2 IE FEP1 IE FEP0 IE UIER Read/Write R/W R/W R R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 B i t 7 6543 2 1 0 $1FFA – – – – – FRWUP RSM GLB SUSP SPRSR Read/Write R R R R R/W R R R Initial Value 0 0 0 0 0 0 0 0

1443E–USB–4/04 Suspend/Resume Interrupt Enable Register – SPRSIE  Bit 7..3 – Res: Reserved Bits These bits are reserved and are always read as zeros.  Bit 3 – BUS INT EN: USB Reset Interrupt Enable When the BUS INT EN bit is set, the USB and microcontroller resets are separated. A USB bus reset (SE0 for longer than 3 ms) will reset the USB hardware only and not the microcon- troller. However, an interrupt to the microcontroller will be generated and bit 3 of SPRSR is set.  Bit 2 – FRWUP IE: Function Remote Wakeup Interrupt Enable Setting the FRWUP IE bit will initiate an interrupt whenever the FRWUP bit of SPRSR is set.  Bit 1 – RSM IE: Resume Interrupt Enable Setting the RSM IE bit will initiate an interrupt whenever the RSM bit of SPRSR is set.  Bit 0 – GLB SUSP IE: Global Suspend Interrupt Enable Setting the GLB SUSP IE bit will initiate an interrupt whenever the GLB SUSP bit of SPRSR is set. Bit 7 6 5 4 3 2 1 0 $1FF9 – – – – – FRWUP RSM GLB SUSP SPRSIE Read/Write R R R R R/W R R R Initial Value 0 0 0 0 0 0 0 0

36 AT43USB320A

1443E–USB–4/04 AVR Register Set Status Register and Stack Pointer Status Register – SREG B i t 7 – I: Global Interrupt Enable The global interrupt enable bit must be set (one) for the interrupts to be enabled. The individ- ual interrupt enable control is then performed in separate control registers. If the global interrupt enable bit is cleared (zero), none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by the hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. B i t 6 – T: Bit Copy Storage The bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T bit as source and des- tination for the operated bit. A bit from a register in the register file can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the register file by the BLD instruction. B i t 5 – H: Half Carry Flag The half carry flag H indicates a half carry in some arithmetic operations. See the Instruction Set Description for detailed information. B i t 4 – S: Sign Bit, S = N⊕V The S-bit is always an exclusive or between the negative flag N and the two's complement overflow flag V. See the Instruction Set Description for detailed information. B i t 3 – V: Two's Complement Overflow Flag The two's complement overflow flag V supports two's complement arithmetics. See the Instruction Set Description for detailed information. B i t 2 – N: Negative Flag The negative flag N indicates a negative result after the different arithmetic and logic opera- tions. See the Instruction Set Description for detailed information. B i t 1 – Z: Zero Flag The zero flag Z indicates a zero result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information. B i t 0 – C: Carry Flag The carry flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set Description for detailed information. Note that the status register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt routine. This must be handled by software. B i t7 6543 2 1 0 $3F ($5F) ITHSV N Z C S R E G Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0

1443E–USB–4/04 Stack Pointer Register – SP The Stack Pointer points to the data SRAM stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The stack pointer must be set to point above $60. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when an address is pushed onto the Stack with subroutine calls and interrupts. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction and it is incremented by two when an address is popped from the Stack with return from subroutine RET or return from interrupt RETI. Sleep Modes To enter the sleep modes, the SE bit in MCUCR must be set (one) and a SLEEP instruction must be executed. If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU awakes, executes the interrupt routine, and resumes execution from the instruction following SLEEP. The contents of the register file, SRAM and I/O memory are unaltered. If a reset occurs during sleep mode, the MCU wakes up and executes from the Reset vector. Power Down Mode When the SM bit is set (one), the SLEEP instruction forces the MCU into the Power Down Mode. In this mode, the external oscillator is stopped, while the external interrupts and the Watchdog (if enabled) continue operating. Only an external reset or an external level interrupt on INT0 or INT1 can wake up the MCU. Note that when a level triggered interrupt is used for wake-up from power down, the low level must be held for a time longer than the reset delay time-out period t TOUT. Otherwise, the MCU will fail to wake up. Bit 15 14 13 12 11 10 9 8 $3E ($5E) I T H S V N Z C SPH $3D ($5D) SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL 76 5 4 3 2 10 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 00 0 0 0 0 00

38 AT43USB320A

as a counter with an external pin connection which triggers the counting. stop, can be selected as clock sources. Figure 9. Timer/Counter Prescaler

time between two external clock transitions must be at least one internal CPU clock period. The external clock signal is sampled on the rising edge of the internal CPU clock. Figure 10. Timer/Counter0 Block Diagram

40 AT43USB320A

These bits are reserved bits in the AT43USB320A and always read as zero. The Clock Select0 bits 2, 1 and 0 define the prescaling source of Timer/Counter0. an output. This feature can give the user SW control of the counting. ing in the clock cycle following the write operation. Table 12. Clock 0 Prescale Select

001 C K

010 C K / 8

011 C K / 6 4

100 C K / 2 5 6

101 C K / 1 0 2 4

Figure 11. Timer/Counter1 Block Diagram

42 AT43USB320A

The 16-bit Timer/Counter1 can select clock source from CK, prescaled CK or an external pin. time between two external clock transitions must be at least one internal CPU clock period. The external clock signal is sampled on the rising edge of the internal CPU clock. monitored over 4 samples, and all 4 must be equal to activate the capture flag. Figure 12. ICP Pin Schematic Diagram

match in Timer/Counter1. Any output pin actions affect pin OC1A (Output CompareA) pin 1. set (one) to control the output pin. The control configuration is shown in Table 13.

1. In PWM mode, these bits have a different function. Refer to Table 17 for a detailed

These bits are reserved bits in the AT43USB320A and always read zero. These bits select PWM operation of Timer/Counter1 as specified in Table 14. Table 13. Compare 1 Mode Select (2) Table 14. PWM Mode Select 0 0 PWM operation of Timer/Counter1 is disabled. 0 1 Timer/Counter1 is an 8-bit PWM. 1 0 Timer/Counter1 is a 9-bit PWM. 1 1 Timer/Counter1 is a 10-bit PWM.

44 AT43USB320A

Timer/Counter1 contents are transferred to the ICR1 on the rising edge of the ICP. These bits are reserved bits in the AT43USB320A and always read zero. In PWM mode, this bit has no effect. The Clock Select1 bits 2, 1 and 0 define the prescaling source of Timer/Counter1. Table 15. Clock 1 Prescale Select 0 0 0 Stop, the Timer/Counter1 is stopped.

an output. This feature can give the user SW control of the counting. Table 15. Clock 1 Prescale Select (Continued)

46 AT43USB320A

1443E–USB–4/04 Timer/Counter1 – TCNT1H and TCNT1L This 16-bit register contains the prescaled value of the 16-bit Timer/Counter1. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary register (TEMP). This tem- porary register is also used when accessing OCR1A, OCR1B and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be dis- abled during access from the main program and from interrupt routines if interrupts are allowed from within interrupt routines.  TCNT1 Timer/Counter1 Write: When the CPU writes to the high byte TCNT1H, the written data is placed in the TEMP regis- ter. Next, when the CPU writes the low byte TCNT1L, this byte of data is combined with the byte data in the TEMP register, and all 16 bits are written to the TCNT1 Timer/Counter1 regis- ter simultaneously. Consequently, the high byte TCNT1H must be accessed first for a full 16- bit register write operation.  TCNT1 Timer/Counter1 Read: When the CPU reads the low byte TCNT1L, the data of the low byte TCNT1L is sent to the CPU and the data of the high byte TCNT1H is placed in the TEMP register. When the CPU reads the data in the high byte TCNT1H, the CPU receives the data in the TEMP register. Consequently, the low byte TCNT1L must be accessed first for a full 16-bit register read operation. The Timer/Counter1 is realized as an up or up/down (in PWM mode) counter with read and write access. If Timer/Counter1 is written to and a clock source is selected, the Timer/Counter1 continues counting in the timer clock cycle after it is preset with the written value. Bit 15 14 13 12 11 10 9 8 76 5 4 3 2 10 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 00 0 0 0 0 00

1443E–USB–4/04 Timer/Counter1 Output Compare Register – OCR1AH and OCR1AL Timer/Counter1 Output Compare Register – OCR1BH and OCR1BL The output compare registers ar e 16-bit read/write registers. The Timer/Counter1 Output Compare Registers contain the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Con- trol and Status register.A compare match does only occur if Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR1B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the com- pare event. Since the Output Compare Registers OCR1A and OCR1B are 16-bit registers, a temporary register TEMP is used when OCR1A/B are wr itten to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the data is tempo- rarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL or OCR1BL, the TEMP register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program and from in terrupt routines if interrupts are allowed from within interrupt routines. Bit 15 14 13 12 11 10 9 8 76 5 4 3 2 10 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 00 0 0 0 0 00 B i t 1 5 1 41 31 21 1 1 0 9 8 7 6543 2 1 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W I n i t i a l V a l u e 0 0000 0 0 0 0 0000 0 0 0

48 AT43USB320A

The input capture register is a 16-bit read-only register. data is sent to the CPU and the data of the high byte ICR1H is placed in the TEMP register. allowed from within interrupt routines. free and phase correct PWM with outputs on the PD5 (OC1A) and OC1B pins. Table 16. Timer TOP Values and PWM Frequency

unsynchronized OCR1A/OCR1B write. See Figure 13 for an example. Figure 13. Effects on Unsynchronized OCR1 Latching COM1B1/COM1B0. This is shown in Table 18. Table 17. Compare1 Mode Select in PWM Mode down-counting (non-inverted PWM).

50 AT43USB320A

time the counter reaches the TOP value, making a one-period PWM pulse. enabled. This also applies to the Timer Output Compare1 flags and interrupts. Watchdog Timer The Watchdog Timer is clocked from a 1 MHz clo ck derived from the 6 MHz on chip oscillator. and executes from the reset vector. Figure 14. Watchdog Timer Table 18. PWM Outputs OCR1X = $0000 or Top

10 T O P H

11 T O P L

1 MHz Clock

These bits are reserved bits in the AT43USB320A and w ill always read as zero. description of the WDE bit for a watchdog disable procedure.

1. In the same operation, write a logical one to WDTOE and WDE. A logical one must be

written to WDE even though it is set to one before the disable operation starts.

1. Within the next four clock cycles, write a logical 0 to WDE. This disables the watchdog.

Periods are shown in Table 19. abled or reset before changing the Watchdog Timer Prescale Select. Table 19. Watchdog Timer Prescale Select

52 AT43USB320A

Figure 15. SPI Block Diagram

PB7(SCK) pin is the clock output in the master mode and is the clock input in the slave mode. data in the master and the slave are interchanged. Figure 16. SPI Master/Slave Interconnection wise, the first byte is lost. Table 20. SPI Pin Overrides

54 AT43USB320A

1. The MSTR bit in SPCR is cleared and the SPI system becomes a slave. As a result of

the SPI becoming a slave, the MOSI and SCK pins become inputs.

1. The SPIF flag in SPSR is set, and if the SPI interrupt is enabled and the I-bit in SREG

are set, the interrupt routine will be executed. bility that SS is driven low, the interrupt should always check that the MSTR bit is still set. ing immediately and both data received and data sent must be considered as lost. Figure 17. SPI Transfer Format with CPHA = 0 and DORD = 0 Note: * Not defined but normally LSB of character just received.

Figure 18. SPI Transfer Format with CPHA = 1 and DORD = 0 Note: * Not defined, but normally LSB of previously transmitted character.

56 AT43USB320A

global interrupts are enabled. When the DORD bit is set (one), the LSB of the data word is transmitted first. When the DORD bit is cleared (zero), the MSB of the data word is transmitted first. when idle. Refer to Figure 17 and Figure 18 for additional information. Refer to Figure 17 or Figure 18 for the functionality of this bit. Table 21. Relationship Between SCK and the Oscillator Frequency

1443E–USB–4/04 SPI Status Register – SPSR B i t 7 – SPIF: SPI Interrupt Flag When a serial transfer is complete, the SPIF bit is set (one) and an interrupt is generated if SPIE in SPCR is set (one) and global interrupts are enabled. If SS is an input and is driven low when the SPI is in master mode, this will also set the SPIF flag. SPIF is cleared by the hard- ware when executing the corresponding interrupt handling vector. Alternatively, the SPIF bit is cleared by first reading the SPI status register when SPIF is set (one), then accessing the SPI Data Register (SPDR). B i t 6 – WCOL: Write Collision Flag The WCOL bit is set if the SPI data register (SPDR) is written during a data transfer. The WCOL bit (and the SPIF bit) are cleared (zero) by first reading the SPI Status Register when WCOL is set (one), and then accessing the SPI Data Register.  Bit 5..0 – Res: Reserved Bits These bits are reserved bits in the AT43USB320A and w ill always read as zero. SPI Data Register – SPDR The SPI Data Register is a read/write register used for data transfer between the register file and the SPI Shift register. Writing to the register initiates data transmission. Reading the regis- ter causes the Shift Register Receive buffer to be read. UART The AT43USB320A features a full duplex (separate receive and transmit registers) Universal Asynchronous Receiver and Transmitter (UART). The main features are:  Baud rate generator that can generate a large number of baud rates (bps)  High baud rates at low XTAL frequencies  8-bit data  Noise filtering  Overrun detection  Framing Error detection  False Start Bit detection  Three separate interrupts on TX Complete, TX Data Register Empty and RX Complete Bit 7 6 5 4 3 2 1 0 R e a d / W r i t e R RRRR R R R Initial Value 0 0 0 0 0 0 0 0 B i t7 6543 2 1 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value x x x x x x x x Undefined

58 AT43USB320A

1443E–USB–4/04 Data Transmission A block schematic of the UART transmitter is shown in Figure 19. Data transmission is initiated by writing the data to be transmitted to the UART I/O Data Register, UDR. Data is transferred from UDR to the Transmit shift register when:  A new character has been written to UDR after the stop bit from the previous character has been shifted out. The shift register is loaded immediately.  A new character has been written to UDR before the stop bit from the previous character has been shifted out. The shift register is loaded when the stop bit of the character currently being transmitted has been shifted out. If the 10-bit Transmitter shift register is empty, data is transferred from UDR to the shift regis- ter. At this time the UDR E (UART Data Register Empty) bit in the UART Status Register, USR, is set. When this bit is set (one), the UART is ready to receive the next character. At the same time as the data is transferred from UDR to the 10-bit shift register, bit 0 of the shift reg- ister is cleared (start bit) and bit 9 is set (stop bit). On the baud rate clock following the transfer operation to the shift register, the start bit is shifted out on the TXD pin. The n follows the data, LSB first. When the stop bit has been shifted out, the shift register is loaded if any new data has been written to the UDR during the transmission. During loading, UDRE is set. If there is no new data in the UDR register to send when the stop bit is shifted out, the UDRE flag will remain set until UDR is written again. When no new data has been written and the stop bit has been present on TXD for one bit length, the TX Complete flag (TXC) in USR is set. The TXEN bit in UCR enables the UART Transmitter when set (one). When this bit is cleared (zero), the PD1 pin can be used for general I/O. When TXEN is set, the UART Transmitter will be connected to PD1, which is forced to be an output pin regardless of the setting of the DDD1 bit in DDRD.

Figure 19. UART Transmitter Data Reception Figure 20 shows a block diagram of the UART Receiver. rejected as a noise spike and the receiver starts looking for the next 1-to-0 transition. Shift register as they are sampled. Sampling of an incoming character is shown in Figure 19. the FE bit to detect framing errors.

60 AT43USB320A

Data register is accessed, and when UDR is written, the Transmit Data register is accessed. control the pull-up resistor on the pin. Figure 20. UART Receiver Figure 21. Sampling Received Data

1443E–USB–4/04 UART Control UART I/O Data Register – UDR The UDR register is actually two physically separate registers sharing the same I/O address. When writing to the register, the UART Transmit Data register is written. When reading from UDR, the UART Receive Data register is read. UART Status Register – USR The USR register is a read-only register providing information on the UART status.  Bits 7 – RXC: UART Receive Complete This bit is set (one) when a received character is transferred from the Receiver Shift register to UDR. The bit is set regardless of any detected framing errors. When the RXCIE bit in UCR is set, the UART Receive Complete interrupt will be executed when RXC is set (one). RXC is cleared by reading UDR. When interrupt-driven data reception is used, the UART Receive Complete Interrupt routine must read UDR in order to clear RXC, otherwise a new interrupt will occur once the interrupt routine terminates.  Bit 6 – TXC: UART Transmit Complete This bit is set (one) when the entire character (including the stop bit) in the Transmit Shift reg- ister has been shifted out an d no new data has been written to UDR. This flag is especially useful in half-duplex communications interfaces, where a transmitting application must enter receive mode and free the communications bus immediately after completing the transmission. When the TXCIE bit in UCR is set, setting of TXC causes the UART Transmit Complete inter- rupt to be executed. TXC is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the TXC bit is cleared (zero) by writing a logical "1"to the bit.  Bit 5 – UDRE: UART Data Register Empty This bit is set (one) when a character written to UDR is transferred to the Transmit Shift regis- ter. Setting of this bit indicates that the transmitter is ready to receive a new character for transmission. B i t 76543210 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W I n i t i a l V a l u e 00000000 B i t 76543210 $0D ($2B) RXC TXC UDRE FE OR – – – USR R e a d / W r i t e R / W R / W RRRRRR I n i t i a l V a l u e 00000000

62 AT43USB320A

1443E–USB–4/04 When the UDRIE bit in UCR is set, the UART Transmit Complete interrupt to be executed as long as UDRE is set. UDRE is cleared by writing UDR. When interrupt-driven data transmittal is used, the UART Data Register Empty Interrupt routine must write UDR in order to clear UDRE, otherwise a new interrupt will occur once the interrupt routine terminates. UDRE is set (one) during reset to indicate that the transmitter is ready.  Bit 4 – FE: Framing Error This bit is set if a Framing Error condition is detected, i.e., when the stop bit of an incoming character is zero. The FE bit is cleared when the stop bit of received data is one.  Bit 3 – OR: Overrun This bit is set if an Overrun condition is detected, i.e., when a character already present in the UDR register is not read before the next character has been shifted into the Receiver Shift reg- ister. The OR bit is buffered, which means that it will be set once the valid data still in UDRE is read. The OR bit is cleared (zero) when data is received and transferred to UDR.  Bits 2...0 – Res: Reserved Bits These bits are reserved bits in the AT43USB320A and w ill always read as zero. UART Control Register – UCR  Bit 7 – RXCIE: RX Complete Interrupt Enable When this bit is set (one), a setting of the RXC bit in USR will cause the Receive Complete Interrupt routine to be executed provided that global interrupts are enabled.  Bit 6 – TXCIE: TX Complete Interrupt Enable When this bit is set (one), a setting of the TXC bit in USR will cause the Transmit Complete Interrupt routine to be executed provided that global interrupts are enabled.  Bit 5 – UDRIE: UART Data Register Empty Interrupt Enable When this bit is set (one), a setting of the UDR E bit in USR will cause the UART Data Register Empty Interrupt routine to be executed provided that global interrupts are enabled.  Bit 4 – RXEN: Receiver Enable This bit enables the UART receiver when set (one). When the receiver is disabled, the TXC, OR and FE status flags cannot become set. If these flags are set, turning off RXEN does not cause them to be cleared.  Bit 3 – TXEN: Transmitter Enable This bit enables the UART transmitter when set (one). When disabling the transmitter while transmitting a character, the transmitter is not disabled before the character in the shift register plus any following character in UDR has been completely transmitted.  Bit 2 ..0 – RES: Reserved Bits These bits are the reserved bits of the AT43USB320A. B i t 76543210 $0A ($2A) RXCIE TXCIE UDRIE RXEN TXEN - - - UCR Read/Write R/W R/W R/W R/W R/W R R/W I n i t i a l v a l u e 00000 10

have more than 1% error is not recommended. High error ratings give less noise immunity. to the equation on the previous page. Table 22. UBRR Settings

64 AT43USB320A

Data Direction Register are read/write. The port pins have no selectable pull-up resistors. when reading PINA, the logical values present on the pins are read. All 8 pins in Port A have equal functionality when used as digital I/O pins. when a reset condition becomes active, even if the clock is not active. Note: n: 7,6...0, pin number. Port B Port B is an 8-bit bi-directional I/O port. The Port B output buffers can sink or source 4 mA. Table 23. DDAn Effects on Port A Pins

Data Direction Register are read/write. The port pins have no selectable pull-up resistors. according to the alternate function description. Table 24. Port B Pins Alternate Functions

66 AT43USB320A

when reading PINB, the logical values present on the pins are read. All 8 pins in port B have equal functionality when used as digital I/O pins. when a reset condition becomes active, even if the clock is not active. Note: n: 7, 6...0, pin number. Table 25. DDBn Effects on Port B Pins

Data Direction Register are read/write. when reading PINC, the logical values present on the pins are read. All 8 pins in Port C have equal functionality when used as digital I/O pins. are tri-stated when a reset condition becomes active, even if the clock is not active. Table 26. DDCn Effects on Port C Pins

68 AT43USB320A

Port D Port D is an 8-bit bi-directional I/O port. Its output buffers can sink or source 2 mA. Data Direction Register are read/write. The port pins have no selectable pull-up resistors. Some Port D pins have alternate functions as shown in Table 27. according to the alternate function description. when reading PIND, the logical values present on the pins are read. Table 27. Port D Alternate Functions

when a reset condition becomes active, even if the clock is not active. Note: n: 7, 6...0, pin number. address and endpoints. Its operation is controlled through a set of memory mapped registers. all packet data types and packet fields. acts upon commands sent by the firmware. controller reads the FIFO and parses the request. Table 28. DDDn Bits on Port D Pins

70 AT43USB320A

1443E–USB–4/04 that the transaction has been completed successfully. Retries and data toggles are performed automatically by the USB hardware. When the IN endpoint is not ready to send data, in the case where the microcontroller has not filled the FIFO, it will automatically respond with a NAK. Similarly, an OUT endpoint will wait for an OUT token. When one is received, it will store the data in the FIFO, completes the transaction and interrupt the microcontroller, which then reads the FIFO and enables the endpoint for the next packet. If the FIFO is not cleared, the USB hardware will responds with a NAK. A detailed description of how USB transactions are handled is described in the following sec- tions. First for a control endpoint and then for non-control endpoints. Control Transfers at Control Endpoint EP0 The description given below is for the function control endpoint, but applies to the hub control endpoint as well if the proper registers are used. The following illustration describes the three possible types of control transfers – Control Write, Control Read and No-data control: Setup Data Status Stage Stage Stage Control Write DATA0 DATA1 DATA0 DATA0/1 DATA1(0) Control Read DATA0 DATA1 DATA0 DATA0/1 DATA1(0) Setup Status Stage Stage No-data Control DATA0 DATA1(0) SETUP(0) SETUP(0) OUT(1) OUT(0) OUT(0/1)… IN(1)IN(1) SETUP(0) IN(1) IN(1) OUT(1)IN(0) IN(0/1)… Legend: DATAn Data packet with PID’s data toggle bit equal to n DATA1(0) Zero length DATA1 packet

1443E–USB–4/04 The following state diagram shows how the various state transitions are triggered. Additional decision making may take place within the response states to determine the next expected state. Unmarked arcs represent transitions that trigger immediately following completion of the response state processing. Stable states, those requiring an interrupt to exit having no unmarked arcs as exit paths, are shown in bold. Idle Setup Response No-data Status Response Control Read Status Response Control Write Status Response RX_SETUP_INT RX_OUT_INT TX_COMPLETE_INT TX_COMPLETE_INT TX_COMPLETE_INT RX_OUT_INT Control Read Data Response TX_COMPLETE_INT Control Write Data ResponseRX_OUT_INT (ANY STABLE STATE)

72 AT43USB320A

1443E–USB–4/04 The following information describes how the AT43USB320A’s USB hardware and firmware operates during a control transfer between the host and the hub’s or function’s control endpoint. Idle State This is the default state from power-up. Setup Response State The Function Interface Unit (FIU) receives a SETUP token with 8 bytes of data from the Host. The FIU stores the data in the FIFO, sends an ACK back to the host and asserts an RX_SETUP interrupt. Legend: DA TA1/DA T A0 = Data packet with DAT A1 or DA T A2 PID DA TA1(0) = Zero length DAT A1 packet Hardware Firmware 1. SETUP token, Data from Host 2. ACK to Host 3. Store data in FIFO 4. Set RX SETUP → INT 5. Read UISR 6. Read CSR0 7. Read Byte Count 8. Read FIFO 9. Parse command data 10. Write to H/FCAR0: a. If Control Read: set DIR, clear RX SETUP , fill FIFO, set TX Packet Ready in CAR0 b. If Control Write: clear DIR in CAR0 c. If no Data Stage: set Data End, clear DIR, set Force STALL in CAR0 11. Set UIAR[EP0 INTACK] to clear the interrupt source

1443E–USB–4/04 No-data Status Response State The Function Interface Unit receives an IN token from the Host. The FIU responds with a zero length DATA1 packet until receiving an ACK from the host, then asserts a TX_COMPLETE interrupt. Control Read Data Response State The Function Interface Unit receives an IN token from the Host. The FIU responds with NAKs until TX_PACKET_READY is set. The FIU then sends the data in the FIFO upstream, retrying until it successfully receives an ACK from the host. Finally, the FIU clears the TX_PACKET_READY bit and asserts a TX_COMPLETE interrupt. Hardware Firmware 1. IN token from Host 2. Send DATA1(0) 3. ACK from Host 4. Set TX COMPLETE → INT 5. Read UISR 6. Read CSR0 7. If SET ADDRESS, program the new Address, set ADD_EN bit 8. Clear TX_COMPLETE, clear Data End, set Force STALL in CAR0 9. Set UIAR[EP0 INT ACK] Hardware Firmware 1. IN token from Host 2. a. If TX Packet Ready = 1, send DATA0/DATA1 b. If TX Packet Ready = 0, send NAK 3. ACK from Host 4. Clear TX Packet Ready Set TX Complete → INT 5. Read UISR 6. Read CSR0 7. Clear TX COMPLETE in CAR0: a. If more data: fill FIFO, set TX Packet Ready, set DIR in CAR0 b. If no more data: set Force STALL, set DAT A END in CAR0 8. Set UIAR[EP0 INTACK] to clear interrupt source Repeat steps 1 through 8

74 AT43USB320A

1443E–USB–4/04 Control Read Status Response State The Function Interface Unit receives an OUT token from the Host with a zero length DATA1 packet. The FIU responds with a NAK until TX_COMPLETE is cleared. The FIU will then ACK the retried OUT token from the Host and assert an RX_OUT interrupt. Control Write Data Response State The Function Interface Unit receives an OUT token from the Host with a DATA packet. The FIU places the incoming data into the FIFO, issues an ACK to the host, and asserts an RX_OUT interrupt. Hardware Firmware 1. OUT token from Host 2. DA TA1(0) from Host 3. TX Complete = 0 ? a. If yes, ACK to Host Set RX OUT → INT b. If no, NAK to Host 4. Read UISR 5. Read CSR0 6. Clear RX OUT, set Data End, set Force Stall in H/FCAR0. Note: A SETUP token will clear Data End, therefore, it is not cleared by FW in case Host retries. 7. Set UIAR[EP0 INTACK] to clear interrupt source Hardware Firmware 1. OUT token from Host 2. Put DATA0/DATA1 into FIFO 3. ACK to Host 4. Set RX OUT → INT 5. Read UISR 6. Read CSR0 7. Read FIFO 8. Clear RX OUT If last data packet, set Force STALL, set DATA END. 9. Set UIAR[EP0 INTACK] to clear the interrupt source Repeat steps 1 through 9 until last DAT A P ACKET:

1443E–USB–4/04 Control Write Status Response State The Function Interface Unit receives an IN token from the Host. The FIU responds with a zero length DATA1 packet, retrying until it receives an ACK back from the Host. The FIU then asserts a TX_COMPLETE interrupt. Hardware Firmware 1. IN token from Host 2. Send Data1(0) 3. ACK from Host 4. Set TX Complete → INT 5. Read UISR 6. Read CSR0 7. Clear TX COMPLETE, clear Data End, set Force STALL in CAR0 8. Set UIAR[EP0 INTACK] to clear the interrupt source

76 AT43USB320A

1443E–USB–4/04 Interrupt/Bulk IN Transfers at Function Endpoint The firmware must first condition the endpoint through the Endpoint Control Register, FENDP1/2_CNTR: Set endpoint direction: set EPDIR Set interrupt or bulk: EPTYPE = 11 or 10 Enable endpoint: set EPEN The Function Interface Unit receives an IN token from the Host. The FIU responds with NAKs until TX_PACKET_READY is set. The FIU then sends the data in the FIFO upstream, retrying until it successfully receives an ACK from the host. Finally, the FIU clears the TX_PACKET_READY bit and asserts a TX_COMPLETE interrupt. 1. Read UISR 2. Read FCSR1/2 3. Clear TX_COMPLETE If more data: fill FIFO, set TX Packet Ready Wait for TX_COMPLETE interrupt If no more data: set DATA END in FCAR1/2 4. Set UIAR[FEP1/2 INTACK] to clear the interrupt source Interrupt/Bulk OUT Transfers at Function Endpoint EP1 and 2 The firmware must first condition the endpoint through the Endpoint Control Register, FENDP1/2_CNTR: Set endpoint direction: clear EPDIR Set interrupt or bulk: EPTYPE = 11 or 10 Enable endpoint: set EPEN The Function Interface Unit receives an OUT token from the Host with a DATA packet. The FIU places the incoming data into the FIFO, issues an ACK to the host, and asserts an RX_OUT interrupt. 1. Read UISR 2. Read FCSR1/2 3. Read FIFO 4. Clear RX_OUT If more data: Wait for RX_OUT interrupt If no more data: set DATA END 5. Set UIAR[FEP1/2 INTACK] to clear the interrupt source

1443E–USB–4/04 USB Registers The following sections describe the registers of the AT43USB320A’s USB hub and function units. Reading a bit for which the microcontroller does not have read access will yield a zero value result. Writing to a bit for which the microcontroller does not have write access has no effect. Hub Address Register – HADDR The USB hub contains an address register that contains the hub address assigned by the host. This Hub Address Register must be programmed by the microcontroller once it has received a SET_ADDRESS re quest from the host. The USB hardware uses the new address only after the status phase of the transaction is completed when the microcontroller has enabled the new address by setting bit 0 of the Global State Register. After power-up or reset, this register will contain the value of 0x00. Hub Address Register – HADDR  Bit 7 – SAEN: Single Address Enable The Single Address Enable bit allows the microcontroller to configure the AT43USB320A into a single address or a composite device. Once this capability is enabled, the hub endpoint 0 (HEP0) is converted from a control endpoint to a programmable function endpoint FEP3; all the endpoints would then operate on the single address. B i t7 6543 2 1 0 $1FEF SAEN HADD6 HADD5 HADD4 HADD3 HADD2 HADD1 HADD0 HADDR Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0

78 AT43USB320A

1443E–USB–4/04 Function Address Register – FADDR The USB function contains an address register that contains the function address assigned by the host. This Function Address Register must be programmed by the microcontroller once it has received a SET_ADDRESS request from the host and completed the status phase of the transaction. After power up or reset, this register will contain the value of 0x00. Function Address Register – FADDR  Bit 7 – FEN: Function Enable The Function Enable bit (FEN) allows the firmware to enable or disable the function endpoints. The firmware will set this bit after rece ipt of a reset through the hub, SetPortFea- ture[PORT_RESET]. Once this bit is set, the USB hardware passes to and from the host. When the Single Address bit is set, the condition of FEN is ignored. Endpoint Registers Hub Endpoint 0 Control Register – HENDP0_CR Function Endpoint 0 Control Register – FENDP0_CR  Bit 7 – EPEN: Endpoint Enable 0 = Disable endpoint 1 = Enable endpoint  Bit 6..4 – Reserved These bits are reserved in the AT43USB320A and will read as zero.  Bit 3 – DTGLE: Data Toggle Identifies DATA0 or DATA1 packets. This bit will automatically toggle and requires clearing by the firmware only in certain special circumstances.  Bit 2 – EPDIR: Endpoint Direction 0 = Out 1 = In  Bit 1, 0 – EPTYPE: Endpoint Type These bits must be programmed as 0, 0. B i t7 6543 2 1 0 $1FEE FEN FADD6 FADD5 FADD4 FADD3 FADD2 FADD1 FADD0 FADDR Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 B i t 7 65432 1 0 $1FE7 EPEN – – – DTGLE EPDIR EPTYPE1 EPTYPE0 HENDP0_CR $24 ($44) EPEN – – – DTGLE EPDIR EPTYPE1 EPTYPE0 FENDP0_CR Read/Write R/W R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0

1443E–USB–4/04 Function Endpoint 1, 2 Control Register – FENDP1,2_CR  Bit 7 – EPEN: Endpoint Enable 0 = Disable endpoint 1 = Enable endpoint  Bit 6..4 – Reserved These bits are reserved in the AT43USB320A and will read as zero.  Bit 3 – DTGLE: Data Toggle Identifies DATA0 or DATA1 packets. This bit will automatically toggle and requires clearing by the firmware only in certain special circumstances.  Bit 2 – EPDIR: Endpoint Direction 0 = Out 1 = In  Bit 1, 0 – EPTYPE: Endpoint Type These bits programs the type of endpoint. B i t 7654 3 2 1 0 $1FE4 EPEN – – – DTGLE EPDIR EPTYPE1 EPTYPE0 FENDP1_CR $1FE3 EPEN – – – DTGLE EPDIR EPTYPE1 EPTYPE0 FENDP2_CR Read/Write R/W R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit1 Bit0 Type 0 1 Isochronous

10 B u l k

80 AT43USB320A

1443E–USB–4/04 Hub Endpoint 0 Data Register – HDR0 Function Endpoint 0..2 Data Register – FDR0..2 This register is used to read data from or to write data to the Hub Endpoint 0 FIFO.  Bit 7..0 – FDAT7..0: FIFO Data Hub endpoint 1 has a single byte data register instead of a FIFO. This data register contains the hub and port status change bitmap. This data register is automatically updated by the USB hardware and is not accessible by the firmware. The bits in this register when read by the host will be:  Bit 7, 6 – Reserved These bits are reserved in the AT43USB320A and will read as zero.  Bit 5 – P5 SC: Port 5 Status Change  Bit 4 – P4 SC: Port 4Status Change  Bit 3 – P3 SC: Port 3 Status Change  Bit 2 – P2 SC: Port 2 Status Change  Bit 1 – P1 SC: Port 1 Status Change  Bit 0 – H SC: Hub Status Change B i t 7 6543 2 1 0 $1FD7 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 HDR0 $1FD5 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 FDR0 $1FD4 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 FDR1 $1FD3 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 FDR2 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 $ – – P5 SC P4 SC P3 SC P2 SC P1 SC H SC HDR1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0

1443E–USB–4/04 Hub Endpoint 0 Byte Count Register – HBYTE_CNT0 Function Endpoint 0..2 Byte Count Register – FBYTE_CNT0..2 The contents of these registers stores the number of bytes to be sent or that was received by USB Hub and Function endpoints. This count includes the 16-bit CRC. To get the actual byte count of the data, subtract the count in the register by 2. Hub endpoint 1 has no byte count register.  Bit 7..5 – Reserved These bits are reserved in the AT43USB320A and will read as zero.  Bit 4..0 – BYTCT4..0: Byte Count – Length of Endpoint Data Packet B i t 7 654321 0 Hub EP0 $1FCF – – – BYTCT4 BYTCT3 BYTCT2 BYTCT1 BYTCT0 HBYTE_CNT0 Function EP0 $1FCD – – – BYTCT4 BYTCT3 BYTCT2 BYTCT1 BYTCT0 FBYTE_CNT0 Function EP1 $1FCC – – – BYTCT4 BYTCT3 BYTCT2 BYTCT1 BYTCT0 FBYTE_CNT1 Function EP2 $1FCB – – – BYTCT4 BYTCT3 BYTCT2 BYTCT1 BYTCT0 FBYTE_CNT2 Read/Write R R R R/W R/W R/W R/W R/W I n i t i a l V a l u e 0 000000 0

82 AT43USB320A

1443E–USB–4/04 Hub Endpoint 0 Service Routine Register – HCSR0 Function Endpoint 0 Service Routine Register – FCSR0  Bit 7..4 – Reserved These bits are reserved in the AT43USB320A and will read as zero.  Bit 3 – STALL SENT The USB hardware sets this bit after a STALL has been sent to the host. The firmware uses this bit when responding to a Get Status[Endpoint] request. It is a read only bit and that is cleared indirectly by writing a one to the STALL_SENT_ACK bit of the Control and Acknowl- edge Register.  Bit 2 – RX SETUP: Setup Packet Received This bit is used by control endpoints only to signal to the microcontroller that the USB hard- ware has received a valid SETUP packet and that the data portion of the packet is stored in the FIFO. The hardware will clear all other bits in this register while setting RX SETUP. If inter- rupt is enabled, the microcontroller will be interrupted when RX SETUP is set. After the completion of reading the data from the FIFO, firmware should clear this bit by writing a one to the RX_SETUP_ACK bit of the Control and Acknowledge Register.  Bit 1 – RX OUT PACKET The USB hardware sets this bit after it has stored the data of an OUT transaction in the FIFO. While this bit is set, the hardware will NAK all OUT tokens. The USB hardware will not over- write the data in the FIFO except for an early set-up. RX OUT Packet is used for the following operations: 1. Control write transactions by a control endpoint. 2. OUT transaction with DA TA1 PID to complete the status phase of a control endpoint. Setting this bit causes an interrupt to the microcontroller if the interrupt is enabled. FW clears this bit after the FIFO contents have been read by writing a one to the RX_OUT_PACKET_ACK bit of the Control and Acknowledge Register.  Bit 0 – TX COMPL: Transmit Completed This bit is used by a control endpoint hardware to signal to the microcontroller that it has suc- cessfully completed certain transactions. TX Complete is set at the completion of a: 1. Control read data stage. 2. Status stage without data stage. 3. Status stage after a control write transaction. This bit is read only and is cleared indirectly by writing a one to the TX_COMPLETE_ACK bit of the Control and Acknowledge Register. B i t 7654 3 2 1 0 Function EP0 $1FDF – – – – STALL SENT RX SETUP RX OUT PACKET TX COMPLETE HCSR0 Function EP0 $1FDD – – – – STALL SENT RX SETUP RX OUT PACKET TX COMPLETE FCSR0 Read/Write R R R R R R R R Initial Value 0 0 0 0 0 0 0 0

1443E–USB–4/04 Hub Endpoint 0 Control and Acknowledge Register – HCAR0 Function Endpoint 0 Control and Acknowledge Register – FCAR0 B i t 7 – DIR: Control transfer direction It is set by the microcontroller firmware to indicate the direction of a control transfer to the USB hardware. The FW writes to this bit location after it receives an RX SETUP interrupt. The hard- ware uses this bit to determine the status phase of a control transfer. 0 = control write or no data stage 1 = control read B i t 6 – DATA END When set to 1 by firmware, this bit indicate that the microcontroller has either placed the last data packet in FIFO, or that the microcontroller has processed the last data packet it expects from the Host. This bit is used by control endpoints only together with bit 4 (TX Packet Ready) to signal the USB hardware to go to the STATUS phase after the packet currently residing in the FIFO is transmitted. After the hardware completes the STATUS phase it will interrupt the microcontroller without clearing this bit. B i t 5 – FORCE STALL This bit is set by the microcontroller to indicate a stalled endpoint. The hardware will send a STALL handshake as a response to the next IN or OUT token, or whenever there is a control transfer without a Data Stage. The microcontroller sets this bit if it wants to force a STALL. A STALL is sent if any of the fol- lowing condition is encountered: 1. An unsupported request is received. 2. The host continues to ask for data after the data is exhausted. 3. The control transfer has no data stage. B i t 4 – TX PACKET READY: Transmit Packet Ready When set by the firmware, this bit indicates that the microcontroller has loaded the FIFO with a packet of data. This bit is cleared by the hardware after the USB Host acknowledges the packet. For ISO endpoints, this bit is cleared unconditionally after the data is sent. This bit is used for the following operations: 1. Control read transactions by a control endpoint. 2. IN transactions with DATA1 PID to complete the status phase for a control endpoint, when this bit is zero but Data End set high (bit 4). 3. By a BULK IN or ISO IN or INT IN endpoint. The microcontroller should write into the FIFO only if this bit is cleared. After it has completed writing the data, it should set this bit. This data can be of zero length. Bit 7 6 5 4 3 2 1 0 Hub EP0 $1FA7 DIR DATA END FORCE STALL TX PACKET READY STALL_ SENT_ ACK RX_ SETUP_ ACK RX_OUT_ PACKET_ ACK TX_ COMPLETE_ ACK HCAR0 Function EP0 $1FDD DIR DATA END FORCE STALL TX PACKET READY STALL_ SENT_ ACK RX_ SETUP_ ACK RX_OUT_ PACKET_ ACK TX_ COMPLETE_ ACK FCAR0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0

84 AT43USB320A

1443E–USB–4/04 Hardware clears this bit after it receives an ACK. If the interrupt is enabled and if the TX Com- plete bit is set, clearing the TX Packet Ready bit by the hardware causes an interrupt to the microcontroller. B i t 3 – STALL_SENT_ACK: Acknowledge Stall Sent Interrupt Firmware sets this bit to clear STALL SENT, CSR bit 3. The 1 written in the CSRACK3 bit is not actually stored and thus does not have to be cleared. B i t 2 – RX_SETUP_ACK: Acknowledge RX SETUP Interrupt Firmware sets this bit to clear RX SETUP, CSR bit2. The 1 written in the CSRACK2 bit is not actually stored and thus does not have to be cleared. B i t 1 – RX_OUT_PACKET_ACK: Acknowledge RX OUT PACKET Interrupt Firmware sets this bit to clear RX OUT PACKET, CSR bit1. The 1 written in the CSRACK1 bit is not actually stored and thus does not have to be cleared. B i t 0 – TX_COMPLETE_ACK: Acknowledge TX COMPLETE Interrupt Firmware sets this bit to clear TX COMPLETE, CSR bit0. The 1 written in the CSRACK0 bit is not actually stored and thus does not have to be cleared. Function Endpoint 1, 2 Service Routine Register – FCSR1, 2  Bit 7..4 – Reserved These bits are reserved in the AT43USB320A and will read as zero.  Bit 3 – STALL SENT The USB hardware sets this bit after a STALL has been sent to the host. The firmware uses this bit when responding to a Get Status[Endpoint] request. It is a read only bit and that is cleared indirectly by writing a one to the STALL_SENT_ACK bit of the Control and Acknowl- edge Register.  Bit 2 – Reserved This bit is reserved in the AT43USB320A and will read as zero.  Bit 1 – RX OUT PACKET The USB hardware sets this bit after it has stored the data of an OUT transaction in the FIFO. While this bit is set, the hardware will NAK all OUT tokens. The USB hardware will not over- write the data in the FIFO except for an early set-up. RX OUT Packet is used by a BULK OUT or ISO OUT or INT OUT endpoint. Setting this bit causes an interrupt to the microcontroller if the interrupt is enabled. FW clears this bit after the FIFO contents have been read by writing a one to the RX_SETUP_ACK bit of the Control and Acknowledge Register.  Bit 0 – TX COMPLETE: Transmit Completed This bit is used by the endpoint hardware to signal to the microcontroller that the IN transac- tion was completed successfully. This bit is read only and is cleared indirectly by writing a one to the TX_COMPLETE_ACK bit of the Control and Acknowledge Register. B i t 7 6 5 432 1 0 Function EP1 $1FDC – – – – STALL SENT – RX OUT PACKET TX COMPLETE FCSR1 Function EP2 $1FDB – – – – STALL SENT – RX OUT PACKET TX COMPLETE FCSR2 Read/Write R R R R R R R R Initial Value 0 0 0 0 0 0 0 0

1443E–USB–4/04 Function Endpoint 1, 2 Control and Acknowledge Register – FCAR1, 2  Bit 7 – Reserved This bit is reserved in the AT43USB320A and will read as zero.  Bit 6 – DATA END When set to 1 by firmware, this bit indicate that the microcontroller has either placed the last data packet in FIFO, or that the microcontroller has processed the last data packet it expects from the Host.  Bit 5 – FORCE STALL This bit is set by the microcontroller to indicate a stalled endpoint. The hardware will send a STALL handshake as a response to the next IN or OUT token. The microcontroller sets this bit if it wants to force a STALL. A STALL is send if the host continues to ask for data after the data is exhausted.  Bit 4 – TX PACKET RDY: Transmit Packet Ready When set by the firmware, this bit indicates that the microcontroller has loaded the FIFO with a packet of data. This bit is cleared by the hardware after the USB Host acknowledges the packet. For ISO endpoints, this bit is cleared unconditionally after the data is sent. The microcontroller should write into the FIFO only if this bit is cleared. After it has completed writing the data, it should set this bit. This data can be of zero length. The hardware clears this bit after it receives an ACK. If the interrupt is enabled and if the TX Complete bit is set, clearing the TX Packet Ready bit by the hardware causes an interrupt to the microcontroller.  Bit 3 – STALL_SENT_ACK: Acknowledge Stall Sent Interrupt Firmware sets this bit to clear STALL SENT, CSR bit 3. The 1 written in the CSRACK3 bit is not actually stored and thus does not have to be cleared.  Bit 2 – Reserved This bit is reserved in the AT43USB320A and will read as zero.  Bit 1 – RX_OUT_PACKET_ACK: Acknowledge RX OUT PACKET Interrupt Firmware sets this bit to clear RX OUT PACKET, CSR bit1. The 1 written in the CSRACK1 bit is not actually stored and thus does not have to be cleared.  Bit 0 – TX_COMPLETE_ACK: Acknowledge TX COMPLETE Interrupt Firmware sets this bit to clear TX COMPLETE, CSR bit0. The 1 written in the CSRACK0 bit is not actually stored and thus does not have to be cleared. Bit 7 6 5 4 3 2 1 0 Function EP1 $1FA4 – DAT A END FORCE STALL TX PACKET RDY STALL_SENT - ACK – RX_OUT_PACKET _ACK TX_COMPLETE _ACK FCAR1 Function EP2 $1FA3 – DAT A END FORCE STALL TX PACKET RDY STALL_SENT - ACK – RX_OUT_PACKET _ACK TX_COMPLETE -ACK FCAR2 Read/Write R R/W R/W R/W R/W R R/W R/W Initial Value 0 0 0 0 0 0 0 0

86 AT43USB320A

1443E–USB–4/04 USB Hub The hub in a USB system provides for the electrical interface between USB devices and the host. The major functions that the hub must supports are:  Connectivity  Power management  Device connect and disconnect  Bus fault detection and recovery  Full speed and low speed device support A hub consists of two major components: a hub repeater and a hub controller. The hub repeater is responsible for:  Providing upstream connectivity between the selected device and the Host  Managing connectivity setup and tear-down  Handling bus fault detection and recovery  Detecting connect/disconnect on each port The Hub Controller is responsible for:  Hub enumeration  Providing configuration information to the host  Providing status of each port to the host  Controlling each port per host command The first two tasks of the hub are similar to that of a USB function and are described in detail in the following section. The descriptions will cover the features of the AT43USB320A's hub and how to program it to make a USB-compliant hub. Control transactions for the hub control endpoint proceed exactly the same way as those described for the embedded function. The operation of the hub's endpoint 1 is fully imple- mented in the hardware and does not need any firmware support. Any status changes within the hub will automatically update hub endpoint 1, which will be sent to the host at the next IN token that is addressed to it. If no change has occurred, the interrupt endpoint will respond with a NAK.

1443E–USB–4/04 Hub General Registers Global State Register – GLB_STATE  Bit 7...5 – Reserved Bits These bits are reserved in the AT43USB320A and will read as zeros. B i t 4 – SUSP FLG: Suspend Flag This bit is set to 1 while the USB hardware is in the suspended state. This bit is a firmware read only bit. It is set and cleared by the USB hardware. B i t 3 – RESUME FLGL Resume Flag When the USB hardware receives a resume signal from the upstream device it sets this bit. This bit will stay set until the USB hardware completes the downstream resume signaling. This bit is a firmware read only bit. It is set and cleared by the USB hardware. B i t 2 – RMWUPE: Remote Wakeup Enable This bit is set if the host enables the hub's remote wakeup feature. B i t 1 – CONFG: Configured This bit is set by firmware after a valid SET_CONFIGURATION request is received. It is cleared by a reset or by a SET_CONFIGURATION with a value of 0. B i t 0 – HADD EN: Hub Address Enabled This bit is set by firmware after the status phase of a SET_ADDRESS request transaction so the hub will use the new address starting at the next transaction. Bit 7 6 5 4 3 2 1 0 $1FFB – – – SUSP FLG RESUME FLG RMWUPE CONFG HADD EN GLB_STATE Read/Write R R R R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0

88 AT43USB320A

1443E–USB–4/04 Hub Status Register In the AT43USB320A overcurrent detection and port power switch control output processing is done in firmware. The hardware is designed so that various types of hubs are possible just through firmware modifications. 1. Hub local power status, bits 0 and 2, are optional features and apply to hubs that report on a global basis. If this feature is not used, both these bits should be programmed to 0. To use this feature, the firmware needs to know the status of the local power supply, which requires an input pin and extra internal or external circuitry. 2. Hub overcurrent status, bits 1 and 3, apply to self powered hubs with bus powered SIE only, or hubs that are programmable as self/bus powered. The firmware should clear these two bits to 0. The firmware uses bits 1 and 3 to generate bit 0 of the Hub and Port Status Change Bitmap which is transmitted through the Hub Endpoint1 Data Register. Bit 0 of this register is a 1 whenever bit 1 or 3 of HSTATR is a 1. Hub Status Register – HSTR  Bit 7..4 – Reserved These bits are reserved in the AT43USB320A and will read as zero.  Bit 3 – OVLSC: Overcurrent Status Change 0 = No change has occurred on Overcurrent Indicator 1 = Overcurrent Indicator has changed  Bit 2 – LPSC: Hub Local Power Status Change 0 = No change has occurred on Local Power Status 1 = Local Power Status has changed  Bit 1 – OVI: Overcurrent Indicator 0 = All power operations normal 1 = An overcurrent exist on a hub wide basis  Bit 0 – LPS: Hub Local Power Status 0 = Local power supply is good 1 = Local power supply is lost (inactive) B i t 7 6543 2 1 0 $1FC7 – – – – OVLSC LPSC OVI LPS HSTR Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0

1443E–USB–4/04 Hub Port Control Register – HPCON B i t 7 – Reserved This bits is reserved in the AT43USB320A and will read as zero.  Bit 6..4 – HPCON2..0: Hub Port Control Command These bits are written by firmware to control the port states upon receipt of a Host request. Disable Port = ClearPortFeature(PORT_ENABLE) Action: USB hardware places addressed port in disabled state. Port 1 is placed in disabled state by firmware. Enable Port = SetPort Feature(PORT_ENABLE) Action: USB hardware places addressed port in enabled state. Firmware is responsible for placing Port 1 in enabled state. Reset and Enable Port = SetPort Feature(PORT_RESET) Action: USB hardware drives reset signaling through addressed port. USB hardware and firmware resets their embedded function registers to the default state. Suspend Port = SetPortFeature(PORT_SUSPEND) Action: USB hardware places port in idle state and stops propagating traffic through the addressed port. Firmware places Port 1 in suspend state by disabling its endpoints and plac- ing the peripheral function in its low power state. Resume Port = ClearPortFeature(PORT_SUSPEND) Action: USB hardware sends resume signaling to addressed port and then enables port. Firmware takes the embedded function out of the suspend state and enables Port 1's endpoints. B i t 3 – Reserved This bits is reserved in the AT43USB320A and will read as zero.  Bit 2..0 – HPCON2..0: Hub Port Address B i t 7 654 3 2 10 $1FC5 – HPCON2 HPCON1 HPCON0 – HPADD2 HPADD1 HPADD0 HPCON Read/Write R R/W R/W R/W R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit6 Bit5 Bit4 Action 0 0 0 Disable port 0 0 1 Enable port 0 1 0 Reset and enable port 0 1 1 Suspend port 1 0 0 Resume port

90 AT43USB320A

1443E–USB–4/04 These bits define which port is being addressed for the command defined by bits [2:0]. Bit2 Bit1 Bit0 Port addresses

101 P o r t 5

100 P o r t 4

011 P o r t 3

010 P o r t 2

001 P o r t 1

1443E–USB–4/04 Selective Suspend and Resume The host can selectively suspend and resume a port through the Set Port Feature (PORT_SUSPEND) and Clear Port Feature (PORT_SUSPEND). A port enters the suspend state after the microcontroller interprets the suspend request and sets the appropriate bits of the Hub Port Control Register, HPCON. From this point on he hub repeater hardware is responsible for proper actions in placing Ports [1:4] in the suspend mode. For Port 5, the embedded function port, the hardware will stop responding to any normal bus traffic, but the microcontroller firmware must place all external circuitry associated with the function in the low-power state. A port exits from the suspend state when the hub receives a Clear Port Feature (PORT_SUSPEND) or Set Port Feature (PORT_RESET). If the Clear Port Feature (PORT_SUSPEND) is directed towards Ports [1:4], the USB hardware drives a "K" down- stream for at least 20 ms followed by a low speed EOP. It then places the port in the enabled state. A Clear Port Feature (PORT_SUSPEND) to Port 1 (the embedded function) causes the firmware to wait 20 ms, take the embedded function out of the suspended state and then enable the port. The ports can also exit from the suspended state through a remote wakeup if this feature is enabled. For Ports [1:4], this means detection of a connect/disconnect or an upstream directed J to K signaling. Remote wakeup for the embedded function is initiated through an external interrupt at INT0.

92 AT43USB320A

1443E–USB–4/04 Hub Port Status Register The bits in this register are used by the microcontroller firmware when reporting a port's status through the Port Status Field, wPortStatus . Bits 3 (POCI) and 5 (PPSTAT) are used by the USB hardware and are the only two bits that the firmware should set or clear. All other bits should not be modified by the firmware. Hub Port Status Register – HPSTAT1:5  Bit 7 – Reserved This bit is reserved in the AT43USB320A and will read as zero.  Bit 6 – LSP: Low-speed Device Attached 0 = Full-speed device attached to this port 1 = Slow-speed device attached to this port Set to 0 for Port 1 (full-speed only). Set and cleared by the hardware upon detection of device at EOF2.  Bit 5 – PPSTAT: Port Power Status 0 = Port is powered OFF 1 = Port is powered ON Set to 1 for Port 1. Set and cleared based on present status of port power.  Bit 4 – PRSTAT: Port Reset Status 0 = Reset signaling not asserted 1 = Reset signaling asserted Set and cleared by the hardware as a result of initiating a port reset by Port Control Register.  Bit 3 – POCI: Port Overcurrent Indicator 0 = Power normal 1 = Overcurrent exist on port Set to 0 for Port 1. Set and cleared by firmware upon detection of an overcurrent or removal of an overcurrent.  Bit 2 – PSSTAT: Port Suspend Status 0 = Port not suspended 1 = Port suspended Set and cleared by the hardware as controlled through Port Control Register.  Bit 1 – PESTAT: Port Enable Status 0 = Port is disabled Bit 7 6 5 4 3 2 1 0 Port1 $1FB8 – LSP PPSTAT PRSTAT POCI PSSTAT PESTAT PCSTAT HPSTAT1 Port2 $1FB9 – LSP PPSTAT PRSTAT POCI PSSTAT PESTAT PCSTAT HPSTAT2 Port3 $1FBA – LSP PPSTAT PRSTAT POCI PSSTAT PESTAT PCSTAT HPSTAT3 Port4 $1FBB – LSP PPSTAT PRSTAT POCI PSSTAT PESTAT PCSTAT HPSTAT4 Port5 $1FBC – LSP PPSTAT PRSTAT POCI PSSTAT PESTAT PCSTAT HPSTAT5 Read/Write R R R/W R R/W R R R Initial Value 0 0 0 0 0 0 0 0

1443E–USB–4/04 1 = Port is enabled Set and cleared by the hardware as controlled through Port Control register.  Bit 0 – PCSTAT: Port Connect Status 0 = No device on this port 1 = Device present on this port Set to 1 for Port 1. Set and cleared by the hardware after sampling of connect status at EOF2. Hub Port State Register – HPSTAT1:5 These registers contain the state of the ports’ DP and DM pins, which will be sent to the host upon receipt of a GetBusState request.  Bit 7..2 – Reserved These bits are reserved in the AT43USB320A and will read as zero. B i t 1 – DPSTATE: DPlus State Value of DP at last EOF. Set and cleared by hardware at EOF2. Set to 1 for Port 1. B i t 0 – DMSTATE: DMinus State Value of DM at last EOF. Set and cleared by hardware at EOF2. Set to 0 for Port 1. B i t 7 6543 2 1 0 Port1 $1FA8 – – – – – – DPSTATE DMSTATE PSTATE1 Port2 $1FA9 – – – – – – DPSTATE DMSTATE PSTATE2 Port3 $1FAA – – – – – – DPSTATE DMSTATE PSTATE3 Port4 $1FAB – – – – – – DPSTATE DMSTATE PSTATE4 Port5 $1FAC – – – – – – DPSTATE DMSTATE PSTATE5 Read/Write R R R R R R R R Initial Value 0 0 0 0 0 0 0 0

94 AT43USB320A

1443E–USB–4/04 Hub Port Status Change Register – PSCR1..3 The microcontroller firmware uses the bits in this register to monitor when a port status change has occurred, which then gets reported to the host through the Port Change Field wPortChange. Except for bit 3, the Port Overcurrent Indicator Change, the bits in this register are set by the USB hardware. Otherwise, the firmware should only clear these bits.  Bit 7..5 – Reserved These bits are reserved in the AT43USB320A and will read as zero.  Bit 4 – RSTSC: Port Reset Status Change 0 = No change 1 = Reset complete This bit is set by the USB hardware after it completes RESET signaling which is initiated when the Reset and Enable Port command is detected at the Port Control Register, HPCON. The firmware sends this command when it decodes a SetPortFeature(PORT_RESET) request from the host. At EOF2 after the hardware completes the port reset, the hardware sets the Port Enable Sta- tus bit and clears the Port Reset Status bit of the Hub Port Status Register, HPSTAT. Cleared by firmware, ClearPortFeature(PORT_RESET).  Bit 3 – POCIC: Port Overcurrent Indicator Change 0 = No change has occurred on Overcurrent Indicator 1 = Overcurrent Indicator has changed This bit is relevant to hubs with individual overcurrent reporting only. The firmware sets this bit as a result of detecting overcurrent at the ports OVC# pin. The firmware clears bit through ClearPortFeature(PORT_OVER_CURRENT). For Port 1, this bit is always cleared.  Bit 2 – PSSC: Port Suspend Status Change 0 = No change 1 = Resume completed Port 1:4 is set by hardware upon completion of firmware initiated resume process. Port 5 is set by firmware 20 ms after the next EOF2 after completion of resume process. RESUME signal- ing is initiated through global resume, selective resume and remote wakeup. Cleared by firmware via host request ClearPortFeature(PORT_SUSPEND). B i t 7 6 543 2 1 0 Port1 $1FB0 – – – RSTSC POCIC PSSC PESC PCSC PSCR1 Port2 $1FB1 – – – RSTSC POCIC PSSC PESC PCSC PSCR2 Port3 $1FB2 – – – RSTSC POCIC PSSC PESC PCSC PSCR3 Port4 $1FB3 – – – RSTSC POCIC PSSC PESC PCSC PSCR4 Port5 $1FB4 – – – RSTSC POCIC PSSC PESC PCSC PSCR5 Read/Write R R R R R R R R Initial Value 0 0 0 0 0 0 0 0

1443E–USB–4/04  Bit 1 – PESC: Port Enable/Disable Status Change 0 = No change has occurred on Port Enable/Disable Status 1 = Port Enable/Disable status has changed Set by hardware due to babble, physical disconnect or overcurrent except for Port 5 in which case it is set by hardware at EOF2 due to hardware events. Cleared by firmware via Host request ClearPortFeature(PORT_ENABLE).  Bit 0 – PCSC: Port Connect Status Change 0 = No change has occurred on Current Connect Status 1 = Current Connect Status has changed This bit is set by hardware at EOF2 after it detects a connect or disconnect at a port, except for Port 5. Hardware sets this bit for Port 5 after a hub reset. Cleared by firmware via Host request ClearPortFeature(PORT_CONNECTION). Hub and Port Power Management For the utmost flexibility, the USB hardware of the AT43USB320A is designed to accommo- date hubs of various capacitance. Management of the downstream port power is also defined by the firmware: per port or global overcurrent sensing, individual or gang power switching. While the interface to the external power supply monitoring and switching is achieved through the microcontroller’s GPIO pins, the USB hardware of the AT43USB320A contains the cir- cuitry to handle all the possible combinations port power management tasks. Overcurrent sensing 1. Global Overcurrent Protection – In this mode, the Port Overcurrent Indicator and Port Overcurrent Indicator Change should be set to 0's. For the AT43USB320A an external solid state switch, such as the Micrel MIC2545-2, is required to switch power to the external USB ports. The FLG# output of the switch should be connected to PD0. When an overcurrent occurs, FLG is asserted and the firmware should set the Hub Overcurrent Indicator and Hub Overcurrent Indicator Change and switch off power to the hub. 2. Individual Port Over-current Protection – The Hub Overcurrent Indicator and Hub Overcurrent Indicator Change bits should be set to 0's. One MIC2026-2 is required for each two USB ports. Each of the FLG# outputs of the MIC2026-2 should be connected to an unused microcontroller port. An overcurrent is indicated by assertion of FLG#. The firmware sets the corresponding port's Overcurrent Indicator and the Overcurrent Indicator Change bits and switches off power to the port. At the next IN token from the Host, the AT43USB320A reports the status change. Port Power Switching 1. Gang Power Switching – One of the microcontroller I/O port pins must be pro- grammed as an output to control the external switch, PWRN. Switch ON is requested by the USB Host through the SetPortFeature(PORT_POWER) request. Switch OFF is executed upon receipt of a ClearPortFeature(PORT_POWER) or upon detecting an overcurrent condition. The firmware clears the Power Control Bit. Only if all of the Power Control Bits of ports 1 through 4 are cleared should the firmware de-assert the PWRN pin. 2. Individual Power Switching – One microcontroller I/O port pin must be assigned for each USB port to control the external switch, PWRxN, where x = 1, 2, 3, 4. Each of the Power Control Bits controls one PWRxN. 3. Multiple Ganged Overcurrent Protection – Overcurrent sensing is grouped physi- cally into one or more gangs, but reported individually. Figure 22 shows a simplified diagram of a power management circuit of an AT43USB320A based hub design with global overcurrent protection and ganged power switching.

96 AT43USB320A

Figure 22. Port Power Management tion. The USB hardware shuts off the oscillator and PLL. interrupt. As part of the ISR, the firmware clears the GLB_SUSP bit. embedded function, through an external interrupt.

1443E–USB–4/04 rupt to the microcontroller. The microcontroller starts executing where it left off and services the interrupt. As part of the ISR, the firmware clears the GLB SUSP bit. At completion of RESUME signaling, the USB hardware sets the Port Suspend Status Change bits of the Hub Port Status Change Registers. Selective Suspend and Resume See “Hub Port Control Register – HPCON” on page 89. Suspend and Resume Process Global Suspend The Host stops sending packets, the hardware detects this as global suspend signaling and stops all downstream signaling. Finally, the hardware asserts the GLB_SUSP interrupt. Global Resume The Host resumes signaling, the hardware detects this as global resume and propagates this signaling to all downstream ports. Finally, the hardware enables the oscillator and asserts the RSM interrupt. Hardware Firmware 1.Host stops sending packets 2. Global suspend signaling detected 3. Stop downstream signaling 4. Set GBL SUS bit → interrupt 5. Shut down any peripheral activity 6. Set Sleep Enable and Sleep Mode bits of MCUCR 7. Set GPIO to low power state if required 8. Set UOVCER bit 2 9. Execute SLEEP instruction 10. SLEEP bit detected 11. Shut off oscillator Hardware Firmware 1.Host resumes signaling 2. Resume signaling detected 3. Propagate signaling downstream 4. Enable oscillator 5. Set RSM bit → interrupt 6. Reset RSM and GBL SUSP bits 7. Restore GPIO states if required 8. Clear UOVCER bit 2 9. Enable peripheral activity

98 AT43USB320A

1443E–USB–4/04 Remote Wake-up, Downstream Ports The hardware detects a connect/disconnect/port resume and propagates resume signaling upstream. Finally, the hardware enables the oscillator and asserts the RSM interrupt. Remote Wake-up, Embedded Function The hardware detects an INT0/INT1 and propagates resume signaling upstream. Finally, the hardware enables the oscillator and asserts the RSM and FRWUP interrupts. Selective Suspend, Downstream Ports Hardware Firmware 1. Connect/disconnect/port resume detected 2. Propagate resume signaling 3. Enable Oscillator 4. Set RSM bit → interrupt 5. Reset RSM and GBL SUSP bits 6. Restore GPIO states if required 7. Clear UOVCER bit 2 8. Enable peripheral activity Hardware Firmware 1.External event activates INT0/INT1 2. Propagate resume signaling 3. Enable Oscillator 4. Set RSM and FRMWUP bits → interrupt 5. Clear GLB SUSP , RSM, FRMWUP bits 6. Restore GPIO states if required 7. Clear UOVCER bit 2 8. Enable peripheral activity Hardware Firmware 1. Set or Clear Port Feature PORT_SUSPEND decoded 2. Write HPCON[2:0] and HP ADD[2:0] bits 3. Suspend or resume port per command

1443E–USB–4/04 Selective Suspend, Embedded Function Selective Resume, Embedded Function Hardware Firmware 1. Set Port Feature PORT_SUSPEND decoded 2. Disable Port 5’s endpoints 3. Set GPIO to low power state if required Hardware Firmware 1. Clear Port Feature PORT_SUSPEND decoded 2. Clear Port 5 suspend status bit 3. Restore GPIO states if required 4. Wait 23 ms, then set enable status bit and suspend change bit 5. Enable Port 5 endpoints 6. Send updated port status at next IN to endpoint1

100 AT43USB320A

sure to absolute maximum rating conditions for extended periods may affect device reliability. Table 29. Absolute Maximum Ratings Table 30. Power Supply

Table 31. USB Signals: DPx, DMx Table 32. PA, PB, PC, PD

102 AT43USB320A

Note: XT AL2 must not be used to drive other circuitry. Note: 1. With external 27 Ω series resistor. Figure 23. Full-speed Load Table 33. Oscillator Signals: XTAL1, XTAL2 Table 34. USB Driver Characteristics, Full Speed Operation Table 35. USB Driver Characteristics, Low-speed Operation

Figure 24. Low-speed Downstream Port Load Note: 1. With 6.000 MHz, 100 ppm crystal.

1.5 K Ohm

Table 36. USB Source Timings, Full-speed Operation

104 AT43USB320A

Figure 25. Differential Data Jitter Figure 26. Differential-to-EOP Transition Skew and EOP Width Figure 27. Receiver Jitter Tolerance

Table 37. Hub Timings, Full-speed Operation Table 38. Hub Timings, Low-speed Operation

106 AT43USB320A

Table 39. Hub Event Timings

108 AT43USB320A

Figure 30. External Program Memory Read Timing Diagram Table 40. External Program Memory Read Timing

1443E–USB–4/04

Ordering Information

Ordering Code Package Operation Range AT43USB320A-AC 100 LQFP Commercial (0°C to 70°C)

110 AT43USB320A

1443E–USB–4/04 Packaging Information 100AA – LQFP

2325 Orchard Parkway

San Jose, CA 95131 TITLE DRAWING NO. R REV. 100AA, 100-lead, 14 x 14 mm Body Size, 1.4 mm Body Thickness, 0.5 mm Lead Pitch, Low Profile Quad Flat Pack (LQFP) C100AA 04/29/2002 PIN 1 IDENTIFIER 0˚~7˚ PIN 1 L C A1 A2 A D e E1 E B A – – 1.60 A1 0.05 – 0.15 A2 1.35 1.40 1.45 D 15.75 16.00 16.25 D1 13.90 14.00 14.10 Note 2 E 15.75 16.00 16.25 E1 13.90 14.00 14.10 Note 2 B 0.17 – 0.27 C 0.09 – 0.20 L 0.45 – 0.75 e 0.50 TYP Notes: 1. This package conforms to JEDEC reference MS-026, Variation AED. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.08 mm maximum. COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE

1443E–USB–4/04 Errata Sheet Errata (All Date Codes): Missed Watchdog Timer Reset Problem There is a synchronization problem between the watchdog clock and the AVR clock. Even though the clock inputs to both the watchdog timer and the AVR core are generated through the same crystal, the two clock sources are not going through the same PLL. The AVR is clocked at 12 MHz and the watchdog timer is clocked at 1MHz. The WDR (Watchdog Reset) instruction is a one-clock-cycle instruction. As such, when a watchdog timer reset occurs due to a WDR, the watchdog timer may miss the reset. This happens frequently if the AVR is clocked much faster than the watchdog timer. Fix/Workaround A workaround is to invoke the WDR repetitively to ensure that the wa tchdog timer will be able to receive the reset signal. If the AVR runs at 12 MHz, the WDR command must be invoked fourteen times back to back. The following is the sample code for resetting and arming the watchdog timer, assuming the AVR is running at 12 MHz: asm ( "ldi r16,15\\n WDR\\n WDR\\n WDR\\n WDR\\n WDR\\n WDR\\n WDR\\n WDR\\n WDR\\n WDR\\n WDR\\n WDR\\n WDR\\n out 0x21,r16 " ); To disarm and disable the watchdog, do the following: asm ( "ldi r16,0x18\\nldi r17,0x10\\n\\n out 0x21,r16\\n out 0x21,r17 " ); Please note that if the AVR runs at 24 MHz, the WDR should be invoked twenty-six times.

112 AT43USB320A

1443E–USB–4/04 Change Log Doc. Rev. Comments 1443E  Data Correction: timeout period data in Table 19 on page 51.  Information Change: UART does not support a 9-bit data mode. Changes were made to “Data Reception” on page 59, to Figure 19 on page 59 and Figure 20 on page 60. The “UART Control Register – UCR” on page 62.  Additions: Added an “Errata Sheet” on page 111 and a “Change Log” on page 112.

1443E–USB–4/04

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