AT43301-AU

AT43301_05 ATMEL | Alldatasheet

Document overview

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Technical content

Features

• Full Compliance with USB Spec Rev 1.1
• Four Downstream Ports
• Full-speed and Low-speed Data Transfers
• Bus-powered Controller
• Bus-powered or Self-powered Hub Operation
• Port Overcurrent Monitoring
• Port Power Switching
• 5V Operation with On-chip 3.3V Regulator
• 24-lead SOIC and 32-lead LQFP

Description

The AT43301 is a 5-port USB hub chip supporting one upstream and four down- stream ports. The AT43301 connects to an upstream hub or host/root hub via Port0, while the other ports connect to external downstream USB devices. The hub re-trans- mits the USB differential signal between Port0 and Ports[1:4] in both directions. The AT43301 is designed for very low-cost bus-powered or self-powered hub applications and is available in a 24-lead SOIC and a 32-lead LQFP packages. The 32-lead ver- sion of the AT43301, the AT43301-AC, has a 48 MHz clock input. The AT43301 supports the 12 Mb/s full speed as well as 1.5 Mb/s slow speed USB transactions. To reduce EMI, the AT43301’s oscillator frequency is 6 MHz even though some internal circuitry operates at 48 MHz. Figure 1-1. Pin Configurations 24-lead SOIC Top View 32-lead LQFP Top View VCC VSS CEXT1 OSC1 OSC2 LFT STAT PWR OVC LPSTAT TEST SELF/BUS NC DP4 DM4 DP3 DM3 DP2 DM2 DP1 DM1 DP0 DM0 VSS AT43301-SC NC DM4 DP4 VCC VSS CEXT1 NC NC DP0 DM0 VSS NC SELF/BUS TEST LPSTAT VSS OSC1 OSC2 LFT STAT PWR NC OVC NC DP3 DM3 DP2 DM2 DP1 DM1 NC AT43301-AC Low-cost USB Hub Controller AT43301 1137J–USB–01/06

1137J–USB–01/06 AT43301 The AT43301 consists of a Serial Interface Engine, a Hub Repeater, and a Hub Controller. The Serial Interface Engine’s tasks are:

• Manage the USB communication protocol
• USB signaling detection/generation
• Clock/data separation, data encoding/decoding, CRC generation/checking
• Data serialization/deserialization The Hub Repeater is responsible for:
• Providing upstream connectivity between the selected device and the host
• Managing connectivity setup and tear-down
• Handling bus fault detection and recovery
• Detecting connect/disconnect on each port The Hub Controller is responsible for:
• Hub enumeration
• Providing configuration information to the Host
• Providing status of each port to the Host
• Controlling each port per host command
• Managing port power supply 1.1 Block Diagram Figure 1-2. AT43301 Block Diagram Note: This document assumes that the reader is familiar with the Universal Serial Bus and therefore only describes the unique features of the AT43301 controller. For detailed information about the USB and its operation, the reader should refer to the Universal Serial Bus Specification Version 1.1, September 23, 1998. HUB CONTROLLER SERIAL INTERFACE ENGINE HUB REPEATER ENDPOINT 0 ENDPOINT 1 PORT 1 PORT 2 PORT 3 PORT 4 TO DOWNSTREAM DEVICES UPSTREAM PORT PORT 0

1137J–USB–01/06 AT43301 1.2 Pin Assignment Type: I = Input, IS = Input, Schmitt Trigger O = Output OD = Output, open drain B = Bi-directional V = Power supply, ground Table 1-1. 24-lead SOIC AT43301-SC Pin Assignment Pin Number Signal Type VCC V VSS V CEXT1 O OSC1 I OSC2 O LFT I STAT O PWR O OVC IS LPSTAT IS TEST I SELF/BUS IS VSS V DM0 B DP0 B DM1 B DP1 B DM2 B DP2 B DM3 B DP3 B DM4 B DP4 B NC

1137J–USB–01/06 AT43301 Table 1-2. 32-lead AT43301-AC Pin Assignment Pin Number Signal Type NC DM4 B DP4 B I VCC V VSS V CEXT O NC VSS V OSC1 I OSC2 O LFT I STAT O PWR O NC OVC IS LPSTAT IS TEST I SELF/BUS IS NC VSS V DM0 B DP0 B NC NC DM1 B DP1 B DM2 B DP2 B DM3 B DP3 B NC

1137J–USB–01/06 AT43301 Table 1-3. Signal Descriptions CEXT1 O External Capacitor. For proper operation of the on-chip regulator, a 0.27 µF capacitor must be connected to CEXT1. DP0 B Upstream Plus USB I/O. This pin should be connected to the CEXT1 pin through an external 1.5 kΩ pull-up resistor. DP0 and DM0 form the differential signal pin pairs connected to the USB host controller or an upstream Hub. DM0 B Upstream Minus USB I/O. DP[1:4] B Port Plus USB I/O. This pin should be connected to VSS through an external 15 kΩ resistor. DP[1:4] and DM[1:4] are the differential signal pin pairs to connect downstream USB devices. DM[1:4] B Port Minus USB I/O. This pin should be connected to VSS through an external 15 kΩ resistor. LFT I PLL Filter. For proper operation of the PLL, this pin should be connected through a 2.2 nF capacitor in parallel with a 100Ω resistor in series with a 10 nF capacitor to ground (VSS). LPSTAT I Local Power Status. Schmitt Trigger input pin that is used in the self-powered mode to indicate the condition of the local power supply. This pin should be connected to the local power supply through a 100 kΩ resistor. I 48 MHz Select, 32-lead LQFP only. This pin sets the clock input to the AT43301-AC. If it is tied low, a 48 MHz clock must be input to OSC1. If it is tied high (to CEXT1 or to 5V through a 47 kΩ resistor), a 6 MHz crystal must be connected between OSC1 and OSC2, or a 6 MHz clock input to OSC1. OSC1 I Oscillator Input. Input to the inverting 6 MHz oscillator amplifier. OSC2 O Oscillator Output. Output of the inverting oscillator amplifier. OVC I Port Overcurrent. This is the Schmitt Trigger input signal used to indicate to the AT43301 that there is a power supply problem with the ports. If OVC is asserted, the AT43301 will de-assert PWR and report the status to the USB Host. PWR O Power Switch. This is an output signal to enable or disable the external port power switch for the port power supply. PWR is de-asserted when an overcurrent is detected at OVC. SELF/BUS I Power Mode. Schmitt Trigger input pin to set power mode of hub. If high, the AT43301 works in the self-powered mode. If low, the bus-powered mode. STAT O Status. Output pin which is asserted by the AT43301 whenever it is enumerated. STAT is de-asserted when the hub enters the suspend state. An LED in series with a resistor can be connected to this pin to provide visual feedback to the user. TEST I Test. This pin has an internal pull up and should be left unconnected in the normal operating mode. VCC V 5V Power Supply from the USB. VSS V Ground. NC No Connect. This pin should be left unconnected.

1137J–USB–01/06 AT43301 Functional Description 2.1 Summary The Atmel AT43301 USB hub controller chip contains various features that makes it the ideal solution for very low-cost USB hubs. These features are: on-chip regulator, low-frequency oscil- lator, bus or self-powered operation, ganged port power switching and global overcurrent protection. Such a hub can be a stand-alone hub used with portable computers to allow conve- nient connectivity to standard desktop peripheral devices. Alternatively, the hub can be added to an existing non-USB peripheral such a keyboard. The AT43301 provides 4 downstream USB ports and can operate in a self-powered or bus-powered mode. 2.2 USB Ports The AT43301’s upstream port, Port0, is a full speed port. A 1.5 kΩ pull-up resistor to the 3.3V regulator output, CEXT, is required for proper operation. The downstream ports support both full-speed as well as low-speed devices. 15 kΩ pull down resistors are required at their inputs. Full speed signal requirements demand controlled rise/fall times and impedance matching of the USB ports. To meet these requirements, 22Ω resistors must be inserted in series between the USB data pins and the USB connectors. 2.3 Hub Repeater The Hub Repeater is responsible for port connectivity setup and teardown. It also supports exception handling such as bus fault detection and recovery, and connect/disconnect detection. Port0 is the root port and is connected to the root hub or an upstream hub. When a packet is received at Port0, the AT43301 propagates it to all the enabled downstream ports. Conversely, a packet from a downstream port is transmitted from Port0. The AT43301 supports downstream port data signaling at both 1.5 Mb/s and 12 Mb/s. Devices attached to the downstream ports are determined to be either full speed or low speed depending which data line (DP or DM) is pulled high. If a port is enumerated as low speed, its output buffers operate at a slew rate of 75-300 ns, and the AT43301 will not propagate any traffic to that port unless it is prefaced with a preamble PID. Low speed data following the preamble PID is propa- gated to both low- and full-speed devices. The AT43301 will enable low-speed drivers within four full-speed bit times of the last bit of a preamble PID, and will disable them at the end of an EOP. The upstream traffic from all ports is propagated by Port0 using the full speed 4-20ns slew rate drivers. All the AT43301 ports independently drive and monitor their DP and DM pins so that they are able to detect and generate the ‘J’, ‘K’, and SE0 bus signaling states. Each hub port has single- ended and differential receivers on its DP and DM lines. The ports’ I/O buffers comply with the voltage levels and drive requirements as specified in the USB Specifications Rev 1.0. The Hub Repeater implements a frame timer which is timed by the 12 MHz USB clock and gets reset every time an SOF token is received from the host. 2.4 Serial Interface Engine The Serial Interface Engine handles the USB communication protocol. It performs the USB clock/data separation, the NRZI data encoding/decoding, bit stuffing, CRC generation and checking, USB packet ID decoding and generation, and data serialization and de-serialization.

1137J–USB–01/06 AT43301 The on-chip phase locked loop generates the high frequency clock for the clock/data separation circuit. 2.5 Power Management A hub is allowed to draw up to 500 mA of power from the host or upstream hub. The AT43301’s itself and its external circuitry typically consume about 24 mA. Therefore, in the bus-powered mode, 100 mA is available for each of the hub’s downstream devices. In the self-powered mode, an external power supply is required which must be capable of supplying 500 mA per port. The power supplied to the ports is monitored and controlled by the AT43301. The AT43301 reports overcurrent on a global basis. The overcurrent signal, which needs to be detected by an external device, is read through the OVC pin. A logic low at OVC is interpreted as an overcurrent condition. This could be caused by an overload, or a short circuit, and causes the AT43301 to set the Over-Current Indicator bit of the Hub Status Field, wHubStatus, as well as the Over-Current Indicator Change bit of the Hub Change Field, wHubChange. At the same time, power to the ports is switched off by de-asserting PWR. An external device is needed to perform the actual switching of the ports’ power under control of the AT43301. Any type of suitable switch or device is acceptable. However, the switch should have a low-voltage drop across it even when the port absorbs full power. In its simplest form, this switch can be a high side MOSFET switch. The advantage of using a MOSFET switch is its very low-voltage drop. The power control pin, PWR, is asserted only when a SetPortFeature[PORT-POWER] request is received from the host. PWR is de-asserted under the following conditions: Power up Reset and initialization Overcurrent condition Requested by the host though a ClearPortFeature[PORT_POWER] for ALL the ports 2.5.1 Self-powered Mode In the self-powered mode, power to the downstream ports must be supplied by an external power supply. This power supply must be capable of supplying 500 mA per port or 2A total with good voltage tolerance and regulation. At full hub operating power, that is all downstream ports drawing 500 mA each, the minimum voltage at the downstream port connector must be 4.75V. The USB specification requires that the voltage drop at the power switch and board traces be no more than 100 mV. A good conservative maximum drop at the power switch itself should be no more than 75 mV. Careful design and selection of the power switch and PC board layout is required to meet the specifications. When using a MOSFET switch, its resistance must be 40 mΩ or less under worst case conditions. A suitable MOSFET switch for an AT43301 based hub is an integrated highside MOSFET switch such as the Micrel MIC2505. 2.5.2 Bus-Powered Mode In the bus-powered mode all the power for the hub itself as well as the downstream ports is sup- plied by the root hub or upstream hub through the USB. Only 100 mA is available for each of the hub’s downstream devices and therefore only low-power devices are supported. The power switch works exactly like the self-powered mode, except that the allowable switch resistance is higher: 140 mΩ or less under the worst case condition. An example of a suitable high side switch for a bus-powered hub is the Micrel MIC2525.

1137J–USB–01/06 AT43301 2.6 Hub Controller The Hub Controller of the AT43301 provides the mechanism for the host to enumerate the hub and the AT43301 to provide the host with its configuration information. It also provides a mecha- nism for the host to monitor and control the downstream ports. The Hub Controller supports two endpoints, Endpoint0 and Endpoint1. The Hub Controller maintains a status register, Controller Status Register, which reflects the AT43301's current settings. At power up, all bits in this register will be set to 0’s. 2.6.1 Endpoint 0 Endpoint 0 is the AT43301’s default endpoint used for enumeration of the hub and exchange of configuration information and requests between the host and the AT43301. Endpoint 0 supports control transfers. The Hub Controller supports the following descriptors through Endpoint 0: Device Descriptor, Configuration Descriptor, Interface Descriptor, Endpoint Descriptor, and Hub Descriptor. These descriptors are described in detail elsewhere in this document. Standard USB Device Requests and class-specific Hub Requests are also supported through Endpoint 0. There is no endpoint descriptor for Endpoint0. 2.6.2 Endpoint 1 Endpoint1 is used by the Hub Controller to send status change information to the host. This end- point supports interrupt transfers. The Hub Controller samples the changes at the end of every frame at time marker EOF2 in prep- aration for a potential data transfer in the subsequent frame. The sampled information is stored in a byte wide register, the Status Change Register, using a bitmap scheme. Table 2-1. Controller Status Register Bit Function Value Set to 0 or 1 by a Set_Configuration Request Hub is not currently configured Hub is currently configured Hub remote wakeup status Set to 0 or 1 by ClearFeature or SetFeature request. Default value is 0. Hub is currently not enabled to request remote wakeup Hub is currently enabled to request remote wakeup Endpoint0 STALL status Endpoint0 is not stalled Endpoint0 is stalled Endpoint1 STALL status Endpoint1 is not stalled Endpoint1 is stalled

1137J–USB–01/06 AT43301 Each bit in the Status Change Register corresponds to one port as shown below: An IN Token packet from the host to Endpoint 1 indicates a request for port change status. If the hub has not detected any change on its ports, or any changes in itself, then all bits in this regis- ter will be 0 and the Hub Controller will return a NAK to requests on Endpoint1. If any of bits 0-4 is 1, the Hub Controller will transfer the whole byte. The Hub Controller will continue to report a status change when polled until that particular change has been removed by a ClearPortFeature request from the Host. No status change will be reported by Endpoint 1 until the AT43301 has been enumerated and configured by the host. 2.7 Oscillator and Phase-Locked-Loop All the clock signals required to run the AT43301 are derived from an on-chip oscillator. To reduce EMI and power dissipation in the system, the AT43301 is designed to operate with a 6 MHz crystal. An on-chip PLL generates the high frequency for the clock/data separator of the Serial Interface Engine. In the suspended state, the oscillator circuitry is turned off. To assure quick startup, a crystal with a high Q, or low ESR, should be used. To meet the USB hub fre- quency accuracy and stability requirements for hubs, the crystal should have an accuracy and stability of better than 100 ppm. Even though the oscillator circuit would work with a ceramic res- onator, its use is not recommended because a resonator would not have the frequency accuracy and stability. A 6 MHz parallel resonance quartz crystal with a load capacitance of approximately 10 pF is rec- ommended. The oscillator is a special low-power design and in most cases no external capacitors and resistors are necessary. If the crystal requires a higher value capacitance, exter- nal capacitors can be added to the two terminals of the crystal and ground to meet the required value. If the crystal used cannot tolerate the drive levels of the oscillator, a series resistor between OSC2 and the crystal pin is recommended. The clock can also be externally sourced. In this case, connect the clock source to the OSC1 pin, while leaving OSC2 pin floating. The switching level at the OSC1 pin can be as low as 0.47V (see “Electrical Specification” on page 12) and a CMOS device is required to drive this pin to maintain good noise margins at the low switching level. The 32-lead AT43301-AC can also be driven by a 48 MHz external clock instead. In this case, connect the 48N pin to ground. Table 2-2. Status Change Register Bit Function Value Meaning Hub status change No change in status Change in status detected Port1 status change No change in status Change in status detected Port2 status change No change in status Change in status detected Port3 status change No change in status Change in status detected Port4 status change No change in status Change in status detected 5-7 Reserved 000 Default values

1137J–USB–01/06 AT43301 For proper operation of the PLL, an external RC filter consisting of a series RC network of 100Ω and 10 nF in parallel with a 2 nF capacitor must be connected from the LFT pin to VSS. 2.8 Status Pin The status pin, STAT, is provided to allow feedback to the user. If an LED and a series resistor is connected between STAT and VCC, the LED will light when the hub is enumerated. During an overcurrent condition, the LED will blink. It will continue to blink until the host turns off the power to the ports or until the hub is re-enumerated. The I/O pins of the AT43301 should not be directly connected to voltages less than VSS or more than the voltage at the CEXT pins. If it is necessary to violate this rule, insert a series resistor between the I/O pin and the source of the external signal source that limits the current into the I/O pin to less than 0.2 mA. Under no circumstance should the external voltage exceed 5.5V. To do so will put the chip under excessive stress. Figure 2-3. External Oscillator and PLL Circuit 2.9 Power Supply The AT43301 is powered from the USB bus, but has an internal voltage regulator to supply the 3.3V operating power to its circuitry. For proper operation, an external high quality, low ESR, 0.27 µF, or larger, capacitor should be connected to the output of the regulator, CEXT1 and ground. The CEXT1 pin can also be used to supply the voltage to the 1.5 kΩ pull up resistor at Port 0’s DP pin. To provide the best operating condition for the AT43301, careful consideration of the power sup- ply connections are recommended. Use short, low impedance connections to all power supply lines: VCC and VSS. Use sufficient decoupling capacitance to reduce noise: 0.1 µF of high quality ceramic capacitor soldered as close as possible to the VCC and VSS package pins are recommended. The AT43301 can also operate directly off a 3.3V power supply. In this case, leave the VCC pin floating and connect the 3.3V power to CEXT1. AT43301 OSC1 OSC2 LFT

6.000 MHz

1137J–USB–01/06 AT43301 Electrical Specification *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 3.2 DC Characteristics The values shown in this table are valid for TA = 0°C to 85°C, VCC = 4.4V to 5.25V, unless otherwise noted. 3.1 Absolute Maximum Ratings* Symbol Parameter Condition Min Max Unit VCC5 5V Power Supply 5.5 V VI DC Input Voltage -0.3V VCEXT + 0.3 4.6 max V VO DC Output Voltage -0.3 VCEXT + 0.3 4.6 max V TO Operating Temperature -40 +125 TS Storage Temperature -65 +150 Table 3-1. Power Supply Symbol Parameter Condition Min Max Unit VCC 5V Power Supply 4.4 5.25 V ICC 5V Supply Current mA ICCS Suspended Device Current 150 µA Table 3-2. USB Signals: DPx, DMx Symbol Parameter Condition Min Max Unit VIH Input Level High (driven) 2.0 V VIHZ Input Level High (floating) 2.7 3.6 V VIL Input Level Low 0.8 V VDI Differential Input Sensitivity DPx and DMx 0.2 V VCM Differential Common Mode Range 0.8 2.5 V VOL1 Static Output Low RL of 1.5 kΩ to 3.6V 0.3 V VOH1 Static Output High RL of 15 kΩ to GND 2.8 3.6 V VCRS Output Signal Crossover 1.3 2.0 V CIN Input Capacitance pF

1137J–USB–01/06 AT43301 Note: OSC2 must not be used to drive other circuitry. 3.3 AC Characteristics Note: 1. With external 22Ω series resistor. Table 3-3. PWR, STAT, OVC Symbol Parameter Condition Min Max Unit VOL2 Output Low Level, PWR, STAT IOL = 4 mA 0.5 V COUT Output Capacitance

1 MHz

0.3VCEXT V VIH3 Input High Level 0.7VCEXT V COUT Output Capacitance Output High Level, PWR IOH = 4 mA VCEXT - 0.5 V Table 3-4. Oscillator Signals: OSC1, OSC2 Symbol Parameter Condition Min Max Unit VLH OSC1 Switching Level 0.47 1.20 V VHL OSC1 Switching Level 0.67 1.44 V CX1 Input Capacitance, OSC1 pF CX2 Output Capacitance, OSC2 pF C12 OSC1/2 Capacitance pF tsu Start-up Time

6 MHz, fundamental

VCC = 3.3V, 6 MHz crystal, 100Ω equiv series resistor 150 µW Table 3-5. DPx, DMx Driver Characteristics, Full Speed Operation Symbol Parameter Condition Min Max Unit tR Rise Time CL = 50 pF ns tF Fall Time CL = 50 pF ns tRFM tR/tF Matching 110 ZDRV Driver Output Resistance(1) Steady state drive Ω

1137J–USB–01/06 AT43301 Note: 1. With 6.000 MHz, 100 ppm crystal. Table 3-6. DPx, DMx Source Timings, Full Speed Operation Symbol Parameter Condition Min Max Unit tDRATE Full Speed Data Rate(1) Average bit rate 11.97 12.03 Mb/s tFRAME Frame Interval(1) 0.9995 1.0005 ms tRFI Consecutive Frame Interval Jitter(1) No clock adjustment 42.0 ns tRFIADJ Consecutive Frame Interval Jitter(1) With clock adjustment 126.0 ns tDJ1 tDJ2 Source Diff Driver Jitter To Next Transition For Paired Transitions -3.5 -4.0 3.5 4.0 ns ns tFDEOP Source Jitter for Differential Transition to SEO Transitions -2.0 5.0 ns tJR1 tJR2 Recvr Data Jitter Tolerance To Next Transition For Paired Transitions -18.5 -9.0 18.5 9.0 ns ns tFEOPT Source SEO interval of EOP 160.0 175.0 ns tFEOPR Receiver SEO interval of EOP 82.0 ns tFST Width of SEO interval during differential transition 14.0 ns Table 3-7. DPx, DMx Driver Characteristics, Low-speed Operation Symbol Parameter Condition Min Max Unit tR Rise time CL = 200 - 600 pF 75.0 300.0 ns tF Fall time CL = 200 - 600 pF 75.0 300.0 ns tRFM tR/tF matching 80.0 125.0 Table 3-8. DPx, DMx Hub Timings, High-Speed Operation Symbol Parameter Condition Min Max Unit tHDD2 Hub Differential Data Delay without Cable 44.0 ns tHDJ1 tHDJ2 Hub Diff Driver Jitter To Next Transition For Paired Transitions -3.0 -1.0 3.0 1.0 ns ns tFSOP Data Bit Width Distortion after SOP -5.0 5.0 ns tFEOPD Hub EOP Delay Relative to tHDD 15.0 ns tFHESK Hub EOP Output Width Skew -15.0 15.0 ns

1137J–USB–01/06 AT43301 Table 3-9. DPx, DMx Hub Timings, Low-speed Operation Symbol Parameter Condition Min Max Unit tLHDD Hub Differential Data Delay 300.0 ns tLHDJ1 tLHDJ2 tLUHJ1 tLUHJ2 Downstr Hub Diff Driver Jitter To Next Transition, downst For Paired Transitions, downst To Next Transition, upstr For Paired Transitions, upstr -45.0 -15.0 -45.0 -45.0 45.0 15.0 45.0 45.0 ns ns ns ns tSOP Data Bit Width Distortion after SOP -60.0 60.0 ns tLEOPD Hub EOP Delay Relative to tHDD 200.0 ns tLHESK Hub EOP Output Width Skew -300.0 300.0 ns Table 3-10. Hub Event Timings Symbol Parameter Condition Min Max Unit tDCNN Time to Detect a Downstream Port Connect Event Awake Hub Suspended Hub 2.5 2.5 2000.0 12000.0 µs µs tDDIS Time to Detect a Disconnect Event on Downstream Port Awake Hub Suspended Hub 2.5 2.5 2.5 10000.0 µs µs tURSM Time from Detecting Downstream Resume to Rebroadcast 100.0 µs tDRST Duration of Driving Reset to a Downstream Device Only for a SetPortFeature (PORT_RESET) request 10.0 20.0 ms tURLK Time to Detect a Long K from Upstream 2.5 100.0 µs tURLSEO Time to Detect a Long SEO from Upstream 2.5 10000.0 µs tURPSEO Duration of repeating SEO Upstream FS bit time

1137J–USB–01/06 AT43301 Figure 4-7. Hub Differential Delay, Differential Jitter, and SOP Distortion Hub Differential Jitter: THDJ1 = THDDX(J) - THDDX(K) or THDDX(K) - THDDX(J) Consecutive Transitions THDJ2 = THDDX(J) - THDDX(J) or THDDX(K) - THDDX(K) Paired Transitions Bit After Sop Width Distortion (Same as Data Jitter for Sop and Next J Transition): TSOP = THDDX(NEXTJ) - THDDX(SOP) Low-speed timings are determined in the same way for: TLHDD, TLDHJ1, TLDJH2, TLUHJ1, TLUJH2, and TLSOP CROSSOVER POINT DIFFERENTIAL DATA LINES A. DOWNSTREAM HUB DELAY WITH CABLE 50% POINT OF INITIAL SWING UPSTREAM END OF CABLE HUB DELAY DOWNSTREAM THDD1 CROSSOVER POINT DOWNSTREAM PORT CROSSOVER POINT HUB DELAY UPSTREAM THDD2 UPSTREAM PORT VSS VSS VSS VSS B. UPSTREAM HUB DELAY WITHOUT CABLE CROSSOVER POINT DOWNSTREAM PORT CROSSOVER POINT HUB DELAY UPSTREAM THDD1, THDD2 UPSTREAM PORT OR END OF CABLE VSS VSS C. UPSTREAM HUB DELAY WITH OR WITHOUT CABLE

1137J–USB–01/06 AT43301 Figure 4-8. Hub EOP Delay and EOP Skew EOP Delay: TEOPD = TEOP - THDDX EOP Skew: THESK = TEOP + -TEOP- Low-speed timings are determined in the same way for: TLEOPD and TLHESK CROSSOVER POINT EXTENDED DOWNSTREAM PORT A. DOWNSTREAM EOP DELAY WITH CABLE 50% POINT OF INITIAL SWING UPSTREAM END OF CABLE UPSTREAM PORT VSS VSS VSS VSS B. DOWNSTREAM EOP DELAY WITHOUT CABLE DOWNSTREAM PORT UPSTREAM PORT OR END OF CABLE VSS VSS C. UPSTREAM EOP DELAY WITH OR WITHOUT CABLE TEOP- TEOP+ CROSSOVER POINT EXTENDED DOWNSTREAM PORT TEOP- TEOP+ CROSSOVER POINT EXTENDED CROSSOVER POINT EXTENDED TEOP- TEOP+ CROSSOVER POINT EXTENDED

1137J–USB–01/06 AT43301 Schematic Diagrams The following pages show schematic diagrams of an AT43301 based bus-powered hub and self- powered hub. Figure 5-1. Bus-powered Hub VBUS DM1 DP1 DM2 DP2 DM3 DP3 DM4 DP4 PWR OVC VBUS 6.000MHz 100 0.01UF 2.2nF 1.5K FB R9 22 R10 22 R11 R12 R13 22 R14 22 470 LED C12 4.7UF RP1 15K 0.27UF USB-B JP1 R16 47K AT43301 DM0 DP0 DM1 DP1 DM2 DP2 DM3 DP3 DM4 DP4 VSS VSS OSC1 OSC2 VCC CEXT LFT PWR OVC LPSTAT TEST STAT SELF/BUS NC 1N4148 L11 FB

1137J–USB–01/06 AT43301 Figure 5-2. Bus-powered Hub VBUS VBUS PWR OVC DP1 DM2 DM4 DM1 DP2 DM3 DP3 DP4 47uF 47uF C10 47uF C11 47uF MIC2525-2 EN FLG GND IN OUT NC OUT NC JP3 USB-2A L13 FB FB 0.1uF L2 FB 0.1uF L12 FB FB 0.1uF JP2 USB-2A 0.1uF L15 FB FB L14 FB

1137J–USB–01/06 AT43301 Figure 5-3. Self-powered Hub VBUS VLOCAL DM1 DP1 DM2 DP2 DM3 DP3 DM4 DP4 PWR OVR 6.000MHz 100 0.01UF 2.2nF 1.5K FB 0.27UF R9 22 R10 22 R11 R12 R13 22 R14 22 47K LED USB-B JP1 RP1 15K R16 47K 2N4401 AT43301 DM0 DP0 DM1 DP1 DM2 DP2 DM3 DP3 DM4 DP4 VSS VSS OSC1 OSC2 VCC CEXT LFT PWR OVC LPSTAT TEST STAT SELF/BUS NC R35 470 470 L11 FB

1137J–USB–01/06 AT43301 Figure 5-4. Self-powered Hub VLOCAL PWR OVC DP4 DM3 DP1 DP3 DM1 DM2 DP2 DM4 100 UF 100 UF C10 100 UF C11 100 UF MIC2505-2 CTL FLG GND IN OUT IN OUT GATE CON2 4.7 UF C15 0.1 UF C14 JP2 USB-2A FB 0.1uF FB L12 FB 0.1uF L2 FB L15 FB L14 FB 0.1uF L13 FB JP3 USB-2A 0.1uF FB

1137J–USB–01/06 AT43301

Ordering Information

6.1 AT43301 Standard Package Options Ordering Code Package Operation Range AT43301-SC 24S – SOIC Commercial (0°C to 70°C) AT43301-AC 32AA – LQFP Commercial (0°C to 70°C) 6.2 AT43301 Green Package Options (Pb/Halide-free/RoHS Compliant) Ordering Code Package Operation Range AT43301-AU 32AA – LQFP Industrial (-40°C to 85°C) AT43301-SU 24S – SOIC Industrial (-40°C to 85°C) Package Type 24S 24-lead (0.300 in. body) Plastic Gull Wing Small Outline Package (SOIC) 32AA 32-lead, Low-profile (1.4 mm) Plastic Quad Flat Package (LQFP)

1137J–USB–01/06 AT43301 Packaging Information 7.1 32AA – LQFP

2325 Orchard Parkway

San Jose, CA 95131 TITLE DRAWING NO. R REV. 32AA, 32-lead, 7 x 7 mm Body Size, 1.4 mm Body Thickness, 0.8 mm Lead Pitch, Low Profile Plastic Quad Flat Package (LQFP) B 32AA 10/5/2001 PIN 1 IDENTIFIER 0˚~7˚ PIN 1 L C A D e E B COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE Notes: 1. This package conforms to JEDEC reference MS-026, Variation BBA. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum. A 1.60 0.05 0.15 1.35 1.40 1.45 D 8.75 9.00 9.25 6.90 7.00 7.10 Note 2 E 8.75 9.00 9.25 6.90 7.00 7.10 Note 2 B 0.30 0.45 C 0.09 0.20 L 0.45 0.75 e

0.80 TYP

1137J–USB–01/06 AT43301 7.2 24S – SOIC 0º ~ 8º PIN 1 ID PIN 1 06/17/2002 San Jose, CA 95131 TITLE DRAWING NO. REV. 24S, 24-lead (0.300" body) Plastic Gull Wing Small Outline (SOIC) B 24S R COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A 2.65 0.10 0.30 D 10.00 10.65 7.40 7.60 E 15.20 15.60 B 0.33 0.51 L 0.40 1.27 0.23 0.32 e

1.27 BSC

B D e E A L

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