AT40KEL040 ATMEL | Alldatasheet
Document overview
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Technical content
Features
- SRAM based FPGA Dedicated to Space Use
- SEE Hardened Cells (configuration RAM, FreeRAM, DFF, JTAG, I/O buffers) Remove the need for Triple Modular Redundancy (TMR)
- Produced on Rad Hard 0.35µm CMOS Process
- Functionally and Pin Compatible with the Atmel Commercial and Military AT40K Series
- High Performance – 46K Available ASIC gates (50% typ. routable) – 60 MHz Internal Performance – 20 MHz System Performance – 30 MHz Array Multipliers – 18 ns FreeRAM ™ access time – Internal Tri-state Capability in Each Cell
- FreeRAM – 18432 Bits of Distributed SRAM Independent of Logic Cells – Flexible, Single/Dual Port, Synchronous/Asynchronous 32x4 RAM blocks
- 8 Global Clocks and 4 Additional Dedicated PCI Clocks – Fast, Low Skew Clock Distribution – Programmable Rising/Falling Edge Transitions – Distributed Clock Shutdown Capability for Low Power Management
- Global Reset Option
- 384 PCI Compliant I/Os – Programmable Output Drive – Fast, Flexible Array Access Facilitates Pin Locking
- Package Options – MQFPF160 – MQFPF256
- Design Software (System Designer) – Combination of Atmel internally developed tools, and industry standard design tools – Fast and Efficient Synthesis – Efficient Integration (Libraries, Interface, Full Back-annotation) – Over 75 Automatic Component Generators Create Thousands of Speed and Area Optimized Logic and RAM Functions – Automatic/Interactive Multi-chip Partitioning
- Supply Voltage 3.3V
- AT40KFL040 is a 5V Tolerant Version
- No Single Event Latch-up below a LET Threshold of 70 MeV/mg/cm2
- Tested up to a Total Dose of 300 krads (Si) according to MIL STD 883 Method 1019
- Quality Grades – QML -Q and -V with SMD 5962-03250 – ESCC with 9304/008
- Design Kit (AT40KEL-DK) Including: – A Board with the RH FPGA (MQFPF160 or MQFPF256) – A configuratio n memory (AT17 Atmel EEPROM) – Design software and documentation – ISP cable and software
- Easy Migration to Atmel Gate Arrays for High Volume Production Note: All features and characteristics described for AT40KEL040 in this document, also apply to the AT40KFL040 unless specified otherwise. Rad Hard Reprogrammable FPGAs with FreeRAM AT40KEL040 AT40KFL040
2 AT40KEL040
space standard packages and support 3.3V. The AT40KFL040 is a 5V tolerant version. the IDS datasheet for other supported tools. based) designs by implementing a variety of compute-intens ive, arithmetic functions. created using Atmel’s macro generator tool. reconfiguration, without loss of data, on-the- fly) for building adaptive logic and systems. Table 1. AT40KEL040
4155I–AERO–06/06 proven functions. The Automatic Component Generators work seamlessly with industry- standard schematic and synthesis tools to cr eate the fastest, most efficient designs available. The patented AT40KEL040 series architecture employs a symmetrical grid of small yet powerful cells connected to a flexible busing network. Independentl y controlled clocks and resets govern every column of cells. The array is surrounded by programmable I/O. Devices offer 46,000 usable ASIC gates, and have 3,056 registers. AT40K series FPGAs utilize a reliable 0.35µm single-poly, 4-metal CMOS process and are 100% fac- tory-tested. Atmel’s PC- and workstation-based integrated development system (IDS) is used to create AT40KEL040 series designs. Multiple design entry methods are sup- ported. The Atmel architecture was de veloped to provide the high est levels of performance, functional density and design fl exibility in an FPGA. The ce lls in the Atmel array are small, efficient and can implement any pair of Boolean functions of (the same) three inputs or any single Boolean function of four inputs. The cell’s small size leads to arrays with large numbers of cells, greatly multiply ing the functionality in each cell. A simple, high-speed busing network provides fast, efficient communicati on over medium and long distances. AT40KEL040 Configurator Statistics extracted from configuration bitstreams show that the maximum needed size is 1Mbit. In order to keep the maximum number of pins assigned to signals, it is recommended to use a serial configuration interface. This is the reason why Atmel proposes a 1Mbit serial EEPROM for configuring the AT40KEL040, the AT17LV010-10DP which is also a 3.3V bias chip. It is packaged into a 28-pin DIL Flat Pack 400mils wide. This memory has been tested for total dose under bias and unbiased conditions, exhib- iting far better results when unbiased; this is the reason why it is recommended to switch off the memory when it is not in the configuration mode. In addition, heavy ions tests have shown that the data stored in the memory cells are not corrupted eventhough errors may be detected while downloading the bitstream; this is the result of the data serializ ation from the parallel memory plan; therefore, it is recom- mended to use the FPGA CRC while configuring it, and to resume the configuration when an error is detected.
4 AT40KEL040
At the heart of the Atmel architecture is a sy mmetrical array of identical cells (Figure 1). Note: 1. The right-most column can only be used as single-port RAM. Figure 1. Symmetrical Array Surrounded by I/O Note: AT40K has registered I/Os. Group enable every sector for tri-states on obuf’s.
Figure 2. Floorplan (Representative Portion)(1) the integrated development system (IDS) tool.
6 AT40KEL040
implemented through pass gates in the ce ll-bus interface (see following page). Some of the bus resource on the AT40KE L040 is used as a dual-function resource. buses in an efficient manner. Table 2. Dual-function Buses
Figure 3. Busing Plane (One of Five)
8 AT40KEL040
Cell Connections Figure 4(a) depicts direct connections betw een a cell and its eight nearest neighbors. busing plane) and five vertical local buses (1 per busing plane). Figure 4. Cell Connections
routability. Up to five simultaneous local/local turns are possible. tant feature in the implementation of efficient array multipliers. Figure 5. The Cell most digital design application areas (see Figure 6).
10 AT40KEL040
Figure 6. Some Single Cell Modes registered, tri-stated and/or fed back into a core cell. Arithmetic Mode is frequently used in many designs. then be tri-stated and/or fed back into the cell. structure fits very well into the AT40K architecture. many outputs data switching.
RAM 32 x 4 dual-ported RAM blocks are dispersed throughout the array as shown in Figure 7. RAM, Ain is the READ/WRITE address port and Din is the (bi-directional) data port. connect to the vertical express buses in the same column. Figure 7. RAM Connections (One Ram Block)
12 AT40KEL040
Figure 8. RAM Logic logic can be automatically generated using the macro generators.
Figure 9. RAM Example: 128 x 8 Dual-ported RAM (Asynchronous)
14 AT40KEL040
4155I–AERO–06/06 Clocking Scheme There are eight Global Clock buses (GCK1 - GCK8) on the AT40KEL040 FPGA. Each of the eight dedicated Global Clock buses is connected to one of the dual-use Global Clock pins. Any clocks used in the design should use global clocks where possible: this can be done by using Assign Pin Locks to lock the clocks to the Global Clock locations. In addition to the eight Global Clocks, there are four Fast Clocks (FCK1 - FCK4), two per edge column of the array for PCI specificat ion. Even the derive d clocks can be routed through the Global network. Access points are provided in the corners of the array to route the derived clocks into the global clock network. The IDS software tools handle derived clocks to global clock connections automatically if used. Each column of an array has a “Column Clock mux” and a “Sector Clock mux”. The Col- umn Clock mux is at the top of every column of an array and the Sector Clock mux is at every four cells. The Column Clock mux is selected from one of the eight Global Clock buses. The clock provided to each sector column of four cells is inverted, non-inverted or tied off to “0”, using the Sector Clock mux to minimize the power consumption in a sector that has no clocks. The clock can either come from the Column Clock or from the Plane 4 express bus (see Figure 10 on page 15) . The extreme-left Column Clock mux has two additional inputs, FCK1 and FCK2, to provide fast clocking to left-side I/Os. The extreme-right Column Clock mux has two addit ional inputs as well, FCK3 and FCK4, to provide fast clocking to right-side I/Os. The register in each cell is triggered on a rising clock edge by default. Before configura- tion on power-up, constant “0” is provided to each register’s clock pins. After configura- tion on power-up, the registers either set or reset, depending on the user’s choice. The clocking scheme is designed to allow effi cient use of multiple clocks with low clock skew, both within a column and across the core cell array.
Figure 10. Clocking (for One Column of Cells)
16 AT40KEL040
4155I–AERO–06/06 Set/Reset Scheme The AT40KEL040 family reset scheme is ess entially the same as the clock scheme except that there is only one Global Reset. A dedicated Global Set/Reset bus can be driven by any User I/O, except those used fo r clocking (Global Clocks or Fast Clocks). The automatic placement tool will choose the reset net with the most connections to use the global resources. You can change this by using an RSBUF component in your design to indicate the global reset. Additional resets will use the express bus network. The Global Set/Reset is distributed to each column of the array. Like Sector Clock mux, there is Sector Set/Reset mux at every four cells. Each sector column of four cells is set/reset by a Plane 5 express bus or Global Set/Reset using the Sector Set/Reset mux (Figure 11 on page 17). The set/reset provided to each sector column of four cells is either inverted or non-inverted using the Sector Reset mux. The function of the Set/Reset input of a register is determined by a configuration bit in each cell. The Set/Reset input of a register is active low (logic 0) by default. Setting or Resetting of a register is asynchronous. Be fore configuration on power-up, a logic 1 (a high) is provided by each register (i.e., all registers are set at power-up).
Figure 11. Set/Reset (for One Column of Cells)
18 AT40KEL040
4155I–AERO–06/06 I/O Structure AT40K has registered I/Os and group enable every sector for tri-states on obuf’s. Pad The I/O pad is the one that connects the I/O to the outside world. Note that not all I/Os have pads: the ones without pads are called Unbonded I/Os. The number of unbonded I/Os varies with the device size and package. These unbonded I/Os are used to perform a variety of bus turns at the edge of the array. Pull-up/Pull-down Each pad has a programmable pull-up and pull-down attached to it. This supplies a weak “1” or “0” level to the pad pin. When all other drivers are off, this control will dictate the signal level of the pad pin. The input stage of each I/O cell has a number of parameters that can be programmed either as properties in schematic entry or in the I/O Pad Attributes editor in IDS. CMOS The threshold level is a CMOS-compatible level. Schmitt A Schmitt trigger circuit can be enabled on the inputs. The Schmitt trigger is a regenera- tive comparator circuit that adds 1V hysteresis to the input. This effectively improves the rise and fall times (leading and trailing e dges) of the incoming signal and can be useful for filtering out noise. Delays The input buffer can be programmed to include four different intrinsic delays as specified in the AC timing characteristics. This feature is useful for meeting data hold require- ments for the input signal. Drive The output drive capa bilities of each I/O are programm able. They can be set to FAST, MEDIUM or SLOW (using IDS tool). The F AST setting has the highest drive capability (16 mA at 3.3V) buffer and the fastest slew rate. MEDIUM produces a medium drive (12 mA at 3.3V) buffer, while SLOW yields a standard (4 mA at 3.3V) buffer. Tri-State The output of each I/O can be made tri-state (0, 1 or Z), open source (1 or Z) or open drain (0 or Z) by programming an I/O’s Source Selection mux. Of course, the output can be normal (0 or 1), as well. Source Selection Mux The Source Selection mux sele cts the source for the output signal of an I/O. See Figure 12 on page 21. Primary, Secondary and Corner I/Os The AT40KEL040 has three kinds of I/Os: Primary I/O, Secondary I/O and a Corner I/O. Every edge cell except corner cells on the AT40KEL040 has access to one Primary I/O and two Secondary I/Os. Primary I/O Every logic cell at the edge of the FPGA array has a direct orthogonal connection to and from a Primary I/O cell. The Primary I/O interf aces directly to its adjacent core cell. It also connects into the repeaters on the ro w immediately above and below the adjacent core cell. In addition, each Primary I/O also connects into the busing network of the three nearest edge cells. This is an extremely powerful feature, as it provides logic cells toward the center of the array with fast access to I/Os via local and express buses. It can be seen from the diagram that a given Prim ary I/O can be accessed from any logic cell on three separate rows or columns of the FPGA. See Figures 12a and 13a. Secondary I/O Every logic cell at the edge of the FPGA array has two direct diagonal connections to a Secondary I/O cell. The Secondary I/O is loca ted between core cell locations. This I/O
4155I–AERO–06/06 connects on the diagonal inputs to the cell ab ove and the cell below. It also connects to the repeater of the cell above and below. In addition, each Secondary I/O also connects into the busing network of the two nearest edge cells. This is an extremely powerful fea- ture, as it provides logic cells toward the center of the array with fast access to I/Os via local and express buses. It can be seen from the diagram that a given Secondary I/O can be accessed from any logic cell on two rows or columns of the FPGA. See Figure 12a and Figure 13b. Corner I/O Logic cells at the corner of the FPGA array have direct-connect access to five separate I/Os: 2 Primary, 2 Secondary and 1 Corner I/O. Corner I/Os are like an extra Secondary I/O at each corner of the array. With the inclusion of Corner I/Os, an AT40KEL040 FPGA with n x n core cells always has 8n I/Os. As the diagram shows, Corner I/Os can be accessed both from the corner logic cell and the horizontal and vertical busing net- works running along the edges of the array. This means that many different edge logic cells can access the Corner I/Os. See Figure 14.
20 AT40KEL040
Figure 12. South I/O (Mirrored for North I/O)
Figure 13. West I/O (Mirrored for East I/O)
22 AT40KEL040
Figure 14. Northwest Corner I/O (Similar NE/SE/SW Corners)
4155I–AERO–06/06
Electrical Characteristics
Absolute Maximum Ratings* Maximum Ratings may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those listed under oper- ating conditions is not implied. Exposure to Abso- lute Maximum Rating conditions for extended periods of time may affect device reliability. Voltage on Any Input Pin Voltage on Any Output Pin 1. For DC Input Voltage (V I) Minimum voltage of -0.5V DC, which may undershoot to -2.0V for pulses of less than 20 ns. DC and AC Operating Range Operating Temperature -55 °C to +125°C VCC Power Supply 3.3V ± 0.3V Input Voltage Level (CMOS) High (VIHC) 70% V CC to VCC + 0.3V DC (KEL version) 70% VCC to 5.5V DC (KFL version) Low (VILC) -0.3V to 30% V CC DC
24 AT40KEL040
Note: 1. Parameter based on characterization and simulation; it is not tested in production. fast ramp-up time requires more current than a slow ramp-up time. Table 3. Power-on Supply Requirements above. A larger capacity power supply may result in a larger initiallization current.
- Ramp-up time is measured from 0V DC to 3.6V DC. Peak current required lasts less
than 2 ms, and occurs near the internal power on reset threshold voltage.
4155I–AERO–06/06 AC Timing Characteristics Delays are based on fixed loads which are described in the notes. Maximum timing based on worst case: Vcc = 3.0V, temperature = 125°C. Minimum timing based on best case: Vcc = 3.6V, temperature = -55°C. Maximum delays are the average of tPDLH and tPDHL. AC Timing Characteristics All input I/O characteristics measured from VIH of 50% of VDD at the pad (CMOS threshold) to the internal VIH of 50% of VDD. All output I/O characteristics are measured as the average of tPDLH and tPDHL to the pad VIH of 50% of VDD. Cell Function Parameter Path Value Unit Notes Core 2-input gate t PD (max) x/y -> x/y 2.9 ns 1 unit load 3-input gate t PD (max) x/y/z -> x/y 3.1 ns 1 unit load 3-input gate t PD (max) x/y/w -> x/y 3.5 ns 1 unit load 4-input gate t PD (max) x/y/w/z -> x/y 3.5 ns 1 unit load Fast carry t PD (max) y -> y 2.8 ns 1 unit load Fast carry t PD (max) x -> y 2.6 ns 1 unit load Fast crry t PD (max) y -> x 2.8 ns 1 unit load Fast carry t PD (max) x -> x 2.9 ns 1 unit load Fast carry t PD (max) w -> y 3.5 ns 1 unit load Fast carry t PD (max) w -> x 3.5 ns 1 unit load Fast carry t PD (max) z -> y 3.1 ns 1 unit load Fast carry t PD (max) z -> x 3.0 ns 1 unit load DFF t PD (max) Clk -> x/y 4.3 ns 1 unit load DFF t PD (max) R -> x/y 4.1 ns 1 unit load DFF t PD (max) S -> x/y 2.8 ns 1 unit load DFF t PD (max) q -> w 4.3 ns Incremental -> L t PD (max) x/y -> L 2.5 ns 1 unit load Local output enable t PZX (max) oe -> L 2.9 ns 1 unit load Local output enable t PXZ (max) oe -> L 0.9 ns Cell Function Parameter Path Value Unit Notes Repeaters Repeater t PD (max) L -> E 1.3 ns 1 unit load Repeater t PD (max) E -> E 1.3 ns 1 unit load Repeater t PD (max) L -> L 1.3 ns 1 unit load Repeater t PD (max) E -> L 1.3 ns 1 unit load Repeater t PD (max) E -> IO 0.7 ns 1 unit load Repeater t PD (max) L -> IO 0.7 ns 1 unit load
26 AT40KEL040
4155I–AERO–06/06 Cell Function Parameter Path Value Unit Notes I/O Input t PD (max) pad -> x/y 5.4 ns no extra delay Input t PD (max) pad -> x/y 7.6 ns 1 extra delay Input t PD (max) pad -> x/y 11.4 ns 2 extra delays Input t PD (max) pad -> x/y 14.9 ns 3 extra delays Output, slow t PD (max) x/y/E/L -> pad 16.0 ns 50 pf load Output, medium t PD (max) x/y/E/L -> pad 14.8 ns 50 pf load Output, fast t PD (max) x/y/E/L -> pad 11.2 ns 50 pf load Output, slow t PZX (max) oe -> pad 16.4 ns 50 pf load Output, slow t PXZ (max) oe -> pad 5.1 ns 50 pf load Output, medium t PZX (max) oe -> pad 14.1 ns 50 pf load Output, medium t PXZ (max) oe -> pad 9.1 ns 50 pf load Output, fast t PZX (max) oe -> pad 11.4 ns 50 pf load Output, fast t PXZ (max) oe -> pad 9.5 ns 50 pf load
4155I–AERO–06/06 AC Timing Characteristics Clocks and Reset Input buffers are measured from a VIH of 1.5V at the input pad to the internal VIH of 50% of VCC. Maximum timings for clock input buffers and internal drivers are measured for rising edge delays only. Notes: 1. CMOS buffer delays are measured from a V IH of 1/2 VCC at the pad to the internal VIH at A. The input buffer load is constant. 2. Buffer delay is to a pad voltage of 1.5V with one output switching. 3. Parameter based on characterization and simulation; not tested in production. 4. Exact power calculation is available in Atmel FPGA Designer software. Cell Function Parameter Path Value Unit Notes Global Clocks and Set/Reset GCK Input buffer t PD (max) pad -> clock 3.3 ns rising edge clock FCK Input buffer t PD (max) pad -> clock 1.9 ns rising edge clock Clock column driver t PD (max) clock -> colclk 1.7 ns rising edge clock Clock sector driver t PD (max) colclk -> secclk 0.8 ns rising edge clock GSRN Input buffer t PD (max) colclk -> secclk 10.3 ns Global clock to output t PD (max) clock pad -> out 21.3 ns rising edge clock fully loaded clock tree rising edge DFF 20 mA output buffer 50 pf pin load Fast clock to output t PD (max) clock pad -> out 19.9 ns rising edge clock fully loaded clock tree rising edge DFF 20 mA output buffer 50 pf pin load
28 AT40KEL040
4155I–AERO–06/06 AC Timing Characteristics Cell Function Parameter Path Value Unit Notes Asynchronous RAM Write t WECYC (min) cycle time 28 ns Write t WEL (min) we 6.5 ns pulse width low Write t WEH (min) we 6.5 ns pulse width high Write t setup (min) wr addr setup -> we 7.0 ns Write t hold (min) wr addr hold -> we 0.0 ns Write t setup (min) din setup -> we 6.5 ns Write t hold (min) din hold -> we 0.0 ns Write t hold (min) oe hold -> we 0.0 ns Write/Read t PD (max) din -> dout 14.1 ns rd addr = wr addr Read t PD (max) rd addr -> dout 13.1 ns Read t PZX (max) oe -> dout 4.5 ns Read t PXZ (max) oe -> dout 4.5 ns Synchronous RAM Write t CYC (min) cycle time 28 ns Write t CLKL (min) clk 6.5 ns pulse width low Write t CLKH (min) clk 6.5 ns pulse width high Write t setup (min) we setup -> clk 5.0 ns Write t hold (min) we hold -> clk 0.0 ns Write t setup (min) wr addr setup -> clk 6.5 ns Write t hold (min) wr addr hold -> clk 0.0 ns Write t setup (min) wr data setup -> clk 5.1 ns Write t hold (min) wr data hold -> clk 0.0 ns Write/Read t PD (max) din -> dout 14.1 ns rd addr = wr addr Write/Read t PD (max) clk -> dout 7.9 ns rd addr = wr addr Read t PD (max) rd addr -> dout 13.1 ns Read t PZX (max) oe -> dout 4.5 ns Read t PXZ (max) oe -> dout 4.5 ns
4155I–AERO–06/06 FreeRAM Asynchronous Timing Characteristics Single Port Write/Read Dual Port Write with Read Dual Port Read
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4155I–AERO–06/06 FreeRAM Synchronous Timing Characteristics Single Port Write/Read Dual Port Write with Read WE ADDR DATA tCLKH tWCS tACS tDCH tWCH tACH 01 2 CLK tOXZ tDCS OE tOZX tAD WE WR ADDR WR DATA RD DATA tCLKH tWCS tACS tCYC tWCH tCD tACH = WR ADDR 1RD ADDR 01 2 CLK tCLKL tDCS tDCH
4155I–AERO–06/06 Dual Port Read RD ADDR DATA tOZX OE tOXZtAD
Table 4. MQFP F-160
2 I/O384_GCK8_A15
3 I/O383_A14
4 I/O382
5 I/O381
6 I/O372_A13
7 I/O371_A12
8 I/O370
9 I/O369
10 GND
11 I/O360
12 I/O359
13 I/O348_A11
14 I/O347_A10
15 I/O344
16 I/O343
17 I/O338_A9
18 I/O337_A8
19 VCC
20 GND
21 I/O336_A7
22 I/O335_A6
23 I/O330
24 I/O329
25 I/O328
26 I/O326_A5
27 I/O325_A4
28 I/O314
29 I/O313
30 GND
31 I/O304
32 I/O303
33 I/O298_A3
34 I/O297_CS1_A2
35 I/O292
36 I/O291
37 I/O290_GCK7_A1
38 I/O289_A0
39 GND
40 TESTCLOCK
41 VCC
42 CCLK
43 I/O288_GCK6
44 I/O287_D0
45 I/O286
46 I/O285
47 I/O278
48 I/O277_D1
49 I/O274
50 I/O273
51 GND
52 I/O262_FCK4
53 I/O261
54 I/O260
55 I/O259_D2
56 I/O246
57 I/O245
58 I/O242_CHECK
59 I/O241_D3
60 GND
61 VCC
62 I/O240
63 I/O239_D4
64 I/O236
65 I/O235
66 I/O222_CS0
67 I/O221_D5
68 I/O220
69 I/O219_FCK3
70 GND
71 I/O208
72 I/O207
73 I/O206
74 I/O205_D6
75 I/O196
76 I/O195
77 I/O194_GCK5
78 I/O193_D7
79 RESETN
80 VCC
81 CON
82 GND
83 I/O192_GCK4
84 I/O191_D8
85 I/O190
86 I/O189
87 I/O184_D9
88 I/O183_D10
89 I/O180
90 I/O179
91 GND
92 I/O168
93 I/O167
94 I/O166_D11
95 I/O165_D12
96 I/O152
97 I/O151
98 I/O146_D13
99 I/O145_D14
100 GND
101 VCC
4155E–AERO–06/04
102 I/O144_INIT
103 I/O143_D15
104 I/O138
105 I/O137
106 I/O124
107 I/O123
108 I/O122
109 I/O121
110 GND
111 I/O110
112 I/O109
113 I/O102_LDC
114 I/O101
115 I/O100
116 I/O99
117 I/O98_HDC
118 I/O97_GCK3
120 VCC
122 GND
124 I/O96_GCK2
125 I/O95_OTS
126 I/O94
127 I/O93
128 I/O90
129 I/O89
130 I/O84
131 I/O83
132 GND
133 I/O72_FCK2
134 I/O71
135 I/O70
136 I/O69
137 I/O54
138 I/O53
139 I/O50
140 I/O49
141 VCC
142 GND
143 I/O48_A23
144 I/O47_A22
145 I/O44
146 I/O43
147 I/O28_A21
148 I/O27_A20
149 I/O26
150 I/O25_FCK1
151 GND
152 I/O16
153 I/O15
154 I/O6_A19
155 I/O5_A18
156 I/O4
157 I/O3
158 I/O2_A17
159 I/O1_GCLK1_A16
160 GND
Table 5. MQFP - F256
1 IO384_GCK8_A15
2 IO383_A14
3 IO382
4 IO381
5 IO378
6 IO377
9 IO375
10 IO374
11 IO372_A13
12 IO371_A12
13 IO370
14 IO369
15 IO366
16 IO365
17 IO362
18 IO360
19 IO359
20 IO358
21 IO356
22 IO355
23 IO353
24 IO352
25 IO349
26 IO348_A11
27 IO347_A10
28 IO346
29 IO344
30 IO343
31 IO338_A9
32 IO337_A8
33 IO336_A7
34 IO335_A6
35 IO334
36 IO330
37 IO329
38 IO328
39 IO326_A5
40 IO325_A4
41 IO324
42 IO323
43 IO321
44 IO320
45 IO318
46 IO317
47 IO314
48 IO313
49 IO312
50 IO311
51 IO308
52 IO307
53 IO304
54 IO303
55 IO301
56 IO298_A3
57 GND
58 VCC
59 IO297_CS1_A2
60 IO291
61 IO292
62 IO290_GCK7_A1
63 IO289_A0
64 TESTCLOCK
65 CCLK
66 IO288_GCK6
67 IO287_D0
68 IO286
69 IO285
70 IO282
71 GND
72 VCC
73 IO278
74 IO277_D1
75 IO276
76 IO274
77 IO273
78 IO272
79 IO270
80 IO269
81 IO267
82 IO266
83 IO262_FCK4
84 IO261
85 IO260
86 IO259_D2
87 IO258
88 IO257
89 IO254
90 IO253
91 IO252
92 IO251
93 IO248
94 IO246
95 IO245
96 IO242_CHECK
97 IO241_D3
98 IO240
99 IO239_D4
100 IO236
101 IO235
4155E–AERO–06/04
102 IO234
103 IO232
104 IO230
105 IO228
106 IO227
107 IO225
108 IO224
109 IO222_CS0
110 IO221_D5
111 IO220
112 IO219_FCK3
113 IO216
114 IO215
115 IO212
116 IO208
117 IO207
118 IO206
119 IO205_D6
120 IO204
121 GND
122 VCC
123 IO203
124 IO196
125 IO195
126 IO194_GCK5
127 IO193_D7
128 RESETN
129 CON
130 IO192_GCK4
131 IO191_D8
132 IO190
133 IO189
134 IO186
135 GND
136 VCC
137 IO184_D9
138 IO183_D10
139 IO181
140 IO180
141 IO179
142 IO177
143 IO174
144 IO173
145 IO171
146 IO168
147 IO167
148 IO166_D11
149 IO165_D12
150 IO163
151 IO162
152 IO161
153 IO158
154 IO157
155 IO156
156 IO152
157 IO151
158 IO150
159 IO149
160 IO146_D13
161 IO145_D14
162 IO144_INIT
163 IO143_D15
164 IO141
165 IO138
166 IO137
167 IO136
168 IO134
169 IO132
170 IO131
171 IO129
172 IO128
173 IO124
174 IO123
175 IO122
176 IO121
177 IO120
178 IO119
179 IO116
180 IO115
181 IO113
182 IO110
183 IO109
184 IO101
185 GND
186 VCC
187 IO102_LDC
188 IO99
189 IO100
190 IO98_HDC
191 IO97_GCK3
195 IO96_GCK2
196 IO95_OTS
197 IO94
198 IO93
199 GND
200 VCC
201 IO90
202 IO89
203 IO86
4155E–AERO–06/04
204 IO85
205 IO84
206 IO83
207 IO80
208 IO79
209 IO77
210 IO76
211 IO72_FCK2
212 IO71
213 IO70
214 IO69
215 IO67
216 IO66
217 IO63
218 IO62
219 IO60
220 IO59
221 IO57
222 IO56
223 IO54
224 IO53
225 IO50
226 IO49
227 IO48_A23
228 IO47_A22
229 IO44
230 IO43
231 IO41
232 IO39
233 IO36
234 IO35
235 IO34
236 IO33
237 IO30
238 IO29
239 IO28_A21
240 IO27_A20
241 IO26
242 IO25_FCK1
243 IO21
244 IO20
245 IO18
246 IO16
247 IO15
248 IO13
249 GND
250 VCC
251 IO6_A19
252 IO5_A18
253 IO4
254 IO3
255 IO2_A17
256 IO1_GCLK1_A16
4155I–AERO–06/06 Part/Package Availability and User I/O Counts (Including Dual-function Pins) MQFPF 160 129 MQFPF 256 233
38 AT40KEL040
4155I–AERO–06/06
Ordering Information
Part Number Package Version Temperature Range Quality Flow AT40KEL040KW1-E MQFPF160 3.3V 25 °C Engineering Samples 5962-0325001QXC MQFPF160 3.3V -55 ° to +125°CQ M L Q 5962-0325001VXC MQFPF160 3.3V -55 ° to +125°CQ M L V 930400801 MQFPF160 3.3V -55 ° to +125°C ESCC AT40KEL040KZ1-E MQFPF256 3.3V 25 °C Engineering Samples 5962-0325001QYC MQFPF256 3.3V -55 ° to +125°CQ M L Q 5962-0325001VYC MQFPF256 3.3V -55 ° to +125°CQ M L V 930400802 MQFPF256 3.3V -55 ° to +125°C ESCC AT40KFL040KW1-E MQFPF160 3.3V, 5V Tolerant 25 °C Engineering Samples 5962-0325002QXC MQFPF160 3.3V, 5V Tolerant -55 ° to +125°CQ M L Q 5962-0325002VXC MQFPF160 3.3V, 5V Tolerant -55 ° to +125°CQ M L V AT40KFL040KW1-SCC MQFPF160 3.3V, 5V Tolerant -55 ° to +125°C ESCC AT40KFL040KZ1-E MQFPF256 3.3V, 5V Tolerant 25 °C Engineering Samples 5962-0325002QYC MQFPF256 3.3V, 5V Tolerant -55 ° to +125°CQ M L Q 5962-0325002VYC MQFPF256 3.3V, 5V Tolerant -55 ° to +125°CQ M L V AT40KFL040KZ1-SCC MQFPF256 3.3V, 5V Tolerant -55 ° to +125°C ESCC
4155I–AERO–06/06 Package Drawing Multilayer Quad Flat Pack (MQFP) 160-pin - Front View
40 AT40KEL040
4155I–AERO–06/06 Multilayer Quad Flat Pack (MQFP) 256-pin - Front View
4155I–AERO–06/06 Datasheet Change Log Changes from 4155B - 06/03 to 4155C 04/04 1. Addition of MQFP F256 package information 2. Pad/ Pin assignment updated. Table 4 on page 31. 3. Ordering information updated 4. Reference to design tools Changes from 4155C - 06/03 to 4155D 04/04 1. Update of radiation hardness performance, page 1. Changes from 4155D 04/04 - to 4155E 06/04 1. Updated FreeRAM timing characteristics, Section “FreeRAM Asynchronous Tim- ing Characteristics”, page 29. Changes from 4155E 06/04 to 4155F 06/04 1. Minor changes throughout the document. Changes from 4155F 06/04 to 4155G 05/05 1. Minor changes. Changes from 4155G 05/05 to 4155H 02/06 1. Added MQFP256 package. Changes from 4155H 02/06 to 4155I 06/06 1. Adding AT40KFL040 5V tolerant version. 2. Corrections on matrix decription.
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