AT34C02C_14 ATMEL | Alldatasheet
Document overview
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Technical content
Features
- Permanent and Reversible Software Write Protection for the First-half of the Array – Software Procedure to Verify Write Protect Status Hardware Write Protection for the Entire Array Standard-voltage Operation – 2.5 (V CC = 2.5V to 5.5V) Internally Organized 256 x 8 Two-wire Serial Interface Schmitt Trigger, Filtered Inputs for Noise Suppression Bidirectional Data Transfer Protocol 400 kHz (2.5V and 5.5V) Compatibility 16-byte Page Write Modes Partial Page Writes Are Allowed Self-timed Write Cycle (5 ms max) High-reliability – Endurance: 1 Million Write Cycles – Data Retention: 100 Years 8-lead JEDEC SOIC and 8-lead TSSOP Packages
Description
The AT34C02C provides 2048 bits of serial electrically-erasable and programmable read only memory (EEPROM) organized as 256 words of 8 bits each. The first-half of the device incorporates a permanent and a reversible software write protection feature while hardware write protection for the entire array is available via an external pin. Once the permanent software write protection is enabled, by sending a special com- mand to the device, it cannot be reversed. However, the reversible software write protection is enabled and can be reversed by sending a special command. The hard- ware write protection is controlled with the WP pin and can be used to protect the entire array, whether or not the software write protection has been enabled. This allows the user to protect none, first-half, or all of the array depending on the applica- tion. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operations are essential. The AT34C02C is avail- able in space saving 8-lead JEDEC SOIC and 8-lead TSSOP packages and is Table 1. Pin Configurations
Figure 1. Block Diagram device and negative edge clock data out of each device. that are hardwired (directly to GND or to Vcc) for compatibility with other AT24Cxx devices.
Note: 1. This parameter is characterized and is not 100% tested. Note: 1. V IL min and VIH max are reference only and are not tested. Table 2. AT34C02C Write Protection Modes Table 3. Pin Capacitance(1) Table 4. DC Characteristics
Note: 1. This parameter is ensured by characterization only. AT34C02C, 2K Serial EEPROM: The 2K is internally organized with 16 pages of 16 bytes each. Random word addressing requires a 8-bit data word address. must precede any other command (see Figure 5 on page 6). word. This happens during the ninth clock cycle. Table 5. AC Characteristics
5242B–SEEPR–01/09 AT34C02C The device address word consists of a mandatory one-zero sequence for the first four most-sig- nificant bits (1010) for normal read and write operations and 0110 for writing to the write protect register. The next 3 bits are the A2, A1 and A0 device address bits for the AT34C02C EEPROM. These 3 bits must compare to their corresponding hard-wired input pins. The eighth bit of the device address is the read/write operation select bit. A read operation is ini- tiated if this bit is high and a write operation is initiated if this bit is low. Upon a compare of the device address, the EEPROM will outpu t a zero. If a compare is not made, the chip will return to a standby state. The device will not acknowledge if the write protect register has been programmed and the control code is 0110. Write Operations BYTE WRITE: A write operation requires an 8-bit data word address following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a zero and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a ze ro and the addr essing device, such as a microcontroller, must terminate the writ e sequence with a stop condition. At this time the EEPROM enters an internally-timed write cycle, t WR, to the nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write is complete (see Figure 11 on page 12). The device will acknowledge a write command, but not write the data, if the software or hard- ware write protection has been enabled. The writ e cycle time must be observed even when the write protection is enabled. PAGE WRITE: The 2K device is capable of 16-byte page write. A page write is initiated the same as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit up to fifteen more data words. The EEPROM will respond with a zero after each data word received. The microcontroller must ter- minate the page write sequence with a stop condition (see Figure 12 on page 12). The data word address lower four bits are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. When the word address, internally generated, reaches the page boundary, the fol- lowing byte is placed at the beginning of the same page. If more than sixteen data words are transmitted to the EEPROM, the data word a ddress will “roll over” and previous data will be overwritten. The address “roll over” during write is from the last byte of the current page to the first byte of the same page. The device will acknowledge a write command, but not write the data, if the software or hard- ware write protection has been enabled. The writ e cycle time must be observed even when the write protection is enabled. ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the EEPROM inputs are disabled, ackno wledge polling can be initiate d. This involves sending a start condition followed by the device address word. The read/write bit is representative of the operation desired. Only if th e internal write cycle has comp leted will the EEPROM respond with a zero allowing the read or write sequence to continue. Write Protection The software write protection, once enabled, write pr otects only the first-half of the array (00H - 7FH) while the hardware write protection, via the WP pin, is used to protect the entire array.
Table 6. Write Protection Table 7. VHV Table 8. WP Connected to GND or Floating
1010 R X X ACK
1010 W Programmed X ACK Can write to second Half (80H - FFH) only
1010 W X Programmed ACK Can write to second Half (80H - FFH) only
1010 W Not Programmed Not Programmed ACK Can write to full array
Table 9. WP Connected to Vcc current address read, random address read and sequential read. during read is from the last byte of the last memory page to the first byte of the first page.
1010 R X X ACK Read array
1010 W X X ACK Device Write Protect
dition (see Figure 13 on page 12). does generate a following stop condition (see Figure 14 on page 12). but does generate a following stop condition (see Figure 15 on page 13). permanently write protected at the first half of the array. Table 10. PSWP Status write protected (reversible) at the first half of the array. Figure 10. Device Address
Figure 15. Sequential Read
5242B–SEEPR–01/09 AT34C02C Notes: 1. “-B” denotes bulk. 2. “-T” denotes tape and reel. SOIC = 4K per reel; TSSOP = 5K per reel. Ordering Code Package Operation Range AT34C02CN-SP25-B(1) (NiPdAu Lead Finish) AT34C02CN-SP25-T(2) (NiPdAu Lead Finish) AT34C02C-TP25-B(1) (NiPdAu Lead Finish) AT34C02C-TP25-T(2) (NiPdAu Lead Finish) 8S1 8S1 8A2 8A2 Lead-free/Halogen-free/NiPdAu Lead Finish Automotive Temperature (–40°C to125°C) Package Type 8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC) 8A2 8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP) Options –2.5 Low Voltage (2.5V to 5.5V)
5242B–SEEPR–01/09 AT34C02C Packaging Information 8S1 – JEDEC SOIC 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TITLE DRAWING NO. R REV. Note: 10/7/03 8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC) 8S1 B COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A1 0.10 – 0.25 These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. A 1.35 – 1.75 b 0.31 – 0.51 C 0.17 – 0.25 D 4.80 – 5.00 E1 3.81 – 3.99 E 5.79 – 6.20 e 1.27 BSC L 0.40 – 1.27 ∅ 0˚ – 8˚ Top View End View Side View e B D A N E C L
5242B–SEEPR–01/09 AT34C02C 8A2 – TSSOP
2325 Orchard Parkway
San Jose, CA 95131 TITLE DRAWING NO. R REV. 5/30/02 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE D 2.90 3.00 3.10 2, 5 E 6.40 BSC E1 4.30 4.40 4.50 3, 5 A – – 1.20 A2 0.80 1.00 1.05 b 0.19 – 0.30 4 e 0.65 BSC L 0.45 0.60 0.75 L1 1.00 REF 8A2, 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP) Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances, datums, etc. 2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed 0.15 mm (0.006 in) per side. 3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm (0.010 in) per side. 4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between protrusion and adjacent lead is 0.07 mm. 5. Dimension D and E1 to be determined at Datum Plane H. 8A2 B Side View End ViewTop View A L D 123 N b Pin 1 indicator this corner E e
5242B–SEEPR–01/09 AT34C02C
Revision History
5242B 1/2009 Removed Preliminary status.
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