AT34C02 ATMEL | Alldatasheet

Document overview

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Technical content

Features

  • Permanent Software Write Protection for the First-Half of the Array – Software Procedure to Verify Write Protect Status
  • Hardware Write Protection for the Entire Array
  • Low Voltage and Standard Voltage Operation – 5.0 (VCC = 4.5V to 5.5V) – 2.7 (VCC = 2.7V to 5.5V) – 1.8 (VCC = 1.8V to 5.5V)
  • Internally Organized 256 x 8
  • 2-Wire Serial Interface
  • Schmitt Trigger, Filtered Inputs for Noise Suppression
  • Bidirectional Data Transfer Protocol
  • 100 KHz (1.8V and 2.7V) and 400 KHz (5.0V) Compatibility
  • 16-Byte Page Write Modes
  • Partial Page Writes Are Allowed
  • Self-Timed Write Cycle (10 ms max)
  • High Reliability – Endurance: 1 Million Write Cycles – Data Retention: 100 Years – ESD Protection: >3,000V
  • Automotive Grade and Extended Temperature Devices Available
  • 8-Pin PDIP , 8-Pin JEDEC SOIC and 8-Pin TSSOP Packages

Description

The AT34C02 provides 2048 bits of serial electrically erasable and programmable read only memory (EEPROM) organized as 256 words of 8 bits each. The first-half of the device incorporates a software write protection feature while hardware write pro- tection for the entire array is available via an external pin as well. Once the software write protection is enabled, by sending a special command to the device, it cannot be reversed. The hardware write protection is controlled with the WP pin and can be used to protect the entire array, whether or not the software write protection has been enabled. This allows the user to protect none, first-half, or all of the array depending on the application. The device is optimized for use in many industrial and commercial applications where low power and low voltage operations are essential. The AT34C02 is available in space saving 8-pin PDIP, 8-pin JEDEC SOIC, and 8-pin TSSOP pack- ages and is accessed via a 2-wire serial interface. In addition, it is available in 5.0V Rev. 0958D–07/98 Pin Configurations Pin Name Function A0 to A2 Address Inputs SDA Serial Data SCL Serial Clock Input WP Write Protect 2-Wire Serial EEPROM with Permanent Software Write Protect 2K (256 x 8) AT34C02 8-Pin PDIP GND VCC WP SCL SDA 8-Pin SOIC GND VCC WP SCL SDA 8-Pin TSSOP GND VCC WP SCL SDA 2-Wire Serial EEPROM with Permanent Software Write Protec

SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device. SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open collector devices. DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1 and A0 pins are device address inputs that are hard wired for the A T34C02. As many as eight 2K devices may be addressed on a single bus system (device addressing is discussed in detail under the Device Addressing section). WRITE PROTECT (WP): The AT34C02 has a Write Pro- tect pin that provides hardware data protection. The Write Protect pin allows normal read/write operations when con- Absolute Maximum Ratings* Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Voltage on Any Pin LOGIC D OUT D IN SDA GND SCL VCC Y DEC DATA WORD ADDR/COUNTER SERIAL CONTROL LOGIC START STOP LOGIC DEVICE ADDRESS COMPARATOR SERIAL MUX E2PROM EN COMP INCLOAD LOAD R/W H.V. PUMP/TIMING DATA RECOVERY X DEC WP WRITE PROTECT CIRCUITRY SOFTWARE WRITE PROTECTED AREA (00H - 7FH)

nected to ground (GND) or when left floating. When the Write Protect pin is connected to VCC , the write protection feature is enabled for the entire array. The write protection modes are shown in the following table. Note: 1. This parameter is characterized and is not 100% tested Note: 1. V IL min and VIH max are reference only and are not tested. AT34C02 Write Protection Modes WP Pin Status Write Protect Register Part of the Array Write Protected VCC — Full Array (2K) GND or Floating Not Programmed Normal Read/Write GND or Floating Programmed First-Half of Array (1K: 00H - 7FH) Pin Capacitance(1) Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +1.8V Symbol Test Condition Max Units Conditions C I/O Input/Output Capacitance (SDA) 8 pF V I/O = 0V C IN Input Capacitance (A0, A1, A2, SCL) 6 pF V IN = 0V DC Characteristics Applicable over recommended operating range from: TAI = -40°C to +85°C, VCC = +1.8V to +5.5V, TAC = 0°C to +70°C, VCC = +1.8V to +5.5V (unless otherwise noted). Symbol Parameter Test Condition Min Typ Max Units VCC1 Supply Voltage 1.8 5.5 V VCC2 Supply Voltage 2.7 5.5 V VCC3 Supply Voltage 4.5 5.5 V ICC Supply Current VCC = 5.0V READ at 100 KHz 0.4 1.0 mA ICC Supply Current VCC = 5.0V WRITE at 100 KHz 2.0 3.0 mA ISB1 Standby Current VCC = 1.8V V IN = VCC or VSS 0.6 3.0 µA ISB2 Standby Current VCC = 2.7V V IN = VCC or VSS 1.6 4.0 µA ISB3 Standby Current VCC = 5.0V V IN = VCC or VSS 8.0 18.0 µA ILI Input Leakage Current V IN = VCC or VSS 0.10 3.0 µA ILO Output Leakage Current V OUT = VCC or VSS 0.05 3.0 µA VIL Input Low Level(1) -0.6 V CC x 0.3 V VIH Input High Level(1) VCC x 0.7 V CC + 0.5 V VOL2 Output Low Level VCC = 3.0V I OL = 2.1 mA 0.4 V VOL1 Output Low Level VCC = 1.8V I OL = 0.15 mA 0.2 V

Note: 1. This parameter is characterized and is not 100% tested. Memory Organization AT34C02, 2K Serial EEPROM: The 2K is internally orga- nized with 256 pages of 1 byte each. Random word addressing requires a 8-bit data word address. Device Operation CLOCK and DATA TRANSITIONS: The SDA pin is nor- mally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (refer to Data Validity timing diagram). Data changes during SCL high periods will indicate a start or stop condition as defined below. START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (refer to Start and Stop Definition timing dia- gram). STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command will place the EEPROM in a standby power mode (refer to Start and Stop Definition timing diagram). ACKNOWLEDGE: All addresses and data words are seri- ally transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a zero to acknowledge that it has received each word. This happens during the ninth clock cycle. STANDBY MODE: The AT34C02 features a low power standby mode which is enabled: (a) upon power-up or (b) after the receipt of the STOP bit and the completion of any internal operations. MEMORY RESET: After an interruption in protocol, power loss or system reset, any 2-wire part can be reset by follow- ing these steps: (a) Clock up to 9 cycles, (b) look for SDA high in each cycle while SCL is high and then (c) create a start condition as SDA is high. AC Characteristics Applicable over recommended operating range from TA = -40°C to +85°C, VCC = +1.8V to +5.5V, C L = 1 TTL Gate and 100 pF (unless otherwise noted). Symbol Parameter 1.8V , 2.7V 5.0V UnitsM i nM a xM i nM a x fSCL Clock Frequency, SCL 100 400 kHz tLOW Clock Pulse Width Low 4.7 1.2 µs tHIGH Clock Pulse Width High 4.0 0.6 µs tI Noise Suppression Time(1) 100 50 ns tAA Clock Low to Data Out Valid 0.1 4.5 0.1 0.9 µs tBUF Time the bus must be free before a new transmission can start(1) 4.7 1.2 µs tHD.ST A Start Hold Time 4.0 0.6 µs tSU.ST A Start Set-up Time 4.7 0.6 µs tHD.DAT Data In Hold Time 0 0 µs tSU.DA T Data In Set-up Time 200 100 ns tR Inputs Rise Time(1) 1.0 0.3 µs tF Inputs Fall Time(1) 300 300 ns tSU.STO Stop Set-up Time 4.7 0.6 µs tDH Data Out Hold Time 100 50 ns tWR Write Cycle Time 10 10 ms Endurance(1) 5.0V , 25°C, Page Mode 1M 1M Write Cycles

Bus Timing SCL: Serial Clock SDA: Serial Data I/O Write Cycle Timing SCL: Serial Clock SDA: Serial Data I/O Note: 1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle. (1)

The 2K EEPROM device requires an 8-bit device address word following a start condition to enable the chip for a read or write operation (refer to Figure 2). The device address word consists of a mandatory one-zero sequence for the first four most-significant bits (1010) for normal read and write operations and 0110 for writing to the write protect register. The next 3 bits are the A2, A1 and A0 device address bits for the AT34C02 EEPROM. These 3 bits must compare to their corresponding hard-wired input pins. The eighth bit of the device address is the read/write opera- tion select bit. A read operation is initiated if this bit is high and a write operation is initiated if this bit is low. Upon a compare of the device address, the EEPROM will output a zero. If a compare is not made, the chip will return to a standby state. The device will not acknowledge if the write protect register has been programmed and the control code is 0110. Write Operations BYTE WRITE: A write operation requires an 8-bit data word address following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a zero and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a zero and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. At this time the EEPROM enters an internally-timed write cycle, t WR , to the nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write is complete (refer to Figure 3). The device will acknowledge a write command, but not write the data, if the software or hardware write protection has been enabled. The write cycle time must be observed even when the write protection is enabled. PAGE WRITE: The 2K device is capable of 16-byte page write. A page write is initiated the same as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcon- troller can transmit up to fifteen more data words. The EEPROM will respond with a zero after each data word received. The microcontroller must terminate the page write sequence with a stop condition (refer to Figure 4). The data word address lower four bits are internally incre- mented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. When the word address, inter- nally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than sixteen data words are transmitted to the EEPROM, the data word address will “roll over” and previous data will be overwritten. The address “roll over” during write is from the last byte of the current page to the first byte of the same page. The device will acknowledge a write command, but not write the data, if the software or hardware write protection has been enabled. The write cycle time must be observed even when the write protection is enabled. ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the EEPROM inputs are dis- abled, acknowledge polling can be initiated. This involves sending a start condition followed by the device address word. The read/write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM respond with a zero allowing the read or write sequence to continue. Write Protection The software write protection, once enabled, permanently write protects only the first-half of the array (00H - 7FH) while the hardware write protection, via the WP pin, is used to protect the entire array. SOFTWARE WRITE PROTECTION: The software write protection is enabled by sending a command, similar to a normal write command, to the device which programs the write protect register. This must be done with the WP pin low. The write protect register is programmed by sending a write command with the device address of 0110 instead of 1010 with the address and data bit being don’t cares (refer to Figure 1). Once the software write protection has been enabled, the device will no longer acknowledge the 0110 control byte. The software write protection cannot be reversed even if the device is powered down. The write cycle time must be observed. HARDWARE WRITE PROTECTION: The WP pin can be connected to V CC , GND, or left floating. Connecting the WP pin to VCC will write protect the entire array, regardless of whether or not the software write protection has been enabled. The software write protection register cannot be programmed when the WP pin is connected to V CC . If the WP pin is connected to GND or left floating, the write pro- tection mode is determined by the status of the software write protect register.

Figure 1. Setting Write Protect Register ing the last read or write operation, incremented by one. first byte of the first page. stop condition (refer to Figure 6).

1010 R X ACK Read Array

1010 W Programmed ACK Can Write to First Half Only

1010 W Not Programmed ACK Can Write to Full Array

0110 R Programmed No ACK Stop - Indicates Write Protect Register is Programmed

0110 W Programmed No ACK Stop - Indicates Write Protect Register is Programmed

0110 W Not Programmed ACK Program Write Protect Register (irreversible)

1010 W Programmed ACK Device Write Protect

1010 W Not Programmed ACK Device Write Protect

0110 W Not Programmed ACK Cannot Program Write Protect Register

Ordering Information

tWR (max) (ms) ICC (max) (µA) ISB (max) (µA) fMAX (kHz) Ordering Code Package Operation Range 10 3000 18 400 A T34C02-10PC AT34C02N-10SC AT34C02-10TC 8P3 8S1 Commercial (0°C to 70°C) 3000 18 400 AT34C02-10PI AT34C02N-10SI AT34C02-10TI 8P3 8S1 Industrial (-40°C to 85°C) 10 1500 4 100 A T34C02-10PC-2.7 AT34C02N-10SC-2.7 A T34C02-10TC-2.7 8P3 8S1 Commercial (0°C to 70°C) 1500 4 100 A T34C02-10PI-2.7 A T34C02N-10SI-2.7 A T34C02-10TI-2.7 8P3 8S1 Industrial (-40°C to 85°C) 10 800 3 100 A T34C02-10PC-1.8 AT34C02N-10SC-1.8 A T34C02-10TC-1.8 8P3 8S1 Commercial (0°C to 70°C) 800 3 100 A T34C02-10PI-1.8 A T34C02N-10SI-1.8 A T34C02-10TI-1.8 8P3 8S1 Industrial (-40°C to 85°C) Package Type 8P3 8-Lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8S1 8-Lead, 0.150" Wide, Plastic Gull Wing Small Outline Package(JEDEC SOIC) 8T 8-Lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP) Options Blank Standard Operation (4.5V to 5.5V) -2.7 Low Voltage (2.7V to 5.5V) -1.8 Low Voltage (1.8V to 5.5V)

.400 (10.16) .355 (9.02) PIN .280 (7.11) .240 (6.10) .037 (.940) .210 (5.33) MAX SEATING PLANE .100 (2.54) BSC .015 (.380) MIN .022 (.559) .014 (.356) .150 (3.81) .115 (2.92) .070 (1.78) .045 (1.14) .325 (8.26) .300 (7.62)

15 REF

.430 (10.9) MAX .012 (.305) .008 (.203) .020 (.508) .013 (.330) PIN 1 .157 (3.99) .150 (3.81) .244 (6.20) .228 (5.79) .050 (1.27) BSC .196 (4.98) .189 (4.80) .068 (1.73) .053 (1.35) .010 (.254) .004 (.102) 8 REF .010 (.254) .007 (.203) .050 (1.27) .016 (.406) 6.50 (.256) 6.25 (.246) 0.30 (.012) 0.19 (.008) .65 (.026) BSC 1.05 (.041) 0.80 (.033) 3.10 (.122) 4.5 (.177) 2.90 (.114) 4.3 (.169) 0.15 (.006) 0.05 (.002) 1.20 (.047) MAX 0.20 (.008) 0.75 (.030) 0.09 (.004) 0.45 (.018)0

8 REF

8P3, 8-Lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) Dimensions in Inches and (Millimeters) 8S1, 8-Lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) Dimensions in Inches and (Millimeters) 8T, 8-Lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP) Dimensions in Millimeters and (Inches)