AT28BV256 ATMEL | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 18
Technical content
Features
- Single 2.7V - 3.6V Supply Fast Read Access Time – 200 ns Automatic Page Write Operation – Internal Address and Data Latches for 64 Bytes – Internal Control Timer Fast Write Cycle Times – Page Write Cycle Time: 10 ms Maximum – 1- to 64-byte Page Write Operation Low Power Dissipation – 15 mA Active Current –2 0 µA CMOS Standby Current Hardware and Software Data Protection Data Polling for End of Write Detection High Reliability CMOS Technology – Endurance: 10,000 Cycles – Data Retention: 10 Years JEDEC Approved Byte-wide Pinout Industrial Temperature Ranges Green (Pb/Halide-free) Packaging Option 1. Description The AT28BV256 is a high-performance elec trically erasable and programmable read- only memory. Its 256K of memory is organized as 32,768 words by 8 bits. Manufac- tured with Atmel’s advanced nonvolatile CMOS technology, the device offers access times to 200 ns with power dissipation of just 54 mW. When the device is deselected, the CMOS standby current is less than 200 µA. The AT28BV256 is accessed like a Static RAM for the read or write cycle without the need for external components. The device contains a 64-byte page register to allow writing of up to 64 bytes simultaneously. During a write cycle, the addresses and 1 to 64 bytes of data are internally latched, freeing the address and data bus for other operations. Following the initiation of a writ e cycle, the device will automatically write the latched data using an internal control timer. The end of a write cycle can be detected by Data polling of I/O7. Once the end of a write cycle has been detected a new access for a read or write can begin. Atmel’s AT28BV256 has additional features to ensure high quality and manufactura- bility. The device utilizes internal erro r correction for extended endurance and improved data retention characteristics. An optional software data protection mecha- nism is available to guard against inadvert ent writes. The device also includes an extra 64 bytes of EEPROM for device identification or tracking. 256K (32K x 8) Battery-Voltage Parallel EEPROMs AT28BV256 0273J–PEEPR–10/06
0273J–PEEPR–10/06 AT28BV256 2. Pin Configurations 2.1 32-lead PLCC – Top View Note: 1. PLCC package pins 1 and 17 are Don’t Connect. Pin Name Function A0 - A14 Addresses CE Chip Enable OE Output Enable WE Write Enable I/O0 - I/O7 Data Inputs/Outputs NC No Connect DC Don’t Connect NC I/O0 A11 NC OE A10 CE I/O7 I/O6 I/O1 I/O2 GND DC I/O3 I/O4 I/O5 A12 A14 DC VCC WE A13 2.2 28-lead PDIP, SOIC – Top View 2.3 28-lead TSOP – Top View A14 A12 I/O0 I/O1 I/O2 GND VCC WE A13 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 OE A11 A13 WE VCC A14 A12 A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0
0273J–PEEPR–10/06 AT28BV256 3. Block Diagram 4. Absolute Maximum Ratings* Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability All Input Voltages (including NC Pins) All Output Voltages CC + 0.6V Voltage on OE and A9
0273J–PEEPR–10/06 AT28BV256 5. Device Operation
5.1 Read
The AT28BV256 is accessed like a Static RAM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state when either CE or OE is high. This dual-line control gives designers flexibility in preventing bus contention in their system.
5.2 Byte Write
A low pulse on the WE or CE input with CE or WE low (respectively) and OE high initiates a write cycle. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Once a byte write has been started, it will automati- cally time itself to completion. Once a programming operation has been initiated and for the duration of t WC, a read operation will effectively be a polling operation.
5.3 Page Write
The page write operation of the AT28BV256 allows 1 to 64 bytes of data to be written into the device during a single internal programming period. A page write operation is initiated in the same manner as a byte write; the first byte written can then be followed by 1 to 63 additional bytes. Each successive byte must be written within 150 µs (t BLC) of the previous byte. If the t BLC limit is exceeded the AT28BV256 will cease accepting data and commence the internal pro- gramming operation. All bytes during a page write operation must reside on the same page as defined by the state of the A6 - A14 inputs. For each WE high to low transition during the page write operation, A6 - A14 must be the same. The A0 to A5 inputs are used to specify which bytes within the page are to be written. The bytes may be loaded in any order and may be altered within the same load period. Only bytes which are specified for writing will be wr itten; unnecessary cycling of other bytes within the page does not occur.
5.4 Data Polling
The AT28BV256 features Data Polling to indicate the end of a write cycle. During a byte or page write cycle, an attempted read of the last byte written will result in the complement of the written data to be presented on I/O7. Once the write cycle has been completed, true data is valid on all outputs, and the next write cycle may begin. Data Polling may begin at anytime during the write cycle.
5.5 Toggle Bit
In addition to Data Polling, the AT28BV256 pr ovides another method for determining the end of a write cycle. During the write operation, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the write has completed, I/O6 will stop tog- gling and valid data will be read. Reading the toggle bit may begin at any time during the write cycle.
5.6 Data Protection
If precautions are not taken, inadvertent writes may occur during transitions of the host system power supply. Atmel® has incorporated both hardware and software features that will protect the memory against inadvertent writes.
0273J–PEEPR–10/06 AT28BV256
5.6.1 Hardware Protection
Hardware features protect against inadvertent writes to the AT28BV256 in the following ways: (a) VCC power-on delay – once V CC has reached 1.8V (typical) the device will automatically time out 10 ms (typical) before allowing a write; (b) write inhibit – holding any one of OE low, CE high or WE high inhibits write cycles; and (c) noise filter – pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a write cycle.
5.6.2 Software Data Protection
A software-controlled data protection feature has been implemented on the AT28BV256. Soft- ware data protection (SDP) helps prevent inadvertent writes from corrupting the data in the device. SDP can prevent inadver tent writes during power-up and power-down as well as any other potential periods of system instability. The AT28BV256 can only be written using the software data protection feature. A series of three write commands to specific addresses with specific data must be presented to the device before writing in the byte or page mode. The same three write commands must begin each write opera- tion. All software write commands must obey the page mode write timing specifications. The data in the 3-byte command sequence is not written to the device; the address in the command sequence can be utilized just like any other location in the device. Any attempt to write to the device without the 3-byte sequence will start the internal write timers. No data will be written to the device; however, for the duration of t WC, read operations will effec- tively be polling operations.
5.7 Device Identification
An extra 64 bytes of EEPROM memory are available to the user for device identification. By rais- ing A9 to 12V ± 0.5V and using address locations 7FC0H to 7FFFH the additional bytes may be written to or read from in the same manner as the regular memory array.
0273J–PEEPR–10/06 AT28BV256 Notes: 1. X can be V IL or VIH. 2. Refer to AC programming waveforms. 3. V H = 12.0V ± 0.5V. 6. DC and AC Operating Range AT28BV256-20 Operating Temperature (Case) -40°C - 85°C V CC Power Supply 2.7V - 3.6V 7. Operating Modes Mode CE OE WE I/O Read V IL VIL VIH DOUT Write(2) VIL VIH VIL DIN Standby/Write Inhibit V IH X(1) X High Z Write Inhibit X X V IH Write Inhibit X V IL X Output Disable X V IH X High Z Chip Erase V IL VH (3) VIL High Z 8. DC Characteristics Symbol Parameter Condition Min Max Units ILI Input Load Current V IN = 0V to VCC + 1V 10 µA ILO Output Leakage Current V I/O = 0V to VCC 10 µA ISB VCC Standby Current CMOS CE = VCC - 0.3V to VCC + 1V 50 µA ICC VCC Active Current f = 5 MHz; I OUT = 0 mA 15 mA VIL Input Low Voltage 0.6 V VIH Input High Voltage 2.0 V VOL Output Low Voltage I OL = 1.6 mA 0.3 V VOH Output High Voltage I OH = -100 µA 2.0 V
0273J–PEEPR–10/06 AT28BV256 10. AC Read Waveforms(1)(2)(3)(4) Notes: 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC. 2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change without impact on tACC. 3. t DF is specified from OE or CE whichever occurs first (CL = 5 pF). 4. This parameter is characterized and is not 100% tested. 9. AC Read Characteristics Symbol Parameter AT28BV256-20 UnitsMin Max tACC Address to Output Delay 200 ns tCE (1) CE to Output Delay 200 ns tOE (2) OE to Output Delay 0 80 ns tDF (3)(4) CE or OE to Output Float 0 55 ns tOH Output Hold from OE, CE or Address, whichever occurred first 0 ns tCE tOE tDF tOHtACC
0273J–PEEPR–10/06 AT28BV256 11. Input Test Waveforms and Measurement Level 12. Output Test Load Note: 1. This parameter is characterized and is not 100% tested. tR, tF < 20 ns 13. Pin Capacitance f = 1 MHz, T = 25°C(1) Symbol Typ Max Units Conditions CIN 46 p F V IN = 0V COUT 81 2 p F V OUT = 0V
0273J–PEEPR–10/06 AT28BV256 Note: 1. NR = No Restriction. 15. AC Write Waveforms
15.1 WE Controlled
15.2 CE Controlled
- AC Write Characteristics Symbol Parameter Min Max Units tAS, tOES Address, OE Set-up Time 0 ns tAH Address Hold Time 50 ns tCS Chip Select Set-up Time 0 ns tCH Chip Select Hold Time 0 ns tWP Write Pulse Width (WE or CE)2 0 0 n s tDS Data Set-up Time 50 ns tDH, tOEH Data, OE Hold Time 0 ns tDV Time to Data Valid NR (1) tOEH tAS tAH tCH tCS tWPH tWP tDV tDS tDH tOES tOES tOEH tAH tCH tWPH tDH tAS tCS tWP tDV tDS
0273J–PEEPR–10/06 AT28BV256 17. Programming Algorithm (1)(2)(3) Notes: 1. Data Format: I/O7 - I/O0 (He x); Address Format: A14 - A0 (Hex). 2. Data protect state will be re-activated at the end of program cycle. 3. 1 to 64 bytes of data are loaded. 18. Software Protected Program Cycle Waveforms(1)(2)(3) Notes: 1. A0 - A14 must conform to the addressing sequence for the first three bytes as shown above. 2. A6 through A14 must specify the same page address during each high to low transition of WE (or CE) after the software code has been entered. 3. OE must be high only when WE and CE are both low. 16. Page Mode Characteristics Symbol Parameter Min Max Units tWC Write Cycle Time 10 ms tAS Address Set-up Time 0 ns tAH Address Hold Time 50 ns tDS Data Set-up Time 50 ns tDH Data Hold Time 0 ns tWP Write Pulse Width 200 ns tBLC Byte Load Cycle Time 150 µs tWPH Write Pulse Width High 100 ns LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA A0 TO ADDRESS 5555 LOAD DATA XX TO ANY ADDRESS(3) LOAD LAST BYTE TO LAST ADDRESS(3) ENTER DATA PROTECT STATE WRITES ENABLED (2) tAS tAH tWP tWPH tBLC tDH tWC tDS
0273J–PEEPR–10/06 AT28BV256 Notes: 1. These parameters are characterized and not 100% tested. 2. See “AC Read Characteristics” on page 7. 20. Data Polling Waveforms Notes: 1. These parameters are characterized and not 100% tested. 2. See “AC Read Characteristics” on page 7. 22. Toggle Bit Waveforms Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit. 2. Beginning and ending state of I/O6 will vary. 3. Any address location may be used but the address should not vary. 19. Data Polling Characteristics(1) Symbol Parameter Min Typ Max Units tDH Data Hold Time 0 ns tOEH OE Hold Time 0 ns tOE OE to Output Delay(2) ns tWR Write Recovery Time 0 ns tDH tOEH tOE tWR 21. Toggle Bit Characteristics(1) Symbol Parameter Min Typ Max Units tDH Data Hold Time 10 ns tOEH OE Hold Time 10 ns tOE OE to Output Delay(2) ns tOEHP OE High Pulse 150 ns tWR Write Recovery Time 0 ns tDH tOE tWR tOEH
0273J–PEEPR–10/06 AT28BV256 23. Normalized I CC Graphs
0273J–PEEPR–10/06 AT28BV256 24. Ordering Information Note: 1. See Valid Part Numbers table below. 25. Standard Package tACC (ns) ICC (mA) Ordering Code Package Operation RangeActive Standby 200 15 0.02 AT28BV256-20JI AT28BV256-20PI AT28BV256-20SI AT28BV256-20TI 32J 28P6 28S 28T Industrial (-40° to 85° C) 26. Green Package Option (Pb/Halide-free) tACC (ns) ICC (mA) Ordering Code Package Operation RangeActive Standby 200 15 0.02 AT28BV256-20JU AT28BV256-20TU AT28BV256-20SU AT28BV256-20PU 32J 28T 27S 28T Industrial (-40° to 85° C) 27. Valid Part Numbers The following table lists standard Atmel products that can be ordered. Device Numbers Speed Package and Temperature Combinations AT28BV256 20 JI, PI, SI, TI, TU, JU, SU, PU 28. Die Products Reference Section: Parallel EEPROM Die Products Package Type 32J 32-lead, Plastic J-leaded Chip Carrier (PLCC) 28P6 28-lead, 0.600" Wide, Plastic Dual Inline Package (PDIP) 28S 28-lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC) 28T 28-lead, Plastic Thin Small Outline Package (TSOP)
0273J–PEEPR–10/06 AT28BV256 29. Packaging Information 29.1 32J – PLCC DRAWING NO. REV.
2325 Orchard Parkway
San Jose, CA 95131R TITLE 32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC) B32J 10/04/01 1.14(0.045) X 45˚ PIN NO. 1 IDENTIFIER 1.14(0.045) X 45˚ 0.51(0.020)MAX 0.318(0.0125) 0.191(0.0075) 45˚ MAX (3X) A B1 E2 B e E1 E D COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE Notes: 1. This package conforms to JEDEC reference MS-016, Variation AE. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. Lead coplanarity is 0.004" (0.102 mm) maximum. A 3.175 – 3.556 A1 1.524 – 2.413 A2 0.381 – – D 12.319 – 12.573 D1 11.354 – 11.506 Note 2 D2 9.906 – 10.922 E 14.859 – 15.113 E1 13.894 – 14.046 Note 2 E2 12.471 – 13.487 B 0.660 – 0.813 B1 0.330 – 0.533 e 1.270 TYP
0273J–PEEPR–10/06 AT28BV256 29.2 28P6 – PDIP San Jose, CA 95131 TITLE DRAWING NO. R REV. 28P6, 28-lead (0.600"/15.24 mm Wide) Plastic Dual Inline Package (PDIP) B28P6 09/28/01 PIN B REF E C L SEATING PLANE A 0º ~ 15º D e eB COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A – – 4.826 A1 0.381 – – D 36.703 – 37.338 Note 2 E 15.240 – 15.875 E1 13.462 – 13.970 Note 2 B 0.356 – 0.559 B1 1.041 – 1.651 L 3.048 – 3.556 C 0.203 – 0.381 eB 15.494 – 17.526 e 2.540 TYP Notes: 1. This package conforms to JEDEC reference MS-011, Variation AB. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").
0273J–PEEPR–10/06 AT28BV256 29.3 28S – SOIC San Jose, CA 95131 TITLE DRAWING NO. R REV. 28S, 28-lead, 0.300" Body, Plastic Gull Wing Small Outline (SOIC) JEDEC Standard MS-013 B28S 8/4/03 Dimensions in Millimeters and (Inches). Controlling dimension: Millimeters. TOP VIEW SIDE VIEWS 0.51(0.020) 0.33(0.013) 7.60(0.2992) 7.40(0.2914) 10.65(0.419) 10.00(0.394) 1.27(0.50) BSC 2.65(0.1043) 2.35(0.0926) 18.10(0.7125) 17.70(0.6969) 0.30(0.0118) 0.10(0.0040) 0.32(0.0125) 0.23(0.0091) 1.27(0.050) 0.40(0.016) 0º ~ 8º PIN 1
0273J–PEEPR–10/06 AT28BV256 29.4 28T – TSOP San Jose, CA 95131 TITLE DRAWING NO. R REV. 28T, 28-lead (8 x 13.4 mm) Plastic Thin Small Outline Package, Type I (TSOP) C28T 12/06/02 PIN 1 0º ~ 5º D1 D Pin 1 Identifier Area be E A c L GAGE PLANESEATING PLANE COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE Notes: 1. This package conforms to JEDEC reference MO-183. 2. Dimensions D1 and E do not include mold protrusion. Allowable protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side. 3. Lead coplanarity is 0.10 mm maximum. A – – 1.20 A1 0.05 – 0.15 A2 0.90 1.00 1.05 D 13.20 13.40 13.60 D1 11.70 11.80 11.90 Note 2 E 7.90 8.00 8.10 Note 2 L 0.50 0.60 0.70 L1 0.25 BASIC b 0.17 0.22 0.27 c 0.10 – 0.21 e 0.55 BASIC
Printed on recycled paper. 0273J–PEEPR–10/06 Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL ’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL ’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTOR Y WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICU LAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR I NCIDEN- TAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF AT MEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the ri ght to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained her ein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not int ended, authorized, or warranted for use as components in applications intended to support or sustain life. Atmel Corporation Atmel Operations San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza
77 Mody Road Tsimshatsui
Tel: (852) 2721-9778 Fax: (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Memory San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 Microcontrollers San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602
44306 Nantes Cedex 3, France
13106 Rousset Cedex, France
1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300 Fax: 1(719) 540-1759 Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 0QR, Scotland Tel: (44) 1355-803-000 Fax: (44) 1355-242-743 RF/Automotive Theresienstrasse 2 Postfach 3535
74025 Heilbronn, Germany
1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300 Fax: 1(719) 540-1759 Biometrics/Imaging/Hi-Rel MPU/ High-Speed Converters/RF Datacom Avenue de Rochepleine BP 123
38521 Saint-Egreve Cedex, France
www.atmel.com/literature © 2006 Atmel Corporation. All rights reserved. Atmel ®, logo and combinations thereof, Everywhere Y ou Are ® and others are registered trade- marks or trademarks of Atmel Corporation or its subsidiari es. Other terms and product names may be trademarks of others.