AT25080A_14 ATMEL | Alldatasheet
Document overview
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Technical content
Features
- Serial Peripheral Interface (SPI) Compatible Supports SPI Modes 0 (0,0) and 3 (1,1) – Data Sheet Describes Mode 0 Operation Medium-voltage and Standard-voltage Operation – 5.0 (V CC = 4.5V to 5.5V) – 2.7 (V CC = 2.7V to 5.5V) 5.0 MHz Clock Rate (5V) 32-byte Page Mode Block Write Protection – Protect 1/4, 1/2, or Entire Array Write Protect (WP) Pin and Write Disable Instructions for both Hardware and Software Data Protection Self-timed Write Cycle (2 ms [5V] typical) High Reliability – Endurance: One Million Write Cycles – Data Retention: 100 Years 8-lead PDIP and 8-lead JEDEC SOIC Packages
Description
The AT25080A/160A/320A/640A provides 8192/16384/32768/65536 bits of serial electrically-erasable programmable read-only memory (EEPROM) organized as 1024/2048/4096/8192 words of 8 bits each. The device is optimized for use in many automotive applications where low-power and low-voltage operation are essential. The AT25080A/160A/320A/640A is available in space saving 8-lead PDIP and 8-lead JEDEC SOIC packages. The AT25080A/160A/320A/640A is enabled through the Chip Select pin (CS ) and accessed via a three-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). All programming cycles are completely self- timed, and no separate erase cycle is required before write. Block write protection is enabled by programming the status register with one of four blocks of write protection. Separate program enable and program disable instructions are provided for additional data protection. Hardware data protection is provided via the WP pin to protect against inadvertent write attempts to the status register. The HOLD pin may be used to sus- pend any serial communication without resetting the serial sequence. Table 1. Pin Configuration
2 AT25080A/160A/320A/640A
Figure 1. Block Diagram
Table 2. Pin Capacitance(1) Note: 1. This parameter is characterized and is not 100% tested. Table 3. DC Characteristics (1) Note: 1. V IL min and VIH max are reference only and are not tested.
- Worst case measured at 125 °C
Applicable over recommended operating range from T A = 25°C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted).
4 AT25080A/160A/320A/640A
Note: 1. This parameter is characterized and is not 100% tested. Table 4. AC Characteristics CL = 1 TTL Gate and 100 pF (unless otherwise noted).
3401C–SEEPR–8/04 Serial Interface MASTER: The device that generates the serial clock. SLAVE: Because the Serial Clock pin (SCK) is always an input, the AT25080A/160A/320A/640A always operates as a slave. TRANSMITTER/RECEIVER: The AT25080A/160A/320A/640A has separate pins designated for data transmission (SO) and reception (SI). MSB: The Most Significant Bit (MSB) is the first bit transmitted and received. SERIAL OP-CODE: After the device is selected with CS going low, the first byte will be received. This byte contains the op-code that defines the operations to be performed. INVALID OP-CODE: If an invalid op-code is received, no data will be shifted into the AT25080A/160A/320A/640A, and the serial output pin (SO) will remain in a high impedance state until the falling edge of CS is detected again. This will reinitialize the serial communication. CHIP SELECT: The AT25080A/160A/320A/640A is selected when the CS pin is low. When the device is not selected, data will not be accepted via the SI pin, and the serial output pin (SO) will remain in a high impedance state. HOLD: The HOLD pin is used in conjunction with the CS pin to select the AT25080A/160A/320A/640A. When the device is selected and a serial sequence is underway, HOLD can be used to pause the serial communication with the master device without resetting the serial sequence. To pause, the HOLD pin must be brought low while the SCK pin is low. To resume serial communication, the HOLD pin is brought high while the SCK pin is low (SCK may still toggle during HOLD ). Inputs to the SI pin will be ignored while the SO pin is in the high impedance state. WRITE PROTECT: The write protect pin (WP ) will allow normal read/write operations when held high. When the WP pin is brought low and WPEN bit is “1”, all write operations to the sta- tus register are inhibited. WP going low while CS is still low will interrupt a write to the status register. If the internal write cycle has already been initiated, WP going low will have no effect on any write operation to the status register. The WP pin function is blocked when the WPEN bit in the status register is "0". This will allow the user to install the AT25080A/ 160A/320A/640A in a system with the WP pin tied to ground and still be able to write to the status register. All WP pin functions are enabled when the WPEN bit is set to “1”.
6 AT25080A/160A/320A/640A
Figure 2. SPI Serial Interface
3401C–SEEPR–8/04 Functional The AT25080A/160A/320A/640A is designed to interface directly with the synchronous serial peripheral interface (SPI) of the 6805 and 68HC11 series of microcontrollers. The AT25080A/160A/320A/640A utilizes an 8-bit instruction register. The list of instructions and their operation codes are contained in Table 5. All instructions, addresses, and data are transferred with the MSB first and start with a high-to-low CS transition. WRITE ENABLE (WREN): The device will power-up in the write disable state when V CC is applied. All programming instructions must therefore be preceded by a Write Enable instruction. WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the Write Disable instruction disables all programming modes. The WRDI instruction is independent of the sta- tus of the WP pin. READ STATUS REGISTER (RDSR): The Read Status Register instruction provides access to the status register. The READY/BUSY and Write Enable status of the device can be deter- mined by the RDSR instruction. Similarly, the Block Write Protection bits indicate the extent of protection employed. These bits are set by using the WRSR instruction. Table 5. Instruction Set for the AT25080A/160A/320A/640A Table 6. Status Register Format Table 7. Read Status Register Bit Definition Bit 2 (BP0) See Table 8 on page 8. Bit 3 (BP1) See Table 8 on page 8. Bits 4–6 are “0”s when device is not in an internal write cycle. Bit 7 (WPEN) See Table 9 on page 8. Bits 0–7 are “1”s during an internal write cycle.
8 AT25080A/160A/320A/640A
four levels of protection. The AT25080A/160A/320A/640A is divided into four array segments. sponding status register control bits are shown in Table 8. memory that are not block-protected. Table 8. Block Write Protect Bits Table 9. WPEN Operation
0 X 0 Protected Protected Protected
0 X 1 Protected Writable Writable
1 Low 0 Protected Protected Protected
1 Low 1 Protected Writable Protected
since the byte address is automatically incremented and data will continue to be shifted out. allowing the entire memory to be read in one continuous read cycle. be ignored except the RDSR instruction. low-time immediately after clocking in the D0 (LSB) data bit. has ended. Only the RDSR instruction is enabled during the write programming cycle. to reinitiate the serial communication. Table 10. Address Key
10 AT25080A/160A/320A/640A
Figure 3. Synchronous Data Timing (for Mode 0) Figure 4. WREN Timing Figure 5. WRDI Timing
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Figure 8. READ Timing Figure 9. WRITE Timing Figure 10. HOLD Timing
3401C–SEEPR–8/04 Ordering Code Package Operation Range A T25080A-10PA-5.0C A T25080AN-10SA-5.0C 8P3 8S1 Automotive (−40°C to 125°C) A T25080A-10PA-2.7C A T25080AN-10SA-2.7C 8P3 8S1 Automotive (−40°C to 125°C) Package Type 8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) Options −5.0 Standard Device (4.5V to 5.5V) −2.7 Low Voltage (2.7V to 5.5V)
14 AT25080A/160A/320A/640A
3401C–SEEPR–8/04 Ordering Code Package Operation Range A T25160A-10PA-5.0C A T25160AN-10SA-5.0C 8P3 8S1 Automotive (−40°C to 125°C) A T25160A-10PA-2.7C A T25160AN-10SA-2.7C 8P3 8S1 Automotive (−40°C to 125°C) Package Type 8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) Options −5.0 Standard Device (4.5V to 5.5V) −2.7 Low Voltage (2.7V to 5.5V)
3401C–SEEPR–8/04 Ordering Code Package Operation Range A T25320A-10PA-5.0C A T25320AN-10SA-5.0C 8P3 8S1 Automotive (−40°C to 125°C) A T25320A-10PA-2.7C A T25320AN-10SA-2.7C 8P3 8S1 Automotive (−40°C to 125°C) Package Type 8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) Options −5.0 Standard Device (4.5V to 5.5V) −2.7 Low Voltage (2.7V to 5.5V)
16 AT25080A/160A/320A/640A
3401C–SEEPR–8/04 Ordering Code Package Operation Range A T25640A-10PA-5.0C A T25640AN-10SA-5.0C 8P3 8S1 Automotive (−40°C to 125°C) A T25640A-10PA-2.7C A T25640AN-10SA-2.7C 8P3 8S1 Automotive (−40°C to 125°C) Package Type 8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) Options −5.0 Standard Device (4.5V to 5.5V) −2.7 Low Voltage (2.7V to 5.5V)
3401C–SEEPR–8/04 Packaging Information 8P3 – PDIP
2325 Orchard Parkway
San Jose, CA 95131 TITLE DRAWING NO. R REV. 8P3, 8-lead, 0.300" Wide Body, Plastic Dual In-line Package (PDIP) 01/09/02 8P3 B Notes: 1. Thi s drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA, for additional information. 2. Dimen sions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3. 3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch. 4. E and eA measured with the leads constrained to be perpendicular to datum. 5. Pointed or ro unded lead tips are preferred to ease insertion. COMMON DIMENSIONS (Unit of Measure = inches) SYMBOL MIN NOM MAX NOTE D E e Lb2 b A2 A N eA c
4 PLCS
A – – 0.210 2 A2 0.115 0.1 30 0.195 b 0.014 0.01 8 0.022 5 b2 0.045 0.060 0.070 6 b3 0.0 30 0.0 39 0.045 6 c 0.00 8 0.010 0.014 D 0. 355 0. 365 0.400 3 D1 0.005 – – 3 E 0. 300 0. 310 0. 325 4 E1 0.240 0.250 0.2 80 3 e 0.100 B SC eA 0. 300 BSC 4 L 0.115 0.1 30 0.150 2 Top View Side View End View
18 AT25080A/160A/320A/640A
3401C–SEEPR–8/04 8S1 – JEDEC SOIC 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TITLE DRAWING NO. R REV. Note: 10/7/03 8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC) 8S1 B COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A1 0.10 – 0.25 These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. A 1. 35 – 1.75 b 0. 31 – 0.51 C 0.17 – 0.25 D 4. 80 – 5.00 E1 3.81 – 3.99 E 5.79 – 6.20 e 1.27 B SC L 0.40 – 1.27 ∅ 0° – 8° Top View End View Side View e B D A N E C L
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