AT25080A-10TI-2.7

AT25640A ATMEL | Alldatasheet

Document overview

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Technical content

Features

• Serial Peripheral Interface (SPI) Compatible
• Supports SPI Modes 0 (0,0) and 3 (1,1) – Data Sheet Describes Mode 0 Operation
• Medium-voltage and Standard-voltage Operation – 2.7 (VCC = 2.7V to 5.5V)
• Extended Temperature Range –40°C to 125°C
• 5.0 MHz Clock Rate
• 32-byte Page Mode
• Block Write Protection – Protect 1/4, 1/2, or Entire Array
• Write Protect (WP) Pin and Write Disable Instructions for Both Hardware and Software Data Protection
• Self-timed Write Cycle (2 ms [5V] typical)
• High Reliability – Endurance: One Million Write Cycles – Data Retention: 100 Years
• 8-lead PDIP, 8-lead JEDEC SOIC Packages and 8-lead TSSOP Packages

Description

The AT25080A/160A/320A/640A provides 8192/16384/32768/65536 bits of serial electrically-erasable programmable read-only memory (EEPROM) organized as 1024/2048/4096/8192 words of 8 bits each. The device is optimized for use in many automotive applications where low-power and low-voltage operation are essential. The AT25080A/160A/320A/640A is available in space-saving 8-lead PDIP, 8-lead JEDEC SOIC and 8-lead TSSOP packages. The AT25080A/160A/320A/640A is enabled through the Chip Select pin (CS) and accessed via a three-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). All programming cycles are completely self- timed, and no separate erase cycle is required before write. Block write protection is enabled by programming the status register with one of four blocks of write protection. Separate program enable and program disable instructions are provided for additional data protection. Hardware data protection is provided via the WP pin to protect against inadvertent write attempts to the status register. The HOLD pin may be used to suspend any serial communication without resetting the serial sequence. Table 1. Pin Configurations

Figure 1. Block Diagram

Table 2. Pin Capacitance(1)

1. This parameter is characterized and is not 100% tested.

Table 3. DC Characteristics

1. Worst case measured at 125°C
2. VIL min and VIH max are reference only and are not tested.

1. This parameter is characterized and is not 100% tested.

Table 4. AC Characteristics CL = 1 TTL Gate and 100 pF (unless otherwise noted).

5082B–SEEPR–1/05 Serial Interface MASTER: The device that generates the serial clock. SLAVE: Because the serial clock pin (SCK) is always an input, the AT25080A/160A/320A/640A always operates as a slave. TRANSMITTER/RECEIVER: The AT25080A/160A/320A/640A has separate pins des- ignated for data transmission (SO) and reception (SI). MSB: The Most Significant Bit (MSB) is the first bit transmitted and received. SERIAL OP-CODE: After the device is selected with CS going low, the first byte will be received. This byte contains the op-code that defines the operations to be performed. INVALID OP-CODE: If an invalid op-code is received, no data will be shifted into the AT25080A/160A/320A/640A, and the serial output pin (SO) will remain in a high imped- ance state until the falling edge of CS is detected again. This will reinitialize the serial communication. CHIP SELECT: The AT25080A/160A/320A/640A is selected when the CS pin is low. When the device is not selected, data will not be accepted via the SI pin, and the serial output pin (SO) will remain in a high impedance state. HOLD: The HOLD pin is used in conjunction with the CS pin to select the AT25080A/160A/320A/640A. When the device is selected and a serial sequence is underway, HOLD can be used to pause the serial communication with the master device without resetting the serial sequence. To pause, the HOLD pin must be brought low while the SCK pin is low. To resume serial communication, the HOLD pin is brought high while the SCK pin is low (SCK may still toggle during HOLD). Inputs to the SI pin will be ignored while the SO pin is in the high impedance state. WRITE PROTECT: The write protect pin (WP) will allow normal read/write operations when held high. When the WP pin is brought low and WPEN bit is “1”, all write opera- tions to the status register are inhibited. WP going low while CS is still low will interrupt a write to the status register. If the internal write cycle has already been initiated, WP going low will have no effect on any write operation to the status register. The WP pin function is blocked when the WPEN bit in the status register is "0". This will allow the user to install the AT25080A/160A/320A/640A in a system with the WP pin tied to ground and still be able to write to the status register. All WP pin functions are enabled when the WPEN bit is set to “1”.

Figure 2. SPI Serial Interface

5082B–SEEPR–1/05 Functional The AT25080A/160A/320A/640A is designed to interface directly with the synchronous serial peripheral interface (SPI) of the 6805 and 68HC11 series of microcontrollers. The AT25080A/160A/320A/640A utilizes an 8-bit instruction register. The list of instruc- tions and their operation codes are contained in Table 5. All instructions, addresses, and data are transferred with the MSB first and start with a high-to-low CS transition. WRITE ENABLE (WREN): The device will power up in the write disable state when VCC is applied. All programming instructions must therefore be preceded by a Write Enable instruction. WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the Write Disable instruction disables all programming modes. The WRDI instruction is indepen- dent of the status of the WP pin. READ STATUS REGISTER (RDSR): The Read Status Register instruction provides access to the status register. The READY/BUSY and Write Enable status of the device can be determined by the RDSR instruction. Similarly, the block write protection bits indicate the extent of protection employed. These bits are set by using the WRSR instruction. Table 5. Instruction Set for the AT25080A/160A/320A/640A

0000 X110

0000 X100

0000 X101

0000 X001

0000 X011

0000 X010

Table 6. Status Register Format Table 7. Read Status Register Bit Definition Bits 4 − 6 are “0”s when device is not in an internal write cycle. Bits 0 − 7 are “1”s during an internal write cycle.

array segments. One-quarter, one-half, or all of the memory segments can be protected. protection levels and corresponding status register control bits are shown in Table 8. tions as the regular memory cells (e.g., WREN, tWC, RDSR). are only allowed to sections of the memory that are not block-protected. “0” as long as the WP pin is held low. Table 8. Block Write Protect Bits Table 9. WPEN Operation

ignored. The data (D7−D0) at the specified address is then shifted out onto the SO line. If only one byte is to be read, the CS line should be driven high after the data comes out. read in one continuous read cycle. write cycle, all commands will be ignored except the RDSR instruction. must occur during the SCK low-time immediately after clocking in the D0 (LSB) data bit. write disable state at the completion of a write cycle. is required to reinitiate the serial communication. Table 10. Address Key

5082B–SEEPR–1/05 Notes: 1. “Q” designates Green package + RoHS compliant. Ordering Code Package Operation Range AT25080A-10PE-2.7 AT25080AN-10SE-2.7 8P3 8S1 Extended Temperature (−40°C to 125°C) AT25080A-10PQ-2.7(1) AT25080AN-10SQ-2.7(1) AT25080A-10TQ-2.7(1) 8P3 8S1 8A2 Lead-free/Halogen-free Extended Temperature (−40°C to 125°C) Package Type 8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 8A2 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP) Options −2.7 Low Voltage (2.7V to 5.5V)

5082B–SEEPR–1/05 Notes: 1. “Q” designates Green package + RoHS compliant. Ordering Code Package Operation Range AT25160A-10PE-2.7 AT25160AN-10SE-2.7 8P3 8S1 Extended Temperature (−40°C to 125°C) AT25160A-10PQ-2.7(1) AT25160AN-10SQ-2.7(1) AT25160A-10TQ-2.7(1) 8P3 8S1 8A2 Lead-free/Halogen-free Extended Temperature (−40°C to 125°C) Package Type 8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 8A2 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP) Options −2.7 Low Voltage (2.7V to 5.5V)

5082B–SEEPR–1/05 Notes: 1. “Q” designates Green package + RoHS compliant. Ordering Code Package Operation Range AT25320A-10PE-2.7 AT25320AN-10SE-2.7 8P3 8S1 Extended Temperature (−40°C to 125°C) AT25320A-10PQ-2.7(1) AT25320AN-10SQ-2.7(1) AT25320A-10TQ-2.7(1) 8P3 8S1 8A2 Lead-free/Halogen-free Extended Temperature (−40°C to 125°C) Package Type 8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 8A2 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP) Options −2.7 Low Voltage (2.7V to 5.5V)

5082B–SEEPR–1/05 Note: 1. “Q” designates Green package + RoHS compliant. Ordering Code Package Operation Range AT25640A-10PE-2.7 AT25640AN-10SE-2.7 8P3 8S1 Extended Temperature (−40°C to 125°C) AT25640A-10PQ-2.7(1) AT25640AN-10SQ-2.7(1) AT25640A-10TQ-2.7(1) 8P3 8S1 8A2 Lead-free/Halogen-free Extended Temperature (−40°C to 125°C) Package Type 8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 8A2 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP) Options −2.7 Low Voltage (2.7V to 5.5V)

5082B–SEEPR–1/05 Packaging Information 8P3 – PDIP

2325 Orchard Parkway

San Jose, CA 95131 TITLE DRAWING NO. R REV. 8P3, 8-lead, 0.300" Wide Body, Plastic Dual In-line Package (PDIP) 01/09/02 8P3 B Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA, for additional information. 2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3. 3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch. 4. E and eA measured with the leads constrained to be perpendicular to datum. 5. Pointed or rounded lead tips are preferred to ease insertion. COMMON DIMENSIONS (Unit of Measure = inches) SYMBOL MIN NOM MAX NOTE D E e L b A2 A N eA c

4 PLCS

A 0.210 0.115 0.130 0.195 b 0.014 0.018 0.022 0.045 0.060 0.070 0.030 0.039 0.045 c 0.008 0.010 0.014 D 0.355 0.365 0.400 0.005 E 0.300 0.310 0.325 0.240 0.250 0.280 e

0.100 BSC

0.300 BSC

L 0.115 0.130 0.150 Top View Side View End View

5082B–SEEPR–1/05 8S1 – JEDEC SOIC 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TITLE DRAWING NO. R REV. Note: 10/7/03 8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC) 8S1 B COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE 0.10 0.25 These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. A 1.35 1.75 b 0.31 0.51 C 0.17 0.25 D 4.80 5.00 3.81 3.99 E 5.79 6.20 e

1.27 BSC

L 0.40 1.27 Top View End View Side View e B D A N E C L

5082B–SEEPR–1/05 8A2 – TSSOP San Jose, CA 95131 TITLE DRAWING NO. R REV. 5/30/02 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE D 2.90 3.00 3.10 2, 5 E

6.40 BSC

4.30 4.40 4.50 3, 5 A 1.20 0.80 1.00 1.05 b 0.19 0.30 e

0.65 BSC

L 0.45 0.60 0.75

1.00 REF

8A2, 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP) Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances, datums, etc. 2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed 0.15 mm (0.006 in) per side. 3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm (0.010 in) per side. 4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between protrusion and adjacent lead is 0.07 mm. 5. Dimension D and E1 to be determined at Datum Plane H. 8A2 B Side View End View Top View A L D N b Pin 1 indicator this corner E e

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