AT25040AY6-10YH-1.8

AT25010A_06 ATMEL | Alldatasheet

Document overview

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Technical content

Features

 Serial Peripheral Interface (SPI) Compatible  Supports SPI Modes 0 (0,0) and 3 (1,1) – Data Sheet Describes Mode 0 Operation  Low-voltage and Standard-voltage Operation – 2.7 (V CC = 2.7V to 5.5V) – 1.8 (V CC = 1.8V to 5.5V)  20 MHz Clock Rate (5V)  8-byte Page Mode  Block Write Protection – Protect 1/4, 1/2, or Entire Array  Write Protect (WP) Pin and Write Disable Instructions for Both Hardware and Software Data Protection  Self-timed Write Cycle (5 ms max)  High Reliability – Endurance: One Million Write Cycles – Data Retention: 100 Years  Automotive Devices Available  8-lead JEDEC PDIP, 8-lead JEDEC SOIC, 8-lead Ultra Thin mini-MAP (MLP 2x3) and 8- lead TSSOP Packages  Die Sales: Wafer Form, Waffle Pack, Bumped Wafers

Description

The AT25010A/020A/040A provides 1024/2048/4096 bits of serial electrically eras - able programmable read-only memory (EEPROM) organized as 128/256/512 words of 8 bits each. The device is optimized for use in many industrial and commercial appli - cations where low-power and low-voltage operation are essential. The AT25010A/020A/040A is available in space saving 8-lead PDIP , 8-lead JEDEC SOIC, 8-lead Ultra Thin mini-MAP (MLP 2x3), and 8-lead TSSOP packages. The AT25010A/020A/040A is enabled through the Chip Select pin (CS) and accessed via a three-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). All programming cycles are completely self-timed, and no separate erase cycle is required before write. Block write protection is enabled by programming the status register with one of four blocks of write protection. Separate Program Enable and Program disable instructions are provided for additional data protection. Hardware data protection is provided via the WP pin to protect against inadvertent write attempts. The HOLD pin may be used to suspend any serial communication without resetting the serial sequence. Table 1. Pin Configuration

2 AT25010A/020A/040A

Figure 1. Block Diagram

Table 2. Pin Capacitance (1) Note: 1. This parameter is characterized and is not 100% tested. Table 3. DC Characteristics(1) Note: 1. V IL min and VIH max are reference only and are not tested.

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Table 4. AC Characteristics

Note: 1. This parameter is characterized and is not 100% tested. Table 4. AC Characteristics (Continued)

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3348J–SEEPR–8/06 Serial Interface MASTER: The device that generates the serial clock. SLAVE: Because the serial clock pin (SCK) is always an input, the AT25010A/020A/040A always operates as a slave. TRANSMITTER/RECEIVER: The AT25010A/020A/040A has separate pins designated for data transmission (SO) and reception (SI). MSB: The Most Significant Bit (MSB) is the first bit transmitted and received. SERIAL OP-CODE: After the device is selected with CS going low, the first byte will be received. This byte contains the op-code that defines the operations to be performed. The op-code also contains address bit A8 in both the read and write instructions. INVALID OP-CODE: If an invalid op-code is received, no data will be shifted into the AT25010A/020A/040A, and the serial output pin (SO) will remain in a high impedance state until the falling edge of CS is detected again. This will reinitialize the serial communication. CHIP SELECT: The AT25010A/020A/040A is selected when the CS pin is low. When the device is not selected, da ta will not be accepted via the SI pin, and the SO pin will remain in a high impedance state. HOLD: The HOLD pin is used in conjunction with the CS pin to select the AT25010A/020A/040A. When the device is selected and a serial sequence is underway, HOLD can be used to pause the serial communication with the master device without resetting the serial sequence. To pause, the HOLD pin must be brought low while the SCK pin is low. To resume serial communication, the HOLD pin is brought high while the SCK pin is low (SCK may still toggle during HOLD ). Inputs to the SI pin will be ignored while the SO pin is in the high impedance state. WRITE PROTECT: The write protect pin (WP ) will allow normal read/write operations when held high. When the WP pin is brought low, all write operations are inhibited. WP going low while CS is still low will interrupt a writ e to the AT25010A/020A/040A. If the internal write cycle has already been initiated, WP going low will have no effect on any write operation.

Figure 2. SPI Serial Interface

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3348J–SEEPR–8/06 Functional Table 5. Instruction Set for the AT25010A/020A/040A peripheral interface (SPI) of the 6805 and 68HC11 series of microcontrollers. Note: “A” represents MSB address bit A8. Table 6. Status Register Format pin must be held high during a WREN instruction. the extent of protection employed. These bits are set by using the WRSR instruction. Table 7. Read Status Register Bit Definition indicates the write cycle is in progress. indicates the device is write enabled. Bits 4–7 are “0”s when device is not in an internal write cycle. Bits 0–7 are “1”s during an internal write cycle.

tion levels and corresponding status register control bits are shown in Table 8. the regular memory cells (e.g., WREN, tWC, RDSR). ) must be held high and two separate instructions must be executed. except the RDSR instruction. lowed by the byte address (A7 −A0) and the data (D7 −D0) to be programmed. state at the completion of a write cycle. brought high. A new CS falling edge is required to reinitiate the serial communication. Table 8. Block Write Protect Bits

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Figure 3. Synchronous Data Timing (for Mode 0) Figure 4. WREN Timing Figure 5. WRDI Timing

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Figure 9. WRITE Timing Figure 10. HOLD Timing

AT25010A-10PU-2.7(2) AT25010A-10PU-1.8(2) AT25010AN-10SU-2.7(2) AT25010AN-10SU-1.8(2) AT25010A-10TU-2.7(2) AT25010A-10TU-1.8(2) AT25010AY1-10YU-1.8(2) (Not recommended for new designs) AT25010AY6-10YH-1.8(3) 8P3 8P3 8S1 8S1 8A2 8A2 8Y1 8Y6 Lead-free/Halogen-free/ Industrial Temperature (−40 to 85°C) AT25010A-W1.8-11(4) Die Sale Industrial Temperature (−40 to 85°C) AT25010A/020A/040A 3348J–SEEPR–8/06 Notes: 1. For 2.7V devices used in the 4.5 to 5.5V range, please refer to performance values in Table on page 3 and Table 4 on p age 2. “U” designates Green Package + RoHS compliant. 3. “H” designates Green Package + RoHS compliant, with NiPdAu Lead Finish. 4. Available in waffle pack and wafer form; order as SL788 for inkless wafer form. Bumped die available upon request. Please contact Serial EEPROM Marketing. Ordering Code Package Operation Range Package Type 8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC) 8A2 8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP) 8Y1 8-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP) 8Y6 8-lead, 2.00mm x 3.00mm Body, 0.50 mm Pitch, Ultra Thin Mini-MAP , Dual No Lead Package (DFN), (MLP 2x3 mm) Options −2.7 Low Voltage (2.7 to 5.5V) −1.8 Low Voltage (1.8 to 5.5V)

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3348J–SEEPR–8/06 Notes: 1. For 2.7V devices used in the 4.5 to 5.5V range, please refer to performance values in Table on page 3 and Table 4 on p age 2. “U” designates Green Package + RoHS compliant. 3. “H” designates Green Package + RoHS compliant, with NiPdAu Lead Finish. 4. Available in waffle pack and wafer form; order as SL788 for inkless wafer form. Bumped die available upon request. Please contact Serial EEPROM Marketing. Ordering Code Package Operation Range AT25020A-10PU-2.7(2) AT25020A-10PU-1.8(2) AT25020AN-10SU-2.7(2) AT25020AN-10SU-1.8(2) AT25020A-10TU-2.7(2) AT25020A-10TU-1.8(2) AT25020AY1-10YU-1.8(2) (Not recommended for new designs) AT25020AY6-10YH-1.8(3) 8P3 8P3 8S1 8S1 8A2 8A2 8Y1 8Y6 Lead-free/Halogen-free/ Industrial Temperature (−40 to 85°C) AT25020A-W1.8-11 (4) Die Sale Industrial Temperature (−40 to 85°C) Package Type 8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC) 8A2 8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP) 8Y1 8-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP) 8Y6 8-lead, 2.00mm x 3.00mm Body, 0.50 mm Pitch, Ultra Thin Mini-MAP , Dual No Lead Package (DFN), (MLP 2x3 mm) Options −2.7 Low Voltage (2.7 to 5.5V) −1.8 Low Voltage (1.8 to 5.5V)

3348J–SEEPR–8/06 Notes: 1. For 2.7V devices used in the 4.5 to 5.5V range, please refer to performance values in Table on page 3 and Table 4 on p age 2. “U” designates Green Package + RoHS compliant. 3. “H” designates Green Package + RoHS compliant, with NiPdAu Lead Finish. 4. Available in waffle pack and wafer form; order as SL788 for inkless wafer form. Bumped die available upon request. Please contact Serial EEPROM Marketing. Ordering Code Package Operation Range AT25040A-10PU-2.7(2) AT25040A-10PU-1.8(2) AT25040AN-10SU-2.7(2) AT25040AN-10SU-1.8(2) AT25040A-10TU-2.7(2) AT25040A-10TU-1.8(2) AT25040AY1-10YU-1.8(2) (Not recommended for new designs) AT25040AY6-10YH-1.8(3) 8P3 8P3 8S1 8S1 8A2 8A2 8Y1 8Y6 Lead-free/Halogen-free/ Industrial Temperature (−40 to 85°C) AT25040A-W1.8-11 (4) Die Sale Industrial Temperature (−40 to 85°C) Package Type 8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC) 8A2 8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP) 8Y1 8-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP) 8Y6 8-lead, 2.00mm x 3.00mm Body, 0.50 mm Pitch, Ultra Thin Mini-MAP , Dual No Lead Package (DFN), (MLP 2x3 mm) Options −2.7 Low Voltage (2.7 to 5.5V) −1.8 Low Voltage (1.8 to 5.5V)

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3348J–SEEPR–8/06 Packaging Information 8P3 –

2325 Orchard Parkway

San Jose, CA 95131 TITLE DRAWING NO. R REV. 8P3, 8-lead, 0.300" Wide Body, Plastic Dual In-line Package (PDIP) 01/09/02 8P3 B Notes: 1. Thi s drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA, for additional information. 2. Dimen sions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3. 3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch. 4. E and eA measured with the leads constrained to be perpendicular to datum. 5. Pointed or ro unded lead tips are preferred to ease insertion. COMMON DIMENSIONS (Unit of Measure = inches) SYMBOL MIN NOM MAX NOTE D E e Lb2 b A2 A N eA c

4 PLCS

A – – 0.210 2 A2 0.115 0.1 30 0.195 b 0.014 0.01 8 0.022 5 b2 0.045 0.060 0.070 6 b3 0.0 30 0.0 39 0.045 6 c 0.00 8 0.010 0.014 D 0. 355 0. 365 0.400 3 D1 0.005 – – 3 E 0. 300 0. 310 0. 325 4 E1 0.240 0.250 0.2 80 3 e 0.100 B SC eA 0. 300 BSC 4 L 0.115 0.1 30 0.150 2 Top View Side View End View PDIP

3348J–SEEPR–8/06 8S1 – JEDEC SOIC 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TITLE DRAWING NO. R REV. Note: 10/7/03 8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC) 8S1B COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A1 0.10 – 0.25 These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. A1 . 35 – 1.75 b 0.31 – 0.51 C 0.17 – 0.25 D4 . 80 – 5.00 E1 3.81– 3.99 E 5.79 – 6.20 e 1.27 B SC L 0.40 – 1.27 ∅ 0˚ – 8˚ Top View End View Side View e B D A N E C L

18 AT25010A/020A/040A

3348J–SEEPR–8/06 8A2 – TSSOP San Jose, CA 95131 TITLE DRAWING NO. R REV. 5/30/02 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE D 2.90 3.00 3.10 2, 5 E 6.40 BSC E1 4.30 4.40 4.50 3, 5 A – – 1.20 A2 0.80 1.00 1.05 b 0.19 – 0.30 4 e 0.65 BSC L 0.45 0.60 0.75 L1 1.00 REF 8A2, 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP) Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances, datums, etc. 2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed 0.15 mm (0.006 in) per side. 3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm (0.010 in) per side. 4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between protrusion and adjacent lead is 0.07 mm. 5. Dimension D and E1 to be determined at Datum Plane H. 8A2 B Side View End ViewTop View A L D 123 N b Pin 1 indicator this corner E e

3348J–SEEPR–8/06 8Y1 − MAP A – – 0.90 A1 0.00 – 0.05 D 4.70 4.90 5.10 E 2. 80 3.00 3.20 D1 0. 85 1.00 1.15 E1 0. 85 1.00 1.15 b 0.25 0. 30 0. 35 e 0.65 TYP L 0.50 0.60 0.70 PIN 1 INDEX AREA D E A A1 b 8 7 6 e L PIN 1 INDEX AREA 1 2 3 4 A Top View End View Bottom View Side View San Jose, CA 95131 TITLE DRAWING NO. R REV. 8Y1, 8-lead (4.90 x 3.00 mm Body) MSOP Array Package (MAP) Y1 C8Y1 2/28/03 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE

20 AT25010A/020A/040A

3348J–SEEPR–8/06 8Y6 - Mini-Map San Jose, CA 95131 TITLE DRAWING NO. R REV. 8Y6, 8-lead 2.0 x 3.0 mm Body, 0.50 mm Pitch, Utlra Thin Mini-Map, Dual No Lead Package (DFN) ,(MLP 2x3) C8Y6 8/26/05 Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-229, for proper dimensions, tolerances, datums, etc. 2. Dimension b applies to metallized terminal and is measured between 0.15 mm and 0.30 mm from the terminal tip. If the terminal has the optional radius on the other end of the terminal, the dimension should not be measured in that radius area. COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE D 2.00 BSC E 3.00 BSC D2 1.40 1.50 1.60 E2 - - 1.40 A - - 0.60 A1 0.0 0.02 0.05 A2 - - 0.55 A3 0.20 REF L 0.20 0.30 0.40 e 0.50 BSC b 0.20 0.25 0.30 2 b (8X) Pin 1 ID Pin 1 Index Area D E A L (8X) e (6X) 1.50 REF.

3348J–SEEPR–8/06

Revision History

Doc. Rev. Comments AT25040A.

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