AT25010A_07 ATMEL | Alldatasheet
Document overview
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Technical content
Features
- Serial Peripheral Interface (SPI) Compatible Supports SPI Modes 0 (0,0) and 3 (1,1) – Data Sheet Describes Mode 0 Operation Medium-voltage and Standard-voltage Operation –2 . 7 ( VCC = 2.7V to 5.5V) Extended Temperature Range −40°C to +125°C 5.0 MHz Clock Rate 8-byte Page Mode Block Write Protection – Protect 1/4, 1/2, or Entire Array Write Protect (WP) Pin and Write Disable Instructions for Both Hardware and Software Data Protection Self-timed Write Cycle (10 ms max) High Reliability – Endurance: One Million Write Cycles – Data Retention: 100 Years 8-lead JEDEC SOIC and 8-lead TSSOP Packages
Description
The AT25010A/020A/040A provides 1024/2048/4096 bits of serial electrically-eras- able programmable read-only memory (EEPROM) organized as 128/256/512 words of 8 bits each. The device is optimized for use in many automotive applications where low-power and low-voltage operation are essential. The AT25010A/020A/040A is available in space-saving 8-lead JEDEC SOIC and 8-lead TSSOP packages. The AT25010A/020A/040A is enabled through the Chip Select pin (CS ) and accessed via a three-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). All programming cycles are completely self-timed, and no separate erase cycle is required before write. Block write protection is enabled by programming the status register with one of four blocks of write protection. Separate program enable and program disable instructions are provided for additional data protection. Hardware data protection is provided via the WP pin to protect against inadvertent write attempts. The HOLD pin may be used to suspend any serial communication without resetting the serial sequence. Table 1. Pin Configurations
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Figure 1. Block Diagram
Table 2. Pin Capacitance(1) Note: 1. This parameter is characterized and is not 100% tested. Table 3. DC Characteristics
- V IL min and VIH max are reference only and are not tested.
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Note: 1. This parameter is characterized and is not 100% tested. Table 4. AC Characteristics CL = 1 TTL Gate and 100 pF (unless otherwise noted).
5087D–SEEPR–3/07 Serial Interface MASTER: The device that generates the serial clock. SLAVE : Because the serial clock pin (SCK) is always an input, the AT25010A/020A/040A always operates as a slave. TRANSMITTER/RECEIVER: The AT25010A/020A/040A has separate pins designated for data transmission (SO) and reception (SI). MSB: The Most Significant Bit (MSB) is the first bit transmitted and received. SERIAL OP-CODE: After the device is selected with CS going low, the first byte will be received. This byte contains the op-code that defines the operations to be performed. The op-code also contains address bit A8 in both the Read and Write instructions. INVALID OP-CODE: If an invalid op-code is received , no data will be shifted into the AT25010A/020A/040A, and the serial output pin (SO) will remain in a high impedance state until the falling edge of CS is detected again. This will reinitialize the serial communication. CHIP SELECT: The AT25010A/020A/040A is selected when the CS pin is low. When the device is not selected, data will not be a ccepted via the SI pin, and the serial output pin (SO) will remain in a high impedance state. HOLD: The HOLD pin is used in conjunction with the CS pin to select the AT25010A/020A/040A. When the device is selected and a serial sequence is underway, HOLD can be used to pause the serial communication with the master device without resetting the serial sequence. To pause, the HOLD pin must be brought low while the SCK pin is low. To resume serial communication, the HOLD pin is brought high while the SCK pin is low (SCK may still toggle during HOLD ). Inputs to the SI pin will be ignored while the SO pin is in the high impedance state. WRITE PROTECT: The write protect pin (WP ) will allow normal re ad/write operations when held high. When the WP pin is brought low, all write operations are inhibited. WP going low while CS is still low will interrupt a write to the AT25010A/020A/040A. If the internal write cycle has already been initiated, WP going low will have no effect on any write operation.
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Figure 2. SPI Serial Interface
5087D–SEEPR–3/07 Functional The AT25010A/020A/040A is designed to interf ace directly with the synchronous serial peripheral interface (SPI) of the 6805 and 68HC11 series of microcontrollers. The AT25010A/020A/040A utilizes an 8-bit instruction register. The list of instructions and their operation codes are contained in Table 5. All instructions, addresses, and data are transferred with the MSB first and start with a high-to-low CS transition. Note: “A” represents MSB address bit A8. WRITE ENABLE (WREN): The device will power up in the write disable state when VCC is applied. All programming instructions must therefore be preceded by a Write Enable instruction. The WP pin must be held high during a WREN instruction. WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the Write Disable instruction disables all programming modes. The WRDI instruction is indepen- dent of the status of the WP pin. READ STATUS REGISTER (RDSR): The Read Status Register instruction provides access to the status register. The READ Y/BUSY and Write Enable status of the device can be determined by the RDSR instruction. Similarly, the block write protection bits indicate the extent of protection employed. These bits are set by using the WRSR instruction. WRITE STATUS REGISTER (WRSR): The WRSR instruction allows the user to select one of four levels of protection. The AT25010A/020A/040A is divided into four array seg- ments. One-quarter, one-half, or all of the memory segments can be protected. Any of Table 5. Instruction Set for the AT25010A/020A/040A Table 6. Status Register Format Table 7. Read Status Register Bit Definition Bit 2 (BP0) See Table 8 on page 8. Bit 3 (BP1) See Table 8 on page 8. Bits 4 − 6 are “0”s when device is not in an internal write cycle. Bits 0 − 7 are “1”s during an internal write cycle.
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tion levels and corresponding status register control bits are shown in Table 8. the regular memory cells (e.g., WREN, tWC, RDSR). address to be read (A7–A0). Upon completion, any data on the SI line will be ignored. read in one continuous read cycle. ) pin must be held high and two separate instructions must be executed. except the RDSR instruction. lowed by the byte address (A7 −A0) and the data (D7–D0) to be programmed. able state at the completion of a write cycle. brought high. A new CS falling edge is required to reinitiate the serial communication. Table 8. Block Write Protect Bits
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Figure 6. RDSR Timing Figure 7. WRSR Timing
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5087D–SEEPR–3/07 Ordering Code Package Operation Range AT25010AN-10SQ-2.7 AT25010A-10TQ-2.7 8S1 8A2 Lead-free/Halogen-free Automotive Temperature (−40°C to 125°C) Package Type 8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 8A2 8-lead, 0.170” Wide, Thin Shrink Small Outline Package (TSSOP) Options −2.7 Low Voltage (2.7V to 5.5V)
5087D–SEEPR–3/07 Ordering Code Package Operation Range AT25020AN-10SQ-2.7 AT25020A-10TQ-2.7 8S1 8A2 Lead-free/Halogen-free Automotive Temperature (−40°C to 125°C) Package Type 8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 8A2 8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP) Options −2.7 Low Voltage (2.7V to 5.5V)
14 AT25010A/020A/040A
5087D–SEEPR–3/07 Ordering Code Package Operation Range AT25040AN-10SQ-2.7 AT25040A-10TQ-2.7 8S1 8A2 Lead-free/Halogen-free Automotive Temperature (−40°C to 125°C) Package Type 8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 8A2 8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP) Options −2.7 Low Voltage (2.7V to 5.5V)
5087D–SEEPR–3/07 Packaging Information 8S1 – JEDEC SOIC 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TITLE DRAWING NO. R REV. Note: 10/7/03 8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC) 8S1 B COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A1 0.10 – 0.25 These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. A 1.35 – 1.75 b 0.31 – 0.51 C 0.17 – 0.25 D 4.80 – 5.00 E1 3.81 – 3.99 E 5.79 – 6.20 e 1.27 BSC L 0.40 – 1.27 ∅ 0˚ – 8˚ Top View End View Side View e B D A N E C L
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5087D–SEEPR–3/07 8A2 – TSSOP
2325 Orchard Parkway
San Jose, CA 95131 TITLE DRAWING NO. R REV. 5/30/02 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE D 2.90 3.00 3.10 2, 5 E 6.40 BSC E1 4.30 4.40 4.50 3, 5 A – – 1.20 A2 0.80 1.00 1.05 b 0.19 – 0.30 4 e 0.65 BSC L 0.45 0.60 0.75 L1 1.00 REF 8A2, 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP) Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances, datums, etc. 2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed 0.15 mm (0.006 in) per side. 3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm (0.010 in) per side. 4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between protrusion and adjacent lead is 0.07 mm. 5. Dimension D and E1 to be determined at Datum Plane H. 8A2 B Side View End ViewTop View A L D 123 N b Pin 1 indicator this corner E e
5087D–SEEPR–3/07
Revision History
Doc. Rev. Date Comments 5087D 3/2007 Corrected package codes on pages 12 and 13 5087C 2/2007 Implemented revision history Removed PDIP package offering Removed PB’d parts
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