AT24C02

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Technical content

Features

 Single supply with operation down to 1.8v  Low-power CMOS technology:  1 mA active current, typical  1 μA standby current, typical(l-temp)  Organized as 1 block of 256 bytes (1×256×8)  2-wire serial interface bus, l2CTM compatible  Schmitt Trigger inputs for noise suppression  Output slope control to eliminate ground bounce  400 kHz (24C02) compatibility  Self-timed write cycle (including auto-erase)  Page write buffer for up to 8 bytes  Hardware write-protect for entire memory  Can be operated as a serial ROM  Factory programming (QTP) available  ESD protection>2000V  1,000,000 erase/write cycles  Data retention>100 years  8-lead PDIP, SOIC ,TSSOP packages  Pb-free finish available

Description

The 24C02 is a 2Kbit Electrically Erasable PROM, The device is organized as one block of 256 x 8-bit memory with a 2-wire serial interface. Low-voltage design permits operation down to1.8V, with standby and active currents of only 1μA and 1mA, respectively. The 24C02 also has a page write capability for up to 8 bytes of data. The 24C02 is available in the standard 8-pin PDIP, surface mount SOIC, TSSOP package. Part Number VCC Range Max. Clock Frequency AT24C02 1.8-5.5 400KHz HOTCHIP

SERIAL 2K（256×8）EEPROM 第2 页 共 13 页 AT24C02(C) Absolute Maximum Ratings NOTICE: Stresses above those listed under ”Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Ex posure to maximum rating conditions for extended periods may affect device reliability. TABLE 1-1: DC CHARACTERISTICS DC CHARACTERISTICS Param.NO Sym. Characteristic Min. Typ. Max Units Conditions VIH VIL VHYS VOL WP.SCL and SDA pins High-level input voltage Low-level input voltage Hysteresis of Schmitt Trigger inputs Low-level output voltage 0.7V -0.05Vcc 0.3Vcc 0.40 V V V V (NOTE) IOL=3.0Ma, Vcc=1.8V D6 ILI Input leakage current - - ±1 μA VIN=VSS or VCC D7 ILO Output leakage current - - ±1 μA VOUT=VSS or VCC D8 CIN. COUT Pin capacitance (all inputs/outputs) - 10 pF VCC=5.0V (Note) TA= 25℃,FCLK=1MHz D10 Icc write Icc read Operating current - mA mA Vcc=5.5V, SCL=400kHz D11 Iccs Standby current - 0.01 μA μA Industrial Automotive SDA=SCL=Vcc WP=Vss Note: This parameter is periodically sampled and not 100% tested. HOTCHIP

SERIAL 2K（256×8）EEPROM 第3 页 共 13 页 AT24C02(C) TABLE 1-2: AC CHARACTERISTICS AC CHARACTERISTICS Param No. Sym. Characteristic Min. Typ. Max Units Conditions 1 FCLK Clock frequency - - 400 kHz 1.8V ≤Vcc≤5.5V 2 THIGH Clock high time 600 - - ns 1.8V ≤Vcc≤5.5V 3 TLOW Clock low time 1300 - - ns 1.8V ≤ Vcc≤5.5V

4 TR SDA and SCL rise time

(Note 1) - - 300 ns 1.8V ≤Vcc≤5.5V( Note1)

5 TF SDA and SCL fall time - - 300 ns (Note1)

6 THD:STA Start condition hold time 600 - - ns 1.8V ≤Vcc≤5.5V

7 THD:STA Start condition setup

600 - - ns 1.8V ≤Vcc≤5.5V

8 THD:DAT Data input hold time 0 - - ns (Note 2)

9 TSU:DAT Data input setup time 100 - - ns 1.8V ≤Vcc≤ 5.5V

10 TSU:STO Stop condition setup

600 - - ns 1.8V ≤Vcc≤ 5.5V

11 TAA Output valid from clock

(Note2) - - 900 ns 1.8V ≤Vcc≤ 5.5V

12 TBUF Bus free time: Time the

new transmission can start 1300 - - ns 1.8V ≤Vcc≤5.5V

13 TOF Output fall time from VIH

20+0.1CB - 250 ns 1.8V ≤Vcc≤ 5.5V

14 TSP Input filter spike

(SDA and SCL pins) — - 50 ns (Notes 1 and 3)

15 TWC Write cycle time (byte or

page) — — 5 ms — 16 — Endurance 1M — — cycles 25℃,(Note 4) Note 1: Not 100% tested. CB=total capacitance of one bus line in pF. 2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. 3:The combined Tsp and VHYS specifications are due to new Schmitt Trigger inputs which provide improved noise spike suppression. This eliminates the need for a Tl specification for standard operation. HOTCHIP

SERIAL 2K（256×8）EEPROM 第5 页 共 13 页 AT24C02(C) Data Valid (D) The state of the data line represents valid data when, after a Start condition, the data line is stable for the duration of the high period of the clock signal. The data on the line must be changed during the low period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a Start condition and terminated with a Stop condition. The number of data bytes transferred between Start and Stop conditions is determined by the master device and is, theoretically, unlimited (although only the last sixteen will be stored when doing a write operation). When an over write does occur, it will replace data in a first-in first-out (FIFO) fashion. Acknowledge Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse which is associated with this Acknowledge bit. Note: The 24C02 does not generate any Acknowledge bits if an internal programming cycle is in progress. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable low during the high period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. During reads, a master must signal an end of data to the slave by not generating an Acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave (24C02) will leave the data line high to enable the master to generate the Stop condition FIGURE 7-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS Device Addressing A control byte is the first byte received following the Start condition from the master device. The control byte consists of a four-bit control code. For the 24C02, this is set as ‘1010’binary for read and write operations. The next three bites of the control byte are “don’t cares” for the 24C02. The last bit of the control byte defines the operation to be performed. When set to’1’, a read operation is selected. When set to ‘0’, a write operation is selected. Following the start condition, the 24C02 monitors the SDA bus, checking the device type identifier being transmitted and, upon a ‘1010’code, the slave device outputs an Acknowledge signal on the SDA line. Depending on the state of the select a read or write operation HOTCHIP

SERIAL 2K（256×8）EEPROM 第6 页 共 13 页 AT24C02(C) FIGURE 7-2: CONTROL BYTEALLOCATION WRITE OPERATION Byte Write Following the Start condition from the master , the device code(4 bits), the block address (3 bits, “don’t cares”) and the R/W bit which is a logic low, is placed onto the bus by the master transmitter. This indicates to the addressed slave receiver that a byte with a word address will follow once it has generated an Acknowledge bit during the ninth clock cycle. Therefore, the next byte transmitted by the master is the word address and will be written into the address Pointer of the 24C02. After receiving another Acknowledge signal from the 24C02, the master device will transmit the data word to be written into the addressed memory location. The 24C02 acknowledges again and the master generates a Stop condition. This initiates the internal write cycle and, during this time, the 24C02 will not generate Acknowledge Signals (Figure 8-1). Page Write The write-control byte, word address and the first data byte are transmitted to the 24C02 in the same way as in a byte write. However, instead of generating a Stop condition, the master transmits up to 8 data bytes to the 24C02, which are temporarily stored in the on-chip page buffer and will be written into memory once the master has transmitted a Stop condition. Upon receipt of each word, the four lower-order Address Pointer bits are internally incremented by ‘1’. The higher-order 7bits of the word address remain constant. If the master should transmit more than 8 words prior to generating the Stop condition, the address counter will roll over and the previously received data will be overwritten. As with the byte write operation, once the Stop condition is received an internal write cycle will begin (Figure 8-2). Note: Page write operations are limited to writing bytes within a single physical page regardless of the number of bytes actually being written. Physical page boundaries start at addresses that are integer multiples of the page buffer size (or ‘page size’) and end at addresses that are integer multiples of [page size -1]. If a Page Write command attempts to write across a physical page boundary, the result is that the data wraps around to the beginning of the current page (overwriting data previously stored there), instead of being written to the next page, as might be expected. It is therefore necessary for the application software to prevent page write operations that would attempt to cross a page boundary HOTCHIP

SERIAL 2K（256×8）EEPROM 第8 页 共 13 页 AT24C02(C) ACKNOWLEDGE PCLLING Since the device will not acknowledge during a write cycle ,this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). Once the Stop condition for a Write command has been issued from the master, the device initiates the internally- timed write cycle and ACK polling can then be initiated immediately. This involves the master sending a Start condition followed by the control byte for a Write command (R/W =0). If the device is still busy with the write cycle, no ACK will be returned. If the cycle is complete, the device will return the ACK and the master can then proceed with the next Read or Write command. See Figure 5-1 for a flow diagram of this operation. WRITE PROTECTION The WP pin allows the user to write-protect the entire array (00-FF) when the pin is tied to Vcc. If tied to Vss, the write protection is disabled READ OPERATION Read operations are initiated in the same way as write operations, with the exception that the R/W bit of the slave address is set to ‘1’. There are three basic types of read operations; current address read, random read and sequential read. Current Address Read The 24C02 contains an address counter that maintains the address of the last word accessed. Internally incremented by ‘1’. Therefore, if the previous access(either a read or write operation) was to address n, the next current address read operation would access data from address n+ 1, Upon receipt of the slave address。 bit set to ‘1’, the 24C02 issues an acknowledge and transmits the 8-bit data word. The master will not acknowledge the transfer, but does generate a Stop condition, and the 24C02 discontinues transmission (Figure 11-1). Random Read Random read operations allow the master to access any memory location in a random manner. To perform this type of read operation, the word address must first be set. This is accomplished by sending the word address to the 24C02 as part of a write operation. Once the word address is sent, the master generates a Start condition following the acknowledge. This terminates the write operation, but not before the internal Address Pointer is set. The master then issues the control byte again, but bit set to a ‘1’. The 24C02 will then issue an acknowledge and transmit the 8-bit data word. The master will not acknowledge the transfer, but does generate a Stop condition, and the discontinue transmission (figure 11-2). HOTCHIP

SERIAL 2K（256×8）EEPROM 第10 页 共13 页 AT24C02(C) PIN DESCRIPTIONS The descriptions of the pins are listed in Table 12-1. TABLE 12-1: PIN FUNCTION TABLE Name PDIP SOIC TSSOP DFN MSOP SOT23 Description A0 1 1 1 1 1 - Not Connected A1 2 2 2 2 2 - Not Connected A2 3 3 3 3 3 - Not Connected Vss 4 4 4 4 4 2 Ground SDA 5 5 5 5 5 3 Serial Address/Data I/O SCL 6 6 6 6 6 1 Serial Clock WP 7 7 7 7 7 5 Write-Protect Input Vcc 8 8 8 8 8 4 +1.8V to 5.5V Power Supply Serial Address/Data Input/Output(SDA) SDA is a bidirectional pin used to transfer addresses and data into and out of the device. Since it is an open-drain terminal, the SDA bus requires a pull-up resistor to Vcc ( typical 10 K Ω for 100KHz, 2KΩ for 400kHz). For normal data transfer, SDA is allowed to change only during SCL low, Changes during SCL high are reserved for indicating Start and Stop conditions. Serial Clock (SCL) The SCL input is used to synchronize the data transferto and from the device. Write-Protect(WP) The WP pin must be connected to either Vss or Vcc. If tied to Vss, normal memory operation is enabled(read/write the entire memory 00-FF).If tied to Vcc, write operations are inhibited. The entire memory will be write-protected. Read operations are not affected. This feature allows the user to use the 24C02 as aserial ROM when WP is enabled (tied to Vcc). A0,A1,A2 These A0,A1 and A2 pins are not used by the 24C02。 They may be left floating or tied to either Vss or Vcc HOTCHIP

SERIAL 2K（256×8）EEPROM 第11 页 共13 页 AT24C02(C) PACKAGE DESCRIPTION DIP-8 PACKAGE Units INCHES^ MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 8 8 Pitch P 0.100 2.54 Base to Seating Plane A1 0.015 0.38 Mold Draft Angle Top a 5 10 15 5 10 15 Mold Draft Angle Bottom ß 5 10 15 5 10 15 Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed.010” (0.254mm) per side. JEDEC Equivalent:MS-001Drawing No.C04-018 HOTCHIP

SERIAL 2K（256×8）EEPROM 第12 页 共13 页 AT24C02(C) SOP-8 PACKAGE Units INCHES^ MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 8 8 Pitch P 0.050 1.27 Foot Angle Ø 0 4 8 0 4 8 Mold Draft Angle Top a 0 12 15 0 12 15 Mold Draft Angle Bottom ß 0 12 15 0 12 15 Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010”(0.254mm) per side. JEDEC Equivalent: MS-012Drawing No. C04-057 HOTCHIP

SERIAL 2K（256×8）EEPROM 第13 页 共13 页 AT24C02(C) TSSOP8 PACKAGE Units INCHES^ MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 8 8 Pitch P 0.026 0.65 Overall Height A 0.043 1.10 Foot Angle Ø 0 4 8 0 4 8 Mold Draft Angle Top a 0 5 10 0 5 10 Mold Draft Angle Bottom ß 0 5 10 0 5 10 Controlling Parameter §Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed.005”(0.127mm) per side. JEDEC Equivalent:MO-153Drawing No. C04-086 HOTCHIP