AT24C02

AT24C01A_06 ATMEL | Alldatasheet

Document overview

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• PDF pages: 26

Technical content

Features

• Low-voltage and Standard-voltage Operation – 2.7 (V CC = 2.7V to 5.5V) – 1.8 (V CC = 1.8V to 5.5V)
• Internally Organized 128 x 8 (1K), 256 x 8 (2K), 512 x 8 (4K), 1024 x 8 (8K) or 2048 x 8 (16K)
• Two-wire Serial Interface
• Schmitt Trigger, Filtered Inputs for Noise Suppression
• Bidirectional Data Transfer Protocol
• 100 kHz (1.8V) and 400 kHz (2.7V, 5V) Compatibility
• Write Protect Pin for Hardware Data Protection
• 8-byte Page (1K, 2K), 16-byte Page (4K, 8K, 16K) Write Modes
• Partial Page Writes Allowed
• Self-timed Write Cycle (5 ms max)
• High-reliability – Endurance: 1 Million Write Cycles – Data Retention: 100 Years
• Automotive Devices Available
• 8-lead JEDEC PDIP , 8-lead JEDEC SOIC, 8-lead Ultra Thin Mini-MAP (MLP 2x3), 5-lead SOT23, 8-lead TSSOP and 8-ball dBGA2 Packages
• Die Sales: Wafer Form, Waffle Pack and Bumped Wafers

Description

The AT24C01A/02/04/08A/16A provides 1024/2048/4096/8192/16384 bits of serial electrically erasable and programmable read-only memory (EEPROM) organized as 128/256/512/1024/2048 words of 8 bits each. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. The AT24C01A/02/04/08A/16A is available in space-saving 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead Ultra Thin Mini-MAP (MLP 2x3) , 5-lead SOT23 (AT24C01A/AT24C02/AT24C04), 8-lead TSSOP , and 8-ball dBGA2 packages and is accessed via a Two-wire serial interface. In addition, the entire fa mily is available in Table 1. Pin Configuration

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Figure 1. Block Diagram

EEPROM device and negative edge clock data out of each device. discussed in detail under the Device Addressing section). and can be connected to ground. CC, the write protection feature is enabled and operates as shown in Table 2. Table 2. Write Protect the 1K requires a 7-bit data word address for random word addressing. the 2K requires an 8-bit data word address for random word addressing. the 4K requires a 9-bit data word address for random word addressing. each, the 8K requires a 10-bit data word address for random word addressing. each, the 16K requires an 11-bit data word address for random word addressing.

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Note: 1. This parameter is characterized and is not 100% tested. Note: 1. V IL min and VIH max are reference only and are not tested. Table 3. Pin Capacitance(1) Table 4. DC Characteristics

Note: 1. This parameter is characterized. Table 5. AC Characteristics

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0180Z–SEEPR–11/06 Device Operation CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an exter- nal device. Data on the SDA pin may change only during SCL low time periods (see Figure 4 on page 7). Data c hanges during SCL high periods will indicate a start or stop condition as defined below. START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (see Figure 5 on page 8). STOP CONDITION: A low-to-high transition of SDA wit h SCL high is a stop condition. After a read sequence, the stop command will place th e EEPROM in a standby power mode (see Figure 5 on page 8). ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a zero to acknowledge that it has received each word. This happens during the ninth clock cycle. STANDBY MODE: The AT24C01A/02/04/08A/16A features a low-power standby mode which is enabled: (a) upon power-up and (b) after the receipt of the STOP bit and the completion of any internal operations. MEMORY RESET: After an interruption in protocol, power loss or system reset, any 2- wire part can be reset by following these steps: 1. Clock up to 9 cycles. 2. Look for SDA high in each cycle while SCL is high. 3. Create a start condition.

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Figure 5. Start and Stop Definition Figure 6. Output Acknowledge

0180Z–SEEPR–11/06 Device Addressing The 1K, 2K, 4K, 8K and 16K EEPROM devices all require an 8-bit device address word following a start condition to enable the chip for a read or write operation (refer to Figure 7). The device address word consists of a mandatory one, zero sequence for the first four most significant bits as shown. This is common to all the EEPROM devices. The next 3 bits are the A2 , A1 and A0 device address bits for the 1K/2K EEPROM. These 3 bits must compare to their corresponding hard-wired input pins. The 4K EEPROM only uses the A2 and A1 device address bits with the third bit being a memory page address bit. The two device address bits must compare to their corre- sponding hard-wired input pins. The A0 pin is no connect. The 8K EEPROM only uses the A2 device address bit with the next 2 bits being for memory page addressing. The A2 bit must compare to its corresponding hard-wired input pin. The A1 and A0 pins are no connect. The 16K does not use any device address bi ts but instead the 3 bits are used for mem- ory page addressing. These page addressing bits on the 4K, 8K and 16K devices should be considered the most significant bits of the data word address which follows. The A0, A1 and A2 pins are no connect. The eighth bit of the device address is the r ead/write operation select bit. A read opera- tion is initiated if this bit is high and a write operation is initiated if this bit is low. Upon a compare of the device address, the EEPROM will output a zero. If a compare is not made, the chip will return to a standby state. Write Operations BYTE WRITE: A write operation requires an 8-bit data word address following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a zero and then cloc k in the first 8-bit data word. Following receipt of the 8-bit data word, the EE PROM will output a zero and the addressing device, such as a microcontroller, must te rminate the write sequence with a stop condi- tion. At this time the EEPROM enters an internally timed write cycle, t WR, to the nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write is complete (see Figure 8 on page 11). PAGE WRITE: The 1K/2K EEPROM is capable of an 8-byte page write, and the 4K, 8K and 16K devices are capable of 16-byte page writes. A page write is initiated the same as a byte write, but the microcontroller does not send a stop condition after the fi rst data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit up to seven (1K/2K) or fifteen (4K, 8K, 16K) more data words. The EEPROM will respond with a zero after each data word received. The microcontroller must terminate the page write sequence with a stop condition (see Figure 9 on page 11). The data word address lower three (1K/2K) or four (4K, 8K, 16K) bits are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. When the word address, internally generated, reaches the page bounda ry, the following byte is placed at the beginning of the same page. If more than eight (1K/2K) or sixteen (4K, 8K, 16K) data words are transmitted to the EEPROM, the da ta word address will “roll over” and previ- ous data will be overwritten.

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0180Z–SEEPR–11/06 ACKNOWLEDGE POLLING: Once the internally timed write cycle has started and the EEPROM inputs are disabled, acknowledge polling c an be initiated. This involves sending a start condition followed by the device address word. The read/write bit is representative of the operation desired. Only if t he internal write cycle has co mpleted will the EEPROM respond with a zero allowing the read or write sequence to continue. Read Operations Read operations are initiated the same way as write operations with th e exception that the read/write select bit in the device address word is set to one. There are three read operations: current address read, random address read and sequential read. CURRENT ADDRESS READ: The internal data word addr ess counter maintains the last address accessed during the last read or write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained. The address “roll over” during read is from the last byte of the last memory page to the first byte of the first page. The address “roll over” during write is from the last byte of the current page to the first byte of the same page. Once the device address with the read/write sele ct bit set to one is clocked in and acknowl- edged by the EEPROM, the curr ent address data word is se rially clocked out. The microcontroller does not respond with an input zero but does generate a following stop condi- tion (see Figure 10 on page 12). RANDOM READ: A random read requires a “dummy” byte write sequence to load in the data word address. Once the device address wo rd and data word address are clocked in and acknowledged by the EEPROM, the microcontr oller must generate another start condition. The microcontroller now initiates a current address read by sending a device address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller does not respond with a zero but does generate a fol- lowing stop condition (see Figure 11 on page 12). SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a ran- dom address read. After the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit is reached, the data word address will “roll over” and the sequential read will con- tinue. The sequential read operation is terminated when the microcontroller does not respond with a zero but does generate a following stop condition (see Figure 12 on page 12).

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Figure 10. Current Address Read Figure 11. Random Read Figure 12. Sequential Read

0180Z–SEEPR–11/06 5.5V range, please refer to performance values in the AC and DC characteristics table. 2. “U” designates Green Package + RoHS compliant. 3. “H” designates Green Package + RoHS compliant, with NiPdAu Lead Finish. 4. Available in waffle pack and wafer form; order as SL788 for inkless wafer form. Bumped die available upon request. Please contact Serial EEPROM Marketing. Ordering Code Package Operation Range AT24C01A-10PU-2.7(2) AT24C01A-10PU-1.8(2) AT24C01A-10SU-2.7(2) AT24C01A-10SU-1.8(2) AT24C01A-10TU-2.7(2) AT24C01A-10TU-1.8(2) AT24C01A-10TSU-1.8(2) AT24C01AU3-10UU-1.8(2) AT24C01AY1-10YU-1.8(2) (Not recommended for new design) AT24C01AY6-10YH-1.8(3) 8P3 8P3 8S1 8S1 8A2 8A2 5TS1 8U31 8Y1 8Y6 Lead-free/Halogen-free/ Industrial Temperature (–40°C to 85°C) AT24C01A-W1.8-11 (4) Die Sale Industrial Temperature (–40°C to 85°C) Package Type 8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 8A2 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP) 8Y1 8-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP) 8Y6 8-lead, 2.00 x 3.00 mm Body, 0.50 mm Pitch, Ultra Thin Mini-MAP, Dual No Lead Package (DFN), (MLP 2x3 mm) 5TS1 5-lead, 2.90 mm x 1.60 mm Body, Plastic Thin Shrink Small Outline Package (SOT23) 8U3-1 8-ball, die Ball Grid Away Package (dBGA2) Options –2.7 Low-voltage (2.7V to 5.5V) –1.8 Low-voltage (1.8V to 5.5V)

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0180Z–SEEPR–11/06 5.5V range, please refer to performance values in the AC and DC characteristics table. 2. “U” designates Green Package + RoHS compliant. 3. Available in waffle pack and wafer form; order as SL719 fo r wafer form. Bumped die available upon request. Please contact Serial EEPROM Marketing. Ordering Code Package Operation Range AT24C02-10PU-2.7(2) AT24C02-10PU-1.8(2) AT24C02N-10SU-2.7(2) AT24C02N-10SU-1.8(2) AT24C02-10TU-2.7(2) AT24C02-10TU-1.8(2) AT24C02Y1-10YU-1.8(2) AT24C02-10TSU-1.8(2) AT24C02U3-10UU-1.8(2) 8P3 8P3 8S1 8S1 8A2 8A2 8Y1 5TS1 8U3-1 Lead-free/Halogen-free/ Industrial Temperature (–40°C to 85°C) AT24C02-W2.7-11(3) Die Sale Industrial Temperature (–40°C to 85°C) Package Type 8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 8A2 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP) 8Y1 8-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP) 5TS1 5-lead, 2.90 mm x 1.60 mm Body, Plastic Thin Shrink Small Outline Package (SOT23) 8U3-1 8-ball, die Ball Grid Away Package (dBGA2) Options –2.7 Low-voltage (2.7V to 5.5V) –1.8 Low-voltage (1.8V to 5.5V)

0180Z–SEEPR–11/06 2. “U” designates Green Package + RoHS compliant. 3. “H” designates Green Package + RoHS compliant, with NiPdAu Lead Finish. 4. Available in waffle pack and wafer form; order as SL788 for inkless wafer form. Bumped die available upon request. Please contact Serial EEPROM Marketing. Ordering Code Package Operation Range AT24C04-10PU-2.7(2) AT24C04-10PU-1.8(2) AT24C04N-10SU-2.7(2) AT24C04N-10SU-1.8(2) AT24C04-10TU-2.7(2) AT24C04-10TU-1.8(2) AT24C04Y1-10YU-1.8(2) (Not recommended for new design) AT24C04Y6-10YH-1.8(3) AT24C04-10TSU-1.8(2) AT24C04U3-10UU-1.8(2) 8P3 8P3 8S1 8S1 8A2 8A2 8Y1 8Y6 5TS1 8U3-1 Lead-free/Halogen-free/ Industrial Temperature (–40°C to 85°C) AT24C04-W1.8-11 (4) Die Sale Industrial Temperature (–40°C to 85°C) Package Type 8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 8A2 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP) 8Y1 8-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP) 8Y6 8-lead, 2.00 x 3.00 mm Body, 0.50 mm Pitch, Ultra Thin Mini-MAP, Dual No Lead Package (DFN), (MLP 2x3 mm) 5TS1 5-lead, 2.90 mm x 1.60 mm Body, Plastic Thin Shrink Small Outline Package (SOT23) 8U3-1 8-ball, die Ball Grid Away Package (dBGA2) Options –2.7 Low-voltage (2.7V to 5.5V) –1.8 Low-voltage (1.8V to 5.5V)

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0180Z–SEEPR–11/06 2. “U” designates Green Package + RoHS compliant. 3. “H” designates Green Package + RoHS compliant, with NiPdAu Lead Finish. 4. Available in waffle pack and wafer form; order as SL788 for inkless wafer form. Bumped die available upon request. Please contact Serial EEPROM Marketing. Ordering Code Package Operation Range AT24C08A-10PU-2.7(2) AT24C08A-10PU-1.8(2) AT24C08AN-10SU-2.7(2) AT24C08AN-10SU-1.8(2) AT24C08A-10TU-2.7(2) AT24C08A-10TU-1.8(2) AT24C08AY1-10YU-1.8(2) (Not recommended for new design) AT24C08AY6-10YH-1.8(3) AT24C08AU2-10UU-1.8(2 8P3 8P3 8S1 8S1 8A2 8A2 8Y1 8Y6 8U2-1 Lead-free/Halogen-free/ Industrial Temperature (−40°C to 85°C) AT24C08A-W1.8-11 (4) Die Sale Industrial Temperature (–40°C to 85°C) Package Type 8P3 8-pin, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 8A2 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP) 8Y1 8-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP) 8Y6 8-lead, 2.00 x 3.00 mm Body, 0.50 mm Pitch, Ultra Thin Mini-MAP, Dual No Lead Package (DFN), (MLP 2x3 mm) 8U2-1 8-ball, die Ball Grid Array Package (dBGA2) Options −2.7 Low Voltage (2.7V to 5.5V) −1.8 Low Voltage (1.8V to 5.5V)

0180Z–SEEPR–11/06 5.5V range, please refer to performance values in the AC and DC characteristics table. 2. “U” designates Green Package + RoHS compliant. 3. “H” designates Green Package + RoHS compliant, with NiPdAu Lead Finish. 4. Available in waffle pack and wafer form; order as SL788 for inkless wafer form. Bumped die available upon request. Please contact Serial EEPROM Marketing. Ordering Code Package Operation Range AT24C16A-10PU-2.7(2) AT24C16A-10PU-1.8(2) AT24C16AN-10SU-2.7(2) AT24C16AN-10SU-1.8(2) AT24C16A-10TU-2.7(2) AT24C16A-10TU-1.8(2) AT24C16AY1-10YU-1.8(2) (Not recommended for new design) AT24C16AY6-10YH-1.8(3) AT24C16AU2-10UU-1.8(2) 8P3 8P3 8S1 8S1 8A2 8A2 8Y1 8Y6 8U2-1 Lead-free/Halogen-free/ Industrial Temperature (−40°C to 85°C) AT24C16A-W1.8-11 (3) Die Sale Industrial Temperature (−40°C to 85°C) Package Type 8P3 8-pin, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 8A2 8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP) 8Y1 8-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP) 8Y6 8-lead, 2.00 x 3.00 mm Body, 0.50 mm Pitch, Ultra Thin Mini-MAP, Dual No Lead Package (DFN), (MLP 2x3 mm) 8U2-1 8-ball, die Ball Grid Array Package (dBGA2) Options −2.7 Low Voltage (2.7V to 5.5V) −1.8 Low Voltage (1.8V to 5.5V)

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0180Z–SEEPR–11/06 Packaging Information 8P3 – PDIP

2325 Orchard Parkway

San Jose, CA 95131 TITLE DRAWING NO. R REV. 8P3, 8-lead, 0.300" Wide Body, Plastic Dual In-line Package (PDIP) 01/09/02 8P3 B Notes: 1. Thi s drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA, for additional information. 2. Dimen sions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3. 3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch. 4. E and eA measured with the leads constrained to be perpendicular to datum. 5. Pointed or ro unded lead tips are preferred to ease insertion. COMMON DIMENSIONS (Unit of Measure = inches) SYMBOL MIN NOM MAX NOTE D E e Lb2 b A2 A N eA c

4 PLCS

A – – 0.210 2 A2 0.115 0.1 30 0.195 b 0.014 0.01 8 0.022 5 b2 0.045 0.060 0.070 6 b3 0.0 30 0.0 39 0.045 6 c 0.00 8 0.010 0.014 D 0. 355 0. 365 0.400 3 D1 0.005 – – 3 E 0. 300 0. 310 0. 325 4 E1 0.240 0.250 0.2 80 3 e 0.100 B SC eA 0. 300 BSC 4 L 0.115 0.1 30 0.150 2 Top View Side View End View

0180Z–SEEPR–11/06 8S1 – JEDEC SOIC 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TITLE DRAWING NO. R REV. Note: 10/7/03 8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC) 8S1 B COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A1 0.10 – 0.25 These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. A 1.35 – 1.75 b 0.31 – 0.51 C 0.17 – 0.25 D 4.80 – 5.00 E1 3.81 – 3.99 E 5.79 – 6.20 e 1.27 BSC L 0.40 – 1.27 ∅ 0˚ – 8˚ Top View End View Side View e B D A N E C L

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0180Z–SEEPR–11/06 8A2 – TSSOP San Jose, CA 95131 TITLE DRAWING NO. R REV. 5/30/02 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE D 2.90 3.00 3.10 2, 5 E 6.40 BSC E1 4.30 4.40 4.50 3, 5 A – – 1.20 A2 0.80 1.00 1.05 b 0.19 – 0.30 4 e 0.65 BSC L 0.45 0.60 0.75 L1 1.00 REF 8A2, 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP) Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances, datums, etc. 2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed 0.15 mm (0.006 in) per side. 3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm (0.010 in) per side. 4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between protrusion and adjacent lead is 0.07 mm. 5. Dimension D and E1 to be determined at Datum Plane H. 8A2 B Side View End ViewTop View A L D 123 N b Pin 1 indicator this corner E e

0180Z–SEEPR–11/06 8Y1 – MAP A – – 0.90 A1 0.00 – 0.05 D 4.70 4.90 5.10 E 2. 80 3.00 3.20 D1 0. 85 1.00 1.15 E1 0. 85 1.00 1.15 b 0.25 0. 30 0. 35 e 0.65 TYP L 0.50 0.60 0.70 PIN 1 INDEX AREA D E A A1 b 8 7 6 e L PIN 1 INDEX AREA 1 2 3 4 A Top View End View Bottom View Side View San Jose, CA 95131 TITLE DRAWING NO. R REV. 8Y1, 8-lead (4.90 x 3.00 mm Body) MSOP Array Package (MAP) Y1 C8Y1 2/28/03 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE

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0180Z–SEEPR–11/06 8Y6 − Mini-MAP (MLP 2x3 mm) San Jose, CA 95131 TITLE DRAWING NO. R REV. 8Y6, 8-lead 2.0 x 3.0 mm Body, 0.50 mm Pitch, Utlra Thin Mini-Map, Dual No Lead Package (DFN) ,(MLP 2x3) C8Y6 8/26/05 Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-229, for proper dimensions, tolerances, datums, etc. 2. Dimension b applies to metallized terminal and is measured between 0.15 mm and 0.30 mm from the terminal tip. If the terminal has the optional radius on the other end of the terminal, the dimension should not be measured in that radius area. COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE D 2.00 BSC E 3.00 BSC D2 1.40 1.50 1.60 E2 - - 1.40 A - - 0.60 A1 0.0 0.02 0.05 A2 - - 0.55 A3 0.20 REF L 0.20 0.30 0.40 e 0.50 BSC b 0.20 0.25 0.30 2 b (8X) Pin 1 ID Pin 1 Index Area D E A L (8X) e (6X) 1.50 REF.

0180Z–SEEPR–11/06 5TS1 – SOT23 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TITLE DRAWING NO. R REV. PO5TS1 A 6/25/03 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE 5TS1, 5-lead, 1.60 mm Body, Plastic Thin Shrink Small Outline Package (SHRINK SOT) A – – 1.10 A1 0.00 – 0.10 A2 0.70 0.90 1.00 c 0.08 – 0.20 4 D 2.90 BSC 2, 3 E 2.80 BSC 2, 3 E1 1.60 BSC 2, 3 L1 0.60 REF e 0.95 BSC e1 1.90 BSC b 0.30 – 0.50 4, 5 NOTES: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-193, Variation AB, for additional information. 2. Dimension D does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per end. Dimension E1 does not include interlead flash or protrusion. Interlead flash or protrusion shall not exceed 0.15 mm per side. 3. The package top may be smaller than the package bottom. Dimensions D and E1 are determined at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs, and interlead flash, but including any mismatch between the top and bottom of the plastic body. 4. These dimensions apply to the flat section of the lead between 0.08 mm and 0.15 mm from the lead tip. 5. Dimension "b" does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the "b" dimension at maximum material condition. The Dambar cannot be located on the lower radius of the foot. Minimum space between protrusion and an adjacent lead shall not be less than 0.07 mm. 5 4 L C End View C AA2 b e Seating Plane D Side View Top View E

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0180Z–SEEPR–11/06 8U2 – dBGA2 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TITLE DRAWING NO. R REV. 8U2, 8-ball 0.75 pitch, Die Ball Grid Array 02/04/02 8U2 A COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE D 5.10 D1 1.43 TYP E 3.25 E1 1.25 TYP e 0.75 TYP d 0.75 TYP A 0.90 REF A1 0.49 0.52 0.55 A2 0.35 0.38 0.41 Øb 0.47 0.50 0.53 d e D E A -Z- ZM80.0 YXZM51.0 Øb Pin 1 Mark this corner Notes: 1. These drawings are for general information only. No JEDEC Drawing to refer to for additional information. 2. Dimension is measured at the maximum solder ball diameter, parallel to primary datum Z. Top View Side View Bottom View

0180Z–SEEPR–11/06 8U3-1 – dBGA2 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TITLE DRAWING NO. R REV. PO8U3-1 A 6/24/03 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE 8U3-1, 8-ball, 1.50 x 2.00 mm Body, 0.50 mm pitch, Small Die Ball Grid Array Package (dBGA2) A 0.71 0. 81 0.91 A1 0.10 0.15 0.20 A2 0.40 0.45 0.50 b 0.20 0.25 0. 30 D 1.50 B SC E 2.00 B SC e 0.50 B SC e1 0.25 REF d 1.00 B SC d1 0.25 REF 1. Dimension “b” is measured at the maximum solder ball diameter. This drawing is for general information only. Bottom View

8 SOLDER BALLS

E Top View PIN 1 BALL PAD CORNER A Side View PIN 1 BALL PAD CORNER e 678 d (e1) (d1)

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