AT24C01BU3-UU-T

AT24C01B_08 ATMEL | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 25

Technical content

Features

• Low-voltage and Standard-voltage Operation – 1.8 (V CC = 1.8V to 5.5V)  Internally Organized 128 x 8 (1K)  Two-wire Serial Interface  Schmitt Trigger, Filtered Inputs for Noise Suppression  Bidirectional Data Transfer Protocol  1 MHz (5V), 400 kHz (1.8V, 2.5V, 2.7V) Compatibility  Write Protect Pin for Hardware Data Protection  8-byte Page (1K) Write Modes  Partial Page Writes Allowed  Self-timed Write Cycle (5 ms max)  High-reliability – Endurance: 1 Million Write Cycles – Data Retention: 100 Years  8-lead PDIP, 8-lead JEDEC SOIC, 8-lead Ultra Thin Mini-MAP (MLP 2x3), 5-lead SOT23, 8-lead TSSOP and 8-ball dBGA2 Packages  Lead-free/Halogen-free  Die Sales: Wafer Form and Tape and Reel

Description

The AT24C01B provides 1024 bits of seri al electrically erasable and programmable read-only memory (EEPROM) org anized as 128 words of 8 bits each. The device is optimized for use in m any industri al and commerci al applications where low-power and low-voltage operation are essential. The AT24C01B is available in space-saving 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead Ultr a Thin Mini-MAP (MLP 2x 3), 5-le ad SOT23, 8-lead TSSOP, and 8-ball dBGA2 packages and is accessed via a Two-wire Table 0-1. Pin Configuration Pin Name Function A0 - A2 Address Inputs SDA Serial Data SCL Serial Clock Input WP Write Protect GND Ground VCC Power Supply Two-wire Serial EEPROM 1K (128 x 8) AT24C01B 5156E–SEEPR–10/08

5156E–SEEPR–10/08 AT24C01B Figure 0-1. Block Diagram Absolute Maximum Ratings Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Voltage on Any Pin START STOP LOGIC VCC GND WP SCL SDA SERIAL CONTROL LOGIC EN H.V. PUMP/TIMING EEPROM DATA RECOVERY SERIAL MUX X DEC DOUT/ACK LOGIC COMP LOAD INC DATA WORD ADDR/COUNTER Y DEC R/W DOUT DIN LOAD DEVICE ADDRESS COMPARATOR

5156E–SEEPR–10/08 AT24C01B 1. Pin Description SERIAL CLOCK (SCL): The SCL input is used to positive edge clock d ata into each EEPROM device and negative edge clock data out of each device. SERIAL DATA (SDA): The SDA pin is bidirection al for seri al data transfer. This pin is open- drain driven and may be wire-ORed with any num ber of other open-dr ain or open-collector devices. DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1 and A0 pins are device address inputs that are hard wired for the AT24C01B. As many as eight 1K devices may be addressed on a sin- gle bus system (device addressing is discussed in detail under the Device Addressing section). WRITE PROTECT (WP): The AT24C01B h as a write protect pin th at provides h ardware data protection. The write protect pin allows normal read/write operations when connected to ground (GND). When the write protect pin is connected to V CC, the write protection fe ature is en abled and operates as shown in Table 1-1. Table 1-1. Write Protect 2. Memory Organization AT24C01B, 1K SERIAL EEPROM: Internally organized with 16 p ages of 8 bytes each, the 1K requires an 7-bit data word address for random word addressing. (See Figure 8-2 on page 10) WP Pin Status Part of the Array Protected 24C01B At VCC Full (1K) Array At GND Norm al Read/Write Operations

5156E–SEEPR–10/08 AT24C01B Note: 1. This p arameter is characterized and is not 100% tested. Note: 1. V IL min and VIH max are reference only and are not tested. Table 2-1. Pin Capacitance(1) Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +1.8V Symbol Test Condition Max Units Conditions CI/O Input/Output Capacitance (SDA) 8 pF V I/O = 0V CIN Input Capacitance (A0, A1, A2, SCL) 6 pF V IN = 0V Table 2-2. DC Characteristics Applicable over recommended oper ating range from: TAI = –40°C to +85°C, VCC = +1.8V to +5.5V, V CC =+ 1 .8V to +5.5V (unless otherwise noted) Symbol Parameter Test Condition Min Typ Max Units VCC1 Supply Voltage 1. 8 5.5 V VCC2 Supply Voltage 2.5 5.5 V VCC3 Supply Voltage 2.7 5.5 V VCC4 Supply Voltage 4.5 5.5 V ICC Supply Current VCC = 5.0V READ at 100 kHz 0.4 1.0 mA ICC Supply Current VCC = 5.0V WRITE at 100 kHz 2.0 3.0 mA ISB1 Standby Current VCC = 1.8VV IN = VCC or VSS 0.6 3.0 µA ISB2 Standby Current VCC = 2.5V V IN = VCC or VSS 1.4 4.0 µA ISB3 Standby Current VCC = 2.7V V IN = VCC or VSS 1.6 4.0 µA ISB4 Standby Current VCC = 5.0V V IN = VCC or VSS 8.0 1 8.0 µA ILI Input Leakage Current V IN = VCC or VSS 0.10 3.0 µA ILO Output Leakage Current V OUT = VCC or VSS 0.05 3.0 µA VIL Input Low Level(1) –0.6 V CC x 0.3 V VIH Input High Level(1) VCC x 0.7 V CC + 0.5 V VOL2 Output Low Level VCC = 3.0V I OL = 2.1 mA 0.4 V VOL1 Output Low Level VCC = 1.8VI OL = 0.15 mA 0.2 V

5156E–SEEPR–10/08 AT24C01B Note: 1. This p arameter is ensured by characterization only. Table 2-3. AC Characteristics Applicable over recommended oper ating range from T AI = –40°C to +85°C, VCC = +1.8V to +5.5V, CL = 1 TTL G ate and 100 pF (unless otherwise noted) Symbol Parameter UnitsMin Max Min Max fSCL Clock Frequency, SCL 400 1000 kHz tLOW Clock Pulse Width Low 1.2 0.4 µs tHIGH Clock Pulse Width High 0.6 0.4 µs tI Noise Suppression Time 50 40 ns tAA Clock Low to Data Out Valid 0.1 0.9 0.05 0.55 µs tBUF Time the bus must be free before a new transmission can start 1.2 0.5 µs tHD.STA Start Hold Time 0.6 0.25 µs tSU.STA Start Setup Time 0.6 0.25 µs tHD.DAT Data In Hold Time 0 0 µs tSU.DAT Data In Setup Time 100 100 ns tR Inputs Rise Time(1) 0.3 0.3 µs tF Inputs Fall Time(1) 300 100 ns tSU.STO Stop Setup Time 0.6 .25 µs tDH Data Out Hold Time 50 50 ns tWR Write Cycle Time 5 5 ms Endurance(1) 5.0V, 25°C, Byte Mode 1 Million Write Cycles

5156E–SEEPR–10/08 AT24C01B 3. Device Operation CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (see Figure 5-2 on page 8). Data changes during SCL high periods will indicate a start or stop condition as defined below. START CONDITION: A high-to-low tr ansition of SDA with SCL high is a start condition which must precede any other command (see Figure 5-3 on page 8). STOP CONDITION: A low-to-high tr ansition of SDA with SCL high is a stop condition. After a read sequence, the stop comm and will place the EEPROM in a standby power mode (see Fig- ure 5-3 on page 8). ACKNOWLEDGE: All addresses and d ata words are seri ally tr ansmitted to and from the EEPROM in 8-bit words. The EEPROM sends a zero to acknowledge that it has received each word. This happens during the ninth clock cycle. STANDBY MODE: The AT24C01B fe atures a low-power st andby mode which is en abled: (a) upon power-up and (b) after the receipt of the STOP bit and the completion of any intern al operations. 2-WIRE SOFTWARE RESET: After an interruption in protocol, power loss or system reset, any 2-wire part can be protocol reset by following these steps: ( a) Create a start bit condition, ( b) Clock 9 cycles, (c) Create another start bit followed by a stop bit condition as shown below. The device is ready for next communication after above steps have been completed. Start bit Stop bitStart bitDummy Clock Cycles SCL SDA 123 89

5156E–SEEPR–10/08 AT24C01B 6. Device Addressing The 1K EEPROM device requires an 8-bit device address word following a start condition to enable the chip for a read or write operation (refer to Figure 8-1). The device address word consists of a mandatory one, zero sequence for the first four most sig- nificant bits as shown. This is common to all the EEPROM devices. The next 3 bits are the A2, A1 and A0 device address bits for the 1K EEPROM. These 3 bits must compare to their corresponding hard-wired input pins. The eighth bit of the device address is the read/write operation select bit. A read operation is ini- tiated if this bit is high and a write operation is initiated if this bit is low. Upon a compare of the device address, the EEPROM will output a zero. If a compare is not made, the chip will return to a standby state. 7. Write Operations BYTE WRITE: A write oper ation requires an 8-bit d ata word address following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a zero and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a zero and the addressing device, such as a microcontroller, must termin ate the write sequence with a stop condition. At th is time the EEPROM enters an internally timed write cycle, t WR, to the nonvol atile memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write is complete (see Figure 8-2 on page 10). PAGE WRITE: The 1K EEPROM is capable of an 8-byte page write. A page write is initi ated the same as a byte write, but the microcontroller does not send a stop condition after the first d ata word is clocked in. Inste ad, after the EEPROM acknowledges receipt of the first d ata word, the microcontroller c an transmit up to seven d ata words. The EEPROM will respond with a zero after each data word received. The microcontroller must ter- minate the page write sequence with a stop condition (see Figure 8-3 on page 11). The data word address lower three bits are internally incremented following the receipt of e ach data word. The higher d ata word address bits are not incremented, ret aining the memory p age row location. When the word address, internally generated, reaches the page boundary, the fol- lowing byte is pl aced at the beginning of the s ame page. If more th an eight d ata words are transmitted to the EEPROM, the d ata word address will “roll over” and previous d ata will be overwritten. ACKNOWLEDGE POLLING: Once the intern ally timed write cycle h as st arted and the EEPROM inputs are disabled, acknowledge polling c an be initi ated. This involves sending a start condition followed by the device address word. The re ad/write bit is represent ative of the operation desired. Only if the intern al write cycle has completed will the EEPROM respond with a zero allowing the read or write sequence to continue.

5156E–SEEPR–10/08 AT24C01B Figure 8-6. Sequential Read

5156E–SEEPR–10/08 AT24C01B Notes: 1. “-B” denotes bulk. 2. “-T” denotes t ape and reel. SOIC = 4K per reel. TSSOP , Ultra Thin Mini MAP , SOT 23 and dBGA2 = 5K per reel. 3.A v ailable in tape and reel and wafer form; order as SL788 for inkless wafer form. Please contact Serial Interface Marketing. Ordering Code Package Voltage Range Operation Range AT24C01B-PU (Bulk form only) 8P3 1.8V to 5.5V Lead-free/Halogen-free/ Industrial Temperature (–40°C to 85°C) AT24C01BN-SH-B(1) (NiPdAu Lead Finish) 8S11 . 8V to 5.5V AT24C01BN-SH-T(2) (NiPdAu Lead Finish) 8S11 . 8V to 5.5V AT24C01B-TH-B(1) (NiPdAu Lead Finish) 8A2 1. 8V to 5.5V AT24C01B-TH-T(2) (NiPdAu Lead Finish) 8A2 1. 8V to 5.5V AT24C01BY6-YH-T(2) (NiPdAu Lead Finish) 8Y6 1. 8V to 5.5V AT24C01B-TSU-T(2) 5TS11 . 8V to 5.5V AT24C01BU3-UU-T(2) 8U3-1 1. 8V to 5.5V AT24C01B-W-11(3) Die Sale 1. 8V to 5.5V Industri al Temperature (–40°C to 85°C) Package Type 8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 8A2 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP) 8Y6 8-lead, 2.0 mm x 3.00 mm Body, 0.50 mm Pitch, Ultra Thin Mini-MAP , Dual No Lead Package (DFN), (MLP 2x3 mm) 5TS1 5-lead, 2.90 mm x 1.60 mm Body, Plastic Thin Shrink Small Outline Package (SOT23) 8U3-1 8-ball, die Ball Grid Array Package (dBGA2)

5156E–SEEPR–10/08 AT24C01B 9. Part Marking Scheme 8-PDIP Seal Year TOP MARK | Seal Week | | | A T M L U Y W W 0 1 B 1 * Lot Number Pin 1 Indicator (Dot) U = Material Set Y = Seal Year WW = Seal Week 01B = Device V = Voltage Indicator *Lot Number to Use ALL Characters in Marking BOTTOM MARK No Bottom Mark

5156E–SEEPR–10/08 AT24C01B 8-SOIC Seal Year TOP MARK | Seal Week | | | A T M L H Y W W 0 1 B 1 * Lot Number Pin 1 Indicator (Dot) H = Material Set Y = Seal Year WW = Seal Week 01B = Device 1 = Voltage Indicator *Lot Number to Use ALL Characters in Marking BOTTOM MARK No Bottom Mark 8-TSSOP TOP MARK Pin 1 Indicator (Dot) * H Y W W 0 1 B 1 H = Material Set Y = Seal Year WW = Seal Week 01B = Device 1 = Voltage Indicator

5156E–SEEPR–10/08 AT24C01B BOTTOM MARK X X A A A A A A A <- Pin 1 Indicator Lot Number XX = Country of Origin AAAAAA = Lot Number SOT23 TOP MARK Pin 1 Indicator (Dot) 1B = Device 1 = Voltage Indicator W = Write Protect Feature U = Material Set BOTTOM MARK Y M T C Y = One Digit Year Code M = Seal Month TC = Trace Code

5156E–SEEPR–10/08 AT24C01B ULTRA THIN MINI MAP TOP MARK |---|---|---| 0 1 B |---|---|---| H 1 |---|---|---| Y T C |---|---|---| Pin 1 Indicator (Dot) 01B = Device H = Material Set 1 = Voltage Indicator Y = Year of Assembly TC = Trace Code dBGA2 TOP MARK |<-- Pin 1 This Corner 01B = Device U = Material Set Y = One Digit Year Code M = Seal Month TC = Trace Code

5156E–SEEPR–10/08 AT24C01B 10. Packaging Information 10.1 8P3 – PDIP

2325 Orchard Parkway

San Jose, CA 95131 TITLE DRAWING NO. R REV. 8P3, 8-lead, 0.300" Wide Body, Plastic Dual In-line Package (PDIP) 01/09/02 8P3 B Notes: 1. Thi s drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA, for additional information. 2. Dimen sions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3. 3. D, D1 and E1 dimen sions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch. 4. E and eA mea sured with the leads constrained to be perpendicular to datum. 5. Pointed or ro unded lead tips are preferred to ease insertion. COMMON DIMENSIONS (Unit of Measure = inches) SYMBOL MIN NOM MAX NOTE D E e Lb2 b A2 A N eA c

4 PLCS

A – – 0.210 2 A2 0.115 0.130 0.195 b 0.014 0.018 0.022 5 b2 0.045 0.060 0.070 6 b3 0.030 0.039 0.045 6 c 0.008 0.010 0.014 D 0.355 0.365 0.400 3 D1 0.005 – – 3 E 0.300 0.310 0.325 4 E1 0.240 0.250 0.280 3 e 0.100 BSC eA 0.300 BSC 4 L 0.115 0.130 0.150 2 Top View Side View End View

5156E–SEEPR–10/08 AT24C01B 10.2 8S1 – JEDEC SOIC 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TITLE DRAWING NO. R REV. Note: 10/7/03 8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC) 8S1 B COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A1 0.10 – 0.25 These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. A 1.35 – 1.75 b 0.31 – 0.51 C 0.17 – 0.25 D 4.80 – 5.00 E1 3.81 – 3.99 E 5.79 – 6.20 e 1.27 BSC L 0.40 – 1.27 ∅ 0˚ – 8˚ Top View End View Side View e B D A N E C L

5156E–SEEPR–10/08 AT24C01B 10.3 8A2 – TSSOP San Jose, CA 95131 TITLE DRAWING NO. R REV. 5/30/02 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE D 2.90 3.00 3.10 2, 5 E 6.40 B SC E1 4. 30 4.40 4.50 3, 5 A – – 1.20 A2 0. 80 1.00 1.05 b 0.19 – 0. 304 e 0.65 B SC L 0.45 0.60 0.75 L1 1.00 REF 8A2, 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP) Notes: 1. This dr awing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances, datums, etc. 2. Dimension D does not include mold Fl ash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed 0.15 mm (0.006 in) per side. 3. Dimension E1 does not include inter-le ad Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm (0.010 in) per side. 4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between protrusion and adjacent lead is 0.07 mm. 5. Dimension D and E1 to be determined at Datum Plane H. 8A2 B Side View End ViewTop View A L D 123 N b Pin 1 indicator this corner E e

5156E–SEEPR–10/08 AT24C01B 11. 8Y6 - Mini Map San Jose, CA 95131 TITLE DRAWING NO. R REV. 8Y6, 8-lead 2.0 x 3.0 mm Body, 0.50 mm Pitch, Utlra Thin Mini-Map, Dual No Lead Package (DFN) ,(MLP 2x3) D8Y6 10/16/07 Notes: 1. Thi s drawing is for general information only. Refer to JEDEC Drawing MO-229, for proper dimensions, tolerance s, datums, etc. 2. Dimen sion b applies to metallized terminal and is measured between 0.15 mm and 0.30 mm from the terminal tip. If the terminal ha s the optional radius on the other end of the terminal, the dimension should not be measured in that radius area. 3. Soldering the large thermal pad is optional, but not recommended. No electrical connection is accomplished to the device through this pad, so if soldered it should be tied to ground COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE D 2.00 BSC E 3.00 BSC D2 1.40 1.50 1.60 E2 - - 1.40 A - - 0.60 A1 0.0 0.02 0.05 A2 - - 0.55 A3 0.20 REF L 0.20 0.30 0.40 e 0.50 BSC b 0.20 0.25 0.30 2 A2A2 b (8X)(8X) Pin 1 IDPin 1 ID Pin 1Pin 1 IndexIndex AreaArea A1A1 A3A3 D E A L (8X)L (8X) e (6X)e (6X) 1.50 REF .1.50 REF. D2D2 E2E2

5156E–SEEPR–10/08 AT24C01B 12. 5TS1 – SOT23 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TITLE DRAWING NO. R REV. PO5TS1 A 6/25/03 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE 5TS1, 5-lead, 1.60 mm Body, Plastic Thin Shrink Small Outline Package (SHRINK SOT) A – – 1.10 A1 0.00 – 0.10 A2 0.70 0.90 1.00 c 0.08 – 0.20 4 D 2.90 BSC 2, 3 E 2.80 BSC 2, 3 E1 1.60 BSC 2, 3 L1 0.60 REF e 0.95 BSC e1 1.90 BSC b 0.30 – 0.50 4, 5 NOTES: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-193, Variation AB, for additional information. 2. Dimension D does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per end. Dimension E1 does not include interlead flash or protrusion. Interlead flash or protrusion shall not exceed 0.15 mm per side. 3. The package top may be smaller than the package bottom. Dimensions D and E1 are determined at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs, and interlead flash, but including any mismatch between the top and bottom of the plastic body. 4. These dimensions apply to the flat section of the lead between 0.08 mm and 0.15 mm from the lead tip. 5. Dimension "b" does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the "b" dimension at maximum material condition. The Dambar cannot be located on the lower radius of the foot. Minimum space between protrusion and an adjacent lead shall not be less than 0.07 mm. 5 4 L C End View C AA2 b e Seating Plane D Side View Top View E

5156E–SEEPR–10/08 AT24C01B 13. 8U3-1 – dBGA2 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TITLE DRAWING NO. R REV. PO8U3-1 A 6/24/03 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE 8U3-1, 8-ball, 1.50 x 2.00 mm Body, 0.50 mm pitch, Small Die Ball Grid Array Package (dBGA2) A 0.71 0.81 0.91 A1 0.10 0.15 0.20 A2 0.40 0.45 0.50 b 0.20 0.25 0.30 D 1.50 BSC E 2.00 BSC e 0.50 BSC e1 0.25 REF d 1.00 BSC d1 0.25 REF 1. Dimension “b” is measured at the maximum solder ball diameter. This drawing is for general information only. Bottom View

8 SOLDER BALLS

E Top View PIN 1 BALL PAD CORNER A Side View PIN 1 BALL PAD CORNER e 678 d (e1) (d1)

5156E–SEEPR–10/08 AT24C01B

Revision History

Doc. Rev. Date Comments 5156E 10/200 8 Modified Ordering Information 5156D 8/2007 Added P art Marking Scheme 5156C 4/2007 Removed NC and GND from Pin Configuration; Removed Preliminary from page 1 and all headers/footers; Added 2-wire Software Reset; Removed LSB and MSB from figures; Removed waffle pack from die sale order information 5156B 5/2006 Ordering information changed; added -B denotes bulk; added bulk ordering codes; added tape and reel ordering codes 5156A 4/2006 Initi al document release

5156E–SEEPR–10/08 Headquarters International Atmel Corporation San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Asia Room 1219 Chinachem Golden Plaza

77 Mody Road Tsimshatsui

Tel: (852) 2721-9778 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309

78054 Saint-Quentin-en-

9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Product Contact Web Site www.atmel.com Technical Support s_eeprom@atmel.com Sales Contact www.atmel.com/contacts Literature Requests www.atmel.com/literature Disclaimer: The inform ation in this document is provided in connection wi th Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectu al property right is gr anted by this document or in connection with the s ale of Atmel products. EXCEPT AS SET FORTH IN ATMEL ’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL ’S WEB SITE, ATMEL ASSUMES NO LI ABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTOR Y WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICU LAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR I NCIDEN- TAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATME L HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel m akes no represent ations or w arranties with respect to the accuracy or completeness of the contents of this document and reserves the right to m ake changes to specific ations and product descriptions at any time without notice. Atmel does not m ake any commitment to upd ate the inform ation cont ained herein. Unless specific ally provided otherwise, Atmel products are not suit able for, and sh all not be used in, automotive applic ations. Atmel ’s products are not intended, authorized, or w arranted for use as components in applic ations intended to support or sust ain life. © 200 8 Atmel Corpor ation. All rights reserved. Atmel ®, logo and com binations thereof, and others, are registered tr ademarks or tr ademarks of Atmel Corpor ation or its su bsidiaries. Other terms and product n ames m ay be trademarks of others.