AT24C01A_04 ATMEL | Alldatasheet
Document overview
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Technical content
Features
- Medium-voltage and Standard-voltage Operation – 5.0 (VCC = 4.5V to 5.5V) – 2.7 (VCC = 2.7V to 5.5V)
- Internally Organized 128 x 8 (1K), 256 x 8 (2K), 512 x 8 (4K), 1024 x 8 (8K) or 2048 x 8 (16K)
- Two-wire Serial Interface
- Schmitt Trigger, Filtered Inputs for Noise Suppression
- Bi-directional Data Transfer Protocol
- 100 kHz (2.7V) and 400 kHz (5V) Compatibility
- Write Protect Pin for Hardware Data Protection
- 8-byte Page (1K, 2K), 16-byte Page (4K, 8K, 16K) Write Modes
- Partial Page Writes are Allowed
- Self-timed Write Cycle (5 ms max)
- High-reliability – Endurance: 1 Million Write Cycles – Data Retention: 100 Years
- 8-lead PDIP and 8-lead JEDEC SOIC Packages
Description
The AT24C01A/02/04/08/16 provides 1024/2048/4096/8192/16384 bits of serial elec- trically erasable and programmable read-only memory (EEPROM) organized as 128/256/512/1024/2048 words of 8 bits each. The device is optimized for use in many automotive applications where low-power and low-voltage operation are essential. The AT24C01A/02/04/08/16 is available in space-saving 8-lead PDIP and 8-lead JEDEC SOIC packages and is accessed via a two-wire serial interface. In addition, Table 1. Pin Configuration
- This device is not recom-
Figure 1. Block Diagram EEPROM device and negative edge clock data out of each device. discussed in detail under the Device Addressing section). devices may be addressed on a single bus system. The A0 pin is a no connect.
on a single bus to one. The A0, A1 and A2 pins are no connects. write protection feature is enabled and operates as shown see Table 2. Table 2. Write Protect
- This device is not recommended for new designs. Please refer to AT24C08A.
- This device is not recommended for new designs. Please refer to AT24C16A.
the 1K requires a 7-bit data word address for random word addressing. the 2K requires an 8-bit data word address for random word addressing. the 4K requires a 9-bit data word address for random word addressing. the 8K requires a 10-bit data word address for random word addressing. each, the 16K requires an 11-bit data word address for random word addressing.
- This parameter is characterized and is not 100% tested.
- VIL min and VIH max are reference only and are not tested.
Table 3. Pin Capacitance(1) Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +2.7V. Table 4. DC Characteristics
- The AT24C01A/02/04/08 bearing the process letter “D” on the package (the mark is located in the lower right corner on the
topside of the package), guarantees 400 kHz (2.5V, 2.7V).
- This parameter is characterized and is not 100% tested (TA = 25°C).
- This parameter is characterized and is not 100% tested.
which must precede any other command (see Figure 5 on page 7). STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. mode (see Figure 5 on page 7). received each word. This happens during the ninth clock cycle. Table 5. AC Characteristics 100 pF (unless otherwise noted).
3256F–SEEPR–10/04 Device Addressing The 1K, 2K, 4K, 8K and 16K EEPROM devices all require an 8-bit device address word following a start condition to enable the chip for a read or write operation (see Figure 7 on page 9). The device address word consists of a mandatory one, zero sequence for the first four most significant bits as shown. This is common to all the EEPROM devices. The next 3 bits are the A2, A1 and A0 device address bits for the 1K/2K EEPROM. These 3 bits must compare to their corresponding hard-wired input pins. The 4K EEPROM only uses the A2 and A1 device address bits with the third bit being a memory page address bit. The two device address bits must compare to their corre- sponding hard-wired input pins. The A0 pin is no connect. The 8K EEPROM only uses the A2 device address bit with the next 2 bits being for memory page addressing. The A2 bit must compare to its corresponding hard-wired input pin. The A1 and A0 pins are no connect. The 16K does not use any device address bits but instead the 3 bits are used for mem- ory page addressing. These page addressing bits on the 4K, 8K and 16K devices should be considered the most significant bits of the data word address which follows. The A0, A1 and A2 pins are no connect. The eighth bit of the device address is the read/write operation select bit. A read opera- tion is initiated if this bit is high and a write operation is initiated if this bit is low. Upon a compare of the device address, the EEPROM will output a zero. If a compare is not made, the chip will return to a standby state. Write Operations BYTE WRITE: A write operation requires an 8-bit data word address following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a zero and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a zero and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condi- tion. At this time the EEPROM enters an internally timed write cycle, tWR, to the nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write is complete (see Figure 8 on page 10). PAGE WRITE: The 1K/2K EEPROM is capable of an 8-byte page write, and the 4K, 8K and 16K devices are capable of 16-byte page writes. A page write is initiated the same as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit up to seven (1K/2K) or fifteen (4K, 8K, 16K) more data words. The EEPROM will respond with a zero after each data word received. The microcontroller must terminate the page write sequence with a stop condition (see Figure 9 on page 10). The data word address lower three (1K/2K) or four (4K, 8K, 16K) bits are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. When the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than eight (1K/2K) or sixteen (4K, 8K, 16K) data words are transmitted to the EEPROM, the data word address will “roll over” and previ- ous data will be overwritten. ACKNOWLEDGE POLLING: Once the internally timed write cycle has started and the EEPROM inputs are disabled, acknowledge polling can be initiated. This involves send-
will the EEPROM respond with a zero allowing the read or write sequence to continue. operations: current address read, random address read and sequential read. rent page to the first byte of the same page. acknowledged by the EEPROM, the current address data word is serially clocked out. stop condition (see Figure 10 on page 10). with a zero but does generate a following stop condition (see Figure 11 on page 11). tion (see Figure 12 on page 11). Figure 7. Device Address
3256F–SEEPR–10/04 Ordering Code Package Operation Range AT24C01A-10PA-5.0C AT24C01A-10SA-5.0C 8P3 8S1 Automotive (−40°C to 125°C) AT24C01A-10PA-2.7C AT24C01A-10SA-2.7C 8P3 8S1 Automotive (−40°C to 125°C) Package Type 8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) Options −5.0 Standard Operation (4.5V to 5.5V) −2.7 Low-voltage (2.7V to 5.5V)
3256F–SEEPR–10/04 Ordering Code Package Operation Range AT24C02-10PA-5.0C AT24C02N-10SA-5.0C 8P3 8S1 Automotive (−40°C to 125°C) AT24C02-10PA-2.7C AT24C02N-10SA-2.7C 8P3 8S1 Automotive (−40°C to 125°C) Package Type 8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) Options −5.0 Standard Operation (4.5V to 5.5V) −2.7 Low-voltage (2.7V to 5.5V)
3256F–SEEPR–10/04 Ordering Code Package Operation Range AT24C04-10PA-5.0C AT24C04N-10SA-5.0C 8P3 8S1 Automotive (−40°C to 125°C) AT24C04-10PA-2.7C AT24C04N-10SA-2.7C 8P3 8S1 Automotive (−40°C to 125°C) Package Type 8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) Options −5.0 Standard Operation (4.5V to 5.5V) −2.7 Low-voltage (2.7V to 5.5V)
3256F–SEEPR–10/04 Note: 1. This device is not recommended for new designs. Please refer to AT24C08A. AT24C08(1) Ordering Information Ordering Code Package Operation Range AT24C08-10PA-5.0C AT24C08N-10SA-5.0C 8P3 8S1 Automotive (−40°C to 125°C) AT24C08-10PA-2.7C AT24C08N-10SA-2.7C 8P3 8S1 Automotive (−40°C to 125°C) Package Type 8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) Options −5.0 Standard Operation (4.5V to 5.5V) −2.7 Low-voltage (2.7V to 5.5V)
3256F–SEEPR–10/04 Note: 1. This device is not recommended for new designs. Please refer to AT24C16A. AT24C16(1) Ordering Information Ordering Code Package Operation Range AT24C16-10PA-5.0C AT24C16N-10SA-5.0C 8P3 8S1 Automotive (−40°C to 125°C) AT24C16-10PA-2.7C AT24C16N-10SA-2.7C 8P3 8S1 Automotive (−40°C to 125°C) Package Type 8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) Options −5.0 Standard Operation (4.5V to 5.5V) −2.7 Low-voltage (2.7V to 5.5V)
3256F–SEEPR–10/04 Packaging Information 8P3 – PDIP
2325 Orchard Parkway
San Jose, CA 95131 TITLE DRAWING NO. R REV. 8P3, 8-lead, 0.300" Wide Body, Plastic Dual In-line Package (PDIP) 01/09/02 8P3 B Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA, for additional information. 2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3. 3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch. 4. E and eA measured with the leads constrained to be perpendicular to datum. 5. Pointed or rounded lead tips are preferred to ease insertion. COMMON DIMENSIONS (Unit of Measure = inches) SYMBOL MIN NOM MAX NOTE D E e L b A2 A N eA c
4 PLCS
A 0.210 0.115 0.130 0.195 b 0.014 0.018 0.022 0.045 0.060 0.070 0.030 0.039 0.045 c 0.008 0.010 0.014 D 0.355 0.365 0.400 0.005 E 0.300 0.310 0.325 0.240 0.250 0.280 e
0.100 BSC
0.300 BSC
L 0.115 0.130 0.150 Top View Side View End View
3256F–SEEPR–10/04 8S1 – JEDEC SOIC San Jose, CA 95131 TITLE DRAWING NO. R REV. 8S2, 8-lead, 0.209" Body, Plastic Small Outline Package (EIAJ) 10/7/03 8S2 C COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE Notes: 1. This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information. 2. Mismatch of the upper and lower dies and resin burrs are not included. 3. It is recommended that upper and lower cavities be equal. If they are different, the larger dimension shall be regarded. 4. Determines the true geometric position. A 1.70 2.16 0.05 0.25 b 0.35 0.48 C 0.15 0.35 D 5.13 5.35 5.18 5.40 2, 3 E 7.70 8.26 L 0.51 0.85 e
1.27 BSC
e b A D E N C L Top View
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