AT24C01-10MI-2.7

AT24C01 ATMEL | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 10

Technical content

Features

• Low Voltage and Standard Voltage Operation – 5.0 (VCC = 4.5V to 5.5V) – 2.7 (VCC = 2.7V to 5.5V) – 2.5 (VCC = 2.5V to 5.5V) – 1.8 (VCC = 1.8V to 5.5V)
• Internally Organized 128 x 8
• 2-Wire Serial Interface
• Bidirectional Data Transfer Protocol
• 100 kHz (1.8V , 2.5V , 2.7V) and 400 kHz (5V) Compatibility
• 4-Byte Page Write Mode
• Self-Timed Write Cycle (10 ms max)
• High Reliability – Endurance: 1 Million Write Cycles – Data Retention: 100 Years – ESD Protection: >3000V
• Automotive Grade and Extended Temperature Devices Available
• 8-Pin PDIP , 8-Pin MSOP , 8-Pin TSSOP and 8-Pin JEDEC SOIC Packages

Description

The AT24C01 provides 1024 bits of serial electrically erasable and programmable read only memory (EEPROM) organized as 128 words of 8 bits each. The device is optimized for use in many industrial and commercial applications where low power and low voltage operation are essential. The AT24C01 is available in space saving 8-pin PDIP, 8-pin MSOP, 8-pin TSSOP, and 8-pin JEDEC SOIC packages and is accessed via a 2-wire serial interface. In addition, the entire family is available in 5.0V sions. 2-Wire Serial EEPROM 1K (128 x 8) AT24C01 Rev. 0134C–07/98 2-Wire, 1K Serial EEPROM Pin Configurations Pin Name Function NC No Connect SDA Serial Data SCL Serial Clock Input T est T est Input (GND or V CC ) 8-Pin PDIP NC NC NC GND VCC TEST SCL SDA 8-Pin SOIC NC NC NC GND VCC TEST SCL SDA 8-Pin MSOP 8-Pin TSSOP NC NC NC GND VCC TEST SCL SDA

SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device. SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open collector devices. Memory Organization AT24C01, 1K SERIAL EEPROM: Internally organized with 128 pages of 1 byte each. The 1K requires a 7-bit data word address for random word addressing. Absolute Maximum Ratings* Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Voltage on Any Pin

Note: 1. V IL min and VIH max are reference only and are not tested. Pin Capacitance Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +1.8V. Symbol Test Condition Max Units Condition C I/O Input/Output Capacitance (SDA) 8 pF V I/O = 0V C IN Input Capacitance (A0, A1, A2, SCL) 6 pF V IN = 0V DC Characteristics Applicable over recommended operating range from: TAI = -40°C to +85°C, VCC = +1.8V to +5.5V, TAC = 0°C to +70°C, VCC = +1.8V to +5.5V (unless otherwise noted). Symbol Parameter Test Condition Min Typ Max Units VCC1 Supply Voltage 1.8 5.5 V VCC2 Supply Voltage 2.5 5.5 V VCC3 Supply Voltage 2.7 5.5 V VCC4 Supply Voltage 4.5 5.5 V ICC Supply Current VCC = 5.0V READ at 100 KHz 0.4 1.0 mA ICC Supply Current VCC = 5.0V WRITE at 100 KHz 2.0 3.0 mA ISB1 Standby Current VCC = 1.8V V IN = VCC or VSS 0.6 3.0 µA ISB2 Standby Current VCC = 2.5V V IN = VCC or VSS 1.4 4.0 µA ISB3 Standby Current VCC = 2.7V V IN = VCC or VSS 1.6 4.0 µA ISB4 Standby Current VCC = 5.0V V IN = VCC or VSS 8.0 18.0 µA ILI Input Leakage Current V IN = VCC or VSS 0.10 3.0 µA ILO Output Leakage Current V OUT = VCC or VSS 0.05 3.0 µA VIL Input Low Level(1) -0.6 V CC × 0.3 V VIH Input High Level(1) VCC × 0.7 V CC + 0.5 V VOL2 Output Low Level VCC = 3.0V I OL = 2.1 mA 0.4 V VOL1 Output Low Level VCC = 1.8V I OL = 0.15 mA 0.2 V

Note: 1. This parameter is characterized and is not 100% tested. Device Operation CLOCK and DATA TRANSITIONS: The SDA pin is nor- mally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (refer to Data Validity timing diagram). Data changes during SCL high periods will indicate a start or stop condition as defined below. START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (refer to Start and Stop Definition timing dia- gram). STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition which terminates all communi- cations. After a read sequence, the stop command will place the EEPROM in a standby power mode (refer to Start and Stop Definition timing diagram). ACKNOWLEDGE: All addresses and data words are seri- ally transmitted to and from the EEPROM in 8-bit words. Any device on the system bus receiving data (when com- municating with the EEPROM) must pull the SDA bus low to acknowledge that it has successfully received each word. This must happen during the ninth clock cycle after each word received and after all other system devices have freed the SDA bus. The EEPROM will likewise acknowl- edge by pulling SDA low after receiving each address or data word (refer to Acknowledge Response from Receiver timing diagram). STANDBY MODE: The AT24C01 features a low power standby mode which is enabled: (a) upon power-up and (b) after the receipt of the STOP bit and the completion of any internal operations. MEMORY RESET: After an interruption in protocol, power loss or system reset, any 2-wire part can be reset by follow- ing these steps: (a) Clock up to 9 cycles, (b) look for SDA high in each cycle while SCL is high and then (c) create a start condition as SDA is high. AC Characteristics Applicable over recommended operating range from TA = -40°C to +85°C, VCC = +1.8V to +5.5V, CL = 1 TTL Gate and 100 pF (unless otherwise noted). Symbol Parameter 2.7-, 2.5-, 1.8-volt 5.0-volt UnitsMin Max Min Max fSCL Clock Frequency, SCL 100 400 KHz tLOW Clock Pulse Width Low 4.7 1.2 µs tHIGH Clock Pulse Width High 4.0 0.6 µs tI Noise Suppression Time(1) 100 50 ns tAA Clock Low to Data Out Valid 0.1 4.5 0.1 0.9 µs tBUF Time the bus must be free before a new transmission can start(1) 4.7 1.2 µs tHD.ST A Start Hold Time 4.0 0.6 µs tSU.ST A Start Set-up Time 4.7 0.6 µs tHD.DAT Data In Hold Time 0 0 µs tSU.DA T Data In Set-up Time 200 100 ns tR Inputs Rise Time(1) 1.0 0.3 µs tF Inputs Fall Time(1) 300 300 ns tSU.STO Stop Set-up Time 4.7 0.6 µs tDH Data Out Hold Time 100 50 ns tWR Write Cycle Time 10 10 ms Endurance(1) 5.0V , 25°C, Page Mode 1M 1M Write Cycles

SCL: Serial Clock, SDA: Serial Data I/O Write Cycle Timing SCL: Serial Clock, SDA: Serial Data I/O Note: 1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle. SCL SDA WORD n 8th BIT ACK STOP CONDITION START CONDITION tWR (1)

write sequence with a stop condition (refer to Figure 2). operations: byte read and sequential read. followed by a 7-bit data word address and a high read bit. condition (refer to Figure 3). stop condition (refer to Figure 4). Figure 1. Byte Write

Ordering Information

tWR (max) (ms) ICC (max) (µA) ISB (max) (µA) fMAX (kHz) Ordering Code Package Operation Range 10 3000 18 400 A T24C01-10PC AT24C01-10SC AT24C01-10MC AT24C01-10TC 8P3 8S1 Commercial (0°C to 70°C) 3000 18 400 A T24C01-10PI AT24C01-10SI AT24C01-10MI AT24C01-10TI 8P3 8S1 Industrial (-40°C to 85°C) 10 1500 4 100 A T24C01-10PC-2.7 A T24C01-10SC-2.7 A T24C01-10MC-2.7 A T24C01-10TC-2.7 8P3 8S1 Commercial (0°C to 70°C) 1500 4 100 A T24C01-10PI-2.7 A T24C01-10SI-2.7 AT24C01-10MI-2.7 A T24C01-10TI-2.7 8P3 8S1 Industrial (-40°C to 85°C) 10 1000 4 100 A T24C01-10PC-2.5 A T24C01-10SC-2.5 A T24C01-10MC-2.5 A T24C01-10TC-2.5 8P3 8S1 Commercial (0°C to 70°C) 1000 4 100 A T24C01-10PI-2.5 A T24C01-10SI-2.5 AT24C01-10MI-2.5 A T24C01-10TI-2.5 8P3 8S1 Industrial (-40°C to 85°C) 10 800 3 100 A T24C01-10PC-1.8 A T24C01-10SC-1.8 A T24C01-10MC-1.8 A T24C01-10TC-1.8 8P3 8S1 Commercial (0°C to 70°C) 800 3 100 A T24C01-10PI-1.8 A T24C01-10SI-1.8 AT24C01-10MI-1.8 A T24C01-10TI-1.8 8P3 8S1 Industrial (-40°C to 85°C) Package Type 8M 8-Lead, 0.118” Wide, Miniature Small Outline Package (MSOP) 8P3 8-Lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8S1 8-Lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 8T 8-Lead, 0.170” Wide, Thin Shrink Small Outline Package (TSSOP) Options Blank Standard Operation (4.5V to 5.5V) -2.7 Low-Voltage (2.7V to 5.5V) -2.5 Low-Voltage (2.5V to 5.5V) -1.8 Low-Voltage (1.8V to 5.5V)

0.23 (0.009) 0.13 (0.005) 1.10 (0.043) 0.97 (0.038) 0.15 (0.006) 0.05 (0.002) 0.40 (0.016) 0.25 (0.010) 3.10 (0.122) 2.90 (0.114) 3.10 (0.122) 2.90 (0.114) PIN 1 0.65 (0.026) TYP 4.90 (0.193) REF 3.81 (0.150) REF .400 (10.16) .355 (9.02) PIN .280 (7.11) .240 (6.10) .037 (.940) .210 (5.33) MAX SEATING PLANE .100 (2.54) BSC .015 (.380) MIN .022 (.559) .014 (.356) .150 (3.81) .115 (2.92) .070 (1.78) .045 (1.14) .325 (8.26) .300 (7.62)

15 REF

.430 (10.9) MAX .012 (.305) .008 (.203) .020 (.508) .013 (.330) PIN 1 .157 (3.99) .150 (3.81) .244 (6.20) .228 (5.79) .050 (1.27) BSC .196 (4.98) .189 (4.80) .068 (1.73) .053 (1.35) .010 (.254) .004 (.102) 8 REF .010 (.254) .007 (.203) .050 (1.27) .016 (.406) *Controlling dimension: millimeters 6.50 (.256) 6.25 (.246) 0.30 (.012) 0.19 (.008) .65 (.026) BSC 1.05 (.041) 0.80 (.033) 3.10 (.122) 4.5 (.177) 2.90 (.114) 4.3 (.169) 0.15 (.006) 0.05 (.002) 1.20 (.047) MAX 0.20 (.008) 0.75 (.030) 0.09 (.004) 0.45 (.018)0

8 REF

8M, 8-Lead, 0.118” Wide, Miniature Small Outline Package (MSOP) 8P3, 8-Lead, 0.300” Wide, Plastic Dual Inline Package (PDIP) Dimensions in Inches and (Millimeters) JEDEC STANDARD MS-001 BA 8S1, 8-Lead, 0.150” Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) Dimensions in Inches and (Millimeters) 8T, 8-Lead 0.170” Wide, Thin Shrink Small Outline Package (TSSOP) Dimensions in Millimeters and (Inches)*