AT22V10B ATMEL | Alldatasheet

Document overview

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Technical content

Features

  • High Performance Programmable Logic Device 7.5 ns Max Propagation Delay Up to 166 MHz Operation

5 V ± 10% Operation

  • Fully Compatible with Standard 22V10 Identical Functionality/Fuse-Map
  • TTL Compatible Inputs and Outputs 10 µA Leakage Maximum
  • Reprogrammable - Tested 100% for Programmability
  • High Reliability Proven UV Erasable CMOS Technology

2000 V ESD Protection

200 mA Latch-Up Protection

  • Full Military, Commercial and Industrial Temperature Ranges
  • Dual-In-Line and Surface Mount Packages with Standard Pinouts PROGRAMMABLE INTERCONNECT AND COMBINATORIAL LOGIC ARRAY LOGIC OPTION (UP T0 10 FLIP-FLOPS) OUTPUT OPTION 8T O1 6 PRODUCT TERMS OE PRODUCT TERMS I/O PINS INPUT PINS Logic Diagram GND IN I/O I/O IN VCC CLK/IN I/O I/O IN IN 228 GND 1312 IN Vcc I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O IN CLK/IN IN IN IN IN IN IN IN IN IN IN I/O I/O I/O I/O I/O I/O IN IN IN IN IN IN 0226B AT22V10B 1-109

Q SP D AR Q CK To Output Voltage on Any Pin with Voltage on Input Pins with Respect to Ground (1) Programming Voltage with (1) *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect de- vice reliability. Note: 1. Minimum voltage is -0.6 V dc which may undershoot to -2.0 V for pulses of less than 20 ns. Maximum output pin voltage is V CC +0.75 V dc which may overshoot to +7.0 V for pulses of less than 20 ns. Absolute Maximum Ratings* The AT22V10B incorporates a variable product term architec- ture. Each output is allocated from eight to 16 product terms, which allows highly complex logic functions to be realized. The AT22V10B includes two additional product terms to pro- vide synchronous preset and asynchronous reset. These terms are common to all ten registers. All registers are automatically cleared upon power up. Register preload simplifies testing. A security fuse prevents un- authorized copying of programmed fuse patterns. Description (Continued) 1-110 AT22V10B

D.C. Characteristics Symbol Parameter Condition Min Max Units ILI Input Load Current V IN = -0.1 V to VCC +1 V 10 µA ILO Output Leakage Current V OUT = -0.1 V to VCC +0.1 V 10 µA ICC Power Supply Current f = 0 MHz to FMAX , VCC = MAX, VIN = GND, Outputs Open Com. 140 mA Ind., Mil. 160 mA IOS (1) Output Short Circuit Current VOUT = 0.5 V -30 -120 mA VIL Input Low Voltage -0.6 0.8 V VIH Input High Voltage 2.0 VCC +0.75 V VOL Output Low Voltage VIN = VIH or VIL, VCC = MIN IOL = 16 mA Com.,Ind. 0.5 V IOL = 12 mA Mil. 0.5 V IOL = 24 mA Com. 0.8 V VOH Output High Voltage VIN = VIH or VIL, VCC = MIN IOH = -4.0 mA 2.4 V Notes: 1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec. D.C. and A.C. Operating Conditions Commercial AT22V10B Commercial AT22V10B -10 Industrial AT22V10B -10 Military AT22V10B -10 Operating Temperature (Case) 0 oC - 70oC0 oC - 70oC- 4 0 oC - 85oC- 5 5 oC - 125oC VCC Power Supply 5 V ± 5% 5 V ± 10% 5 V ± 10% 5 V ± 10% AT22V10B 1-111

5.0V CL= 50pF R1= 338 R2= 248 Ω Ω Military AC MEASUREMENT LEVEL AC DRIVING LEVELS 0.0V 3.0V 1.5V tR, tF < 2 ns (10% to 90%) Input Test Waveforms and Measurement Levels tCO tAP tER HIGH ZOUTPUT VALID OUTPUT VALIDOUTPUTS ASYNCH. RESET INPUTS,I/O CP tP tWH tS OUTPUTS VALID OUTPUT VALID OUTPUT HIGH Z REG. FEEDBACK SYNCH. PRESET REGISTERED COMBINATORIAL tH tPD tWP tAR tAW OUTPUT VALID VALID OUTPUT tER tEA tEA A.C. Waveforms (1) OUTPUT PIN 5.0V CL= 50pF R1= 250 R2= 167 Ω Ω Output Test Loads: Commercial (1) Note: 1. CL = 30 pF for AT22V10B-7 A.C. Characteristics AT22V10B-7 AT22V10B-10 Symbol Parameter Min Typ Max Min Typ Max Units tPD Input or Feedback to Non-Registered Output 5 7.5 6 10 ns tEA Input to Output Enable 5 7.5 6 10 ns tER Input to Output Disable 5 7.5 6 10 ns tCF (1) Clock to Feedback 0 1 2 0 1 2 ns tCO Clock to Output 0 3.5 5.5 0 4 7 ns tS Input or Feedback Setup Time 3.5 2 5 3 ns tH Hold Time 0 0 ns tP Clock Period 6 7 ns tWL (1) Clock Width Low 3 3.5 ns tWH Clock Width High 3 3.5 ns FMAX External Feedback 1/(tS+tCO ) 111 83 MHz Internal Feedback 1/(tS + tCF ) 166 142 MHz No Feedback 1/(tP) 166 142 MHz tAW Asynchronous Reset Width 6 3 7 4 ns tAR Asynchronous Reset, Synchronous Preset, Recovery Time 74 85 n s tAP Asynchronous Reset to Registered Output Reset 61 0 81 4 n s Note: 1. This parameter is only sampled and is not 100% tested. 1-112 AT22V10B

Functional Logic Diagram AT22V10B AT22V10B 1-113

Pin Capacitance (f = 1 MHz, T = 25°C) (1) Typ Max Units Conditions C IN 58 p F V IN = 0 V C OUT 68 p F V OUT = 0 V Note: 1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested. Power Up Reset The registers in the AT22V10B are designed to reset during power up. At a point delayed slightly from VCC crossing 3.8 V, all registers will be reset to the low state. The output state will depend on the polarity of the output buffer. This feature is critical for state machine initialization. However, due to the asynchronous nature of reset and the uncertainty of how V CC actually rises in the system, the following conditions are required: 1) The VCC rise must be monotonic, 2) After reset occurs, all input and feedback setup times must be met before driving the clock pin high, and 3) The clock must remain stable during tPR . Parameter Description Min Typ Max Units tPR Power-Up Reset Time 600 1000 ns CLOCK 3.8 V POWER REGISTERED OUTPUTS tS tPR tW Erasure Characteristics The entire fuse array of an AT22V10B is erased after exposure to ultraviolet light at a wavelength of 2537 Å. Complete erasure is assured after a minimum of 20 minutes exposure using 12,000 µW/cm 2 intensity lamps spaced one inch away from the chip. Minimum erase time for lamps at other intensity ratings can be calculated from the minimum integrated erasure dose of 15 W •sec/cm2. To prevent unintentional erasure, an opaque label is recommended to cover the clear window on any UV erasable PLD which will be subjected to continuous fluorescent indoor lighting or sunlight. Preload of Registered Outputs The registers in the AT22V10B are provided with circuitry to allow loading of each register asynchronously with either a high or a low. This feature will simplify testing since any state can be forced into the registers to control test sequencing. A V IH level on the I/O pin will force the register high; a VIL will force it low, independent of the polarity bit (C0) setting. The preload state is entered by placing an 10.5-V to 12-V signal on pin 8 on DIPs, and pin 10 on SMPs. When the clock pin is pulsed high, the data on the I/O pins is placed into the ten registers. CLOCK VH OUTPUTS DISABLED PRELOAD CLOCKEDIN PRELOAD DATA PRELOAD REGISTERED VOLTAGE REMOVED tD tD tDtD tD OUTPUT FORCEI/O’S TO VIH ORVIL PRELOADENA. OUTPUTSDIS. tDMIN = 100 ns Level forced on registered output pin during preload cycle Register state after cycle V IH High VIL Low 1-114 AT22V10B

vs. OUTPUT VOLTAGE (TA = 25C, VCC = 5V) 120 150 O u t p u t C u r r e n t 012345 Output Voltage (V) (mA) OUTPUT SINK CURRENT vs. SUPPLY VOLTAGE (VOL = 0.5V) O u t p u t C u r r e n t Supply Voltage (V) (mA) OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE (TA = 25C, VCC = 5V) O u t p u t C u r r e n t Output Voltage (V) (mA) OUTPUT SOURCE CURRENT vs. SUPPLY VOLTAGE (VOH = 2.4V) -45 -30 -15 O u t p u t C u r r e n t Supply Voltage (V) (mA) OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE (TA = 25C, VCC = 5V) -100 -80 -60 -40 -20 O u t p u t C u r r e n t 012345 Output Voltage (V) (mA) NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 0.6 0.8 1.0 1.2 1.4N o r m a l i z e d I C C Supply Voltage (V) NORMALIZED ICC vs. AMBIENT TEMP. f = 50 MHz 0.6 0.8 1.0 1.2 1.4 N o r m a l i z e d I C C -55 -25 5 35 65 95 125 Ambient Temperature (C) SUPPLY CURRENT vs. INPUT FREQUENCY AT22V10B (TA = 25C, VCC = 5V) 120 150 I C C 0 2 04 06 08 0 1 0 0 Frequency (MHz) (mA) AT22V10B 1-115

DELTA TCO vs. OUTPUT LOADING ( VCC = 4.5V, OUTPUT LOAD = COMMERCIAL ) D e l t a T C O n s 0 100 200 300 400 Output Load (jig included) Capacitance pF DELTA TPD vs. OUTPUT LOADING (VCC = 4.5V, OUTPUT LOAD = COMMERCIAL) D e l t a T P D n s 0 100 200 300 400 Output Load (jig included) Capacitance pF NORMALIZED TS vs. TEMPERATURE 0.7 0.9 1.1 1.3 N o r m a l i z e d T S -55 -25 5 35 65 95 125 Ambient Temperature (C) NORMALIZED TS vs. SUPPLY VOLTAGE 0.7 0.8 0.9 1.0 1.1 1.2 N o r m a l i z e d T S Supply Voltage (V) NORMALIZED TCO vs. TEMPERATURE 0.9 1.1 1.3 1.5N o r m a l i z e d T C O -55 -25 5 35 65 95 125 Ambient Temperature (C) NORMALIZED TCO vs. SUPPLY VOLTAGE 0.9 1.0 1.1 1.2N o r m a l i z e d T C O Supply Voltage (V) NORMALIZED TPD vs. TEMPERATURE 0.7 0.9 1.1 1.3 1.5N o r m a l i z e d T P D -55 -25 5 35 65 95 125 Ambient Temperature (C) NORMALIZED TPD vs. SUPPLY VOLTAGE 0.9 1.0 1.1 1.2 1.3N o r m a l i z e d T P D Supply Voltage (V) 1-116 AT22V10B

(ns) tS (ns) tCO (ns) Ordering Code Package Operation Range 7.5 3.5 5.5 AT22V10B-7DC 24DW3 Commercial AT22V10B-7JC 28J (0 °C to 70°C) AT22V10B-7PC 24P3 10 5 7 AT22V10B-10DC 24DW3 Commercial AT22V10B-10GC 24D3 (0 °C to 70°C) AT22V10B-10JC 28J AT22V10B-10PC 24P3 AT22V10B-10SC 24S AT22V10B-10DI 24DW3 Industrial AT22V10B-10GI 24D3 (-40 °C to 85°C) AT22V10B-10JI 28J AT22V10B-10PI 24P3 AT22V10B-10SI 24S AT22V10B-10DM 24DW3 Military AT22V10B-10GM 24D3 (-55 °C to 125°C) AT22V10B-10LM 28LW AT22V10B-10NM 28L AT22V10B-10DM/883 24DW3 Military/883C AT22V10B-10GM/883 24D3 (-55 °C to 125°C) AT22V10B-10LM/883 28LW Class B, Fully Compliant AT22V10B-10NM/883 28L AT22V10B-12LM/883 28LW AT22V10B-12NM/883 28L 10 5 7 5962-87539 06 LA 24DW3 Military/883C 5962-87539 06 3X 28L (-55 °C to 125°C) Class B, Fully Compliant

Ordering Information

24DW3 24 Lead, 0.300" Wide, Windowed, Ceramic Dual Inline Package (Cerdip) 24D3 24 Lead, 0.300" Wide, Non-Windowed (OTP), Ceramic Dual Inline Package (Cerdip) 28J 28 Lead, Plastic J-Leaded Chip Carrier OTP (PLCC) 28LW 28 Pad, Windowed, Ceramic Leadless Chip Carrier (LCC) 28L 28 Pad, Non-Windowed, Ceramic Leadless Chip Carrier OTP (LCC) 24P3 24 Lead, 0.300" Wide, Plastic Dual Inline Package OTP (PDIP) 24S 24 Lead, 0.300" Wide, Plastic Gull Wing Small Outline OTP (SOIC) AT22V10B 1-117