AT17F080-30JC

AT17F040 ATMEL | Alldatasheet

Document overview

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• PDF pages: 19

Technical content

Features

• Programmable 4,194,304 x 1 and 8,388,608 x 1-bit Serial Memories Designed to Store Configuration Programs for Field Programmable Gate Arrays (FPGAs)
• 3.3V Output Capability
• 5V Tolerant I/O Pins
• Program Support using the Atmel ATDH2200E System or Industry Third Party Programmers
• In-System Programmable (ISP) via 2-wire Bus
• Simple Interface to SRAM FPGAs
• Compatible with Atmel AT40K and AT94K Devices, Altera® FLEX®, APEX™ Devices, Lucent® ORCA® FPGAs, Xilinx® XC3000, XC4000, XC5200, Spartan®, Virtex™ FPGAs, Motorola® MPA1000 FPGAs
• Cascadable Read-back to Support Additional Configurations or Higher-density Arrays
• Low-power CMOS FLASH Process
• Available in 6 mm x 6 mm x 1 mm 8-lead LAP (Pin-compatible with 8-lead SOIC/VOIC Packages), 20-lead PLCC, 44-lead PLCC and 44-lead TQFP Packages
• Emulation of Atmel’s AT24CXXX Serial EEPROMs
• Low-power Standby Mode
• Single Device Capable of Holding 4 Bit Stream Files Allowing Simple System Reconfiguration
• Fast Serial Download Speeds up to 33 MHz
• Endurance: 5,000 Write Cycles Typical
• LHF Package Available (Lead and Halide Free)

Description

The AT17F Series of In-System Programmable Configuration PROMs (Configurators) provide an easy-to-use, cost-effective configuration memory for Field Programmable Gate Arrays. The AT17F Series device is packaged in the 8-lead LAP, 20-lead PLCC, 44-lead PLCC and 44-lead TQFP, see Table 1-1. The AT17F Series Configurator uses a simple serial-access procedure to configure one or more FPGA devices. The AT17F Series Configurators can be programmed with industry-standard program- mers, Atmel’s ATDH2200E Programming Kit or Atmel’s ATDH2225 ISP Cable. Table 1-1. AT17F Series Packages Package AT17F040 AT17F080 8-lead LAP Yes Yes 20-lead PLCC Yes Yes 44-lead PLCC Yes 44-lead TQFP Yes FPGA Configuration Flash Memory AT17F040 AT17F080 3039I–CNFG–2/05

3039I–CNFG–2/05 AT17F040/080 Pin Configuration 8-lead LAP 20-lead PLCC 20-lead PLCC (Virtex Pinout)(1)(2) Notes: 1. 20-lead PLCC (Virtex pinout) is only available in the AT17F040. 2. Virtex pinout is compatible with the XC17V and XC18V Series PROM. DATA CLK RESET/OE CE VCC SER_EN CEO (A2) GND CLK NC RESET/OE PAGESEL1 CE NC SER_EN PAGE_EN READY CEO (A2) NC GND PAGESEL0 NC NC NC DATA NC VCC NC NC NC NC NC RESET/OE SER_EN NC NC READY NC NC CE GND NC CEO (A2) CLK NC DATA VCC NC

3039I–CNFG–2/05 AT17F040/080

44 PLCC

44 TQFP

PAGE_EN VCC NC NC SER_EN NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC READY NC RESET/OE PAGESEL0 CE NC NC GND PAGESEL1 NC CEO(A2) NC NC CLK NC NC DATA PAGE_EN VCC NC NC SER_EN NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC READY

3039I–CNFG–2/05 AT17F040/080 Block Diagram Device Description The control signals for the configuration memory device (CE, RESET/OE and CLK) interface directly with the FPGA device control signals. All FPGA devices can control the entire configura- tion process and retrieve data from the configuration device without requiring an external intelligent controller. The RESET/OE and CE pins control the tri-state buffer on the DATA output pin and enable the address counter. When RESET/OE is driven Low, the configuration device resets its address counter and tri-states its DATA pin. The CE pin also controls the output of the AT17F Series Configurator. If CE is held High after the RESET/OE reset pulse, the counter is disabled and the DATA output pin is tri-stated. When OE is subsequently driven High, the counter and the DATA output pin are enabled. When RESET/OE is driven Low again, the address counter is reset and the DATA output pin is tri-stated, regardless of the state of CE. When the configurator has driven out all of its data and CEO is driven Low, the device tri-states the DATA pin to avoid contention with other configurators. Upon power-up, the address counter is automatically reset. Config. Page Select Power-on Reset Flash Memory Clock/Oscillator Logic 2-wire Serial Programming Serial Download Logic Control Logic CLK CEO(A2) DATA CE RESET/OE SER_EN CE/WE/OE Data Address READY PAGE_EN PAGESEL0 PAGESEL1 Reset

3039I–CNFG–2/05 AT17F040/080 Pin Description 5.1 DATA(1) Three-state DATA output for configuration. Open-collector bi-directional pin for programming. 5.2 CLK(1) Clock input. Used to increment the internal address and bit counter for reading and programming. 5.3 PAGE_EN(2) Input used to enable page download mode. When PAGE_EN is high the configuration download address space is partitioned into 4 equal pages. This gives users the ability to easily store and retrieve multiple configuration bitstreams from a single configuration device. This input works in conjunction with the PAGESEL inputs. PAGE_EN must be remain low if paging is not desired. When SER_EN is Low (ISP mode) this pin has no effect. Notes: 1. This pin has an internal 20 KΩ pull-up resistor. 2. This pin has an internal 30 KΩ pull-down resistor. Table 5-1. Pin Description Name I/O AT17F040 AT17F080 LAP PLCC

20 PLCC

(Virtex) LAP PLCC PLCC TQFP DATA I/O CLK I PAGE_EN I PAGESEL0 I PAGESEL1 I RESET/OE I CE I GND CEO O I READY O SER_EN I VCC

3039I–CNFG–2/05 AT17F040/080 5.4 PAGESEL1:0 Page select inputs. Used to determine which of the 4 memory pages are targeted during a serial configuration download. The address space for each of the pages is shown in Table 5-2. When SER_EN is Low (ISP mode) these pins have no effect. 5.5 RESET/OE(1) Output Enable (active High) and RESET (active Low) when SER_EN is High. A Low level on RESET/OE resets both the address and bit counters. A High level (with CE Low) enables the data output driver. 5.6 CE(1) Chip Enable input (active Low). A Low level (with OE High) allows CLK to increment the address counter and enables the data output driver. A High level on CE disables both the address and bit counters and forces the device into a low-power standby mode. Note that this pin will not enable/disable the device in the 2-wire Serial Programming mode (SER_EN Low). 5.7 GND Ground pin. A 0.2 µF decoupling capacitor between VCC and GND is recommended. 5.8 CEO Chip Enable Output (when SER_EN is High). This output goes Low when the internal address counter has reached its maximum value. If the PAGE_EN input is set High, the maximum value is the highest address in the selected partition. The PAGESEL[1:0] inputs are used to make the 4 partition selections. If the PAGE_EN input is set Low, the device is not partitioned and the address maximum value is the highest address in the device, see Table 5-2 on page 6. In a daisy chain of AT17F Series devices, the CEO pin of one device must be connected to the CE input of the next device in the chain. It will stay Low as long as CE is Low and OE is High. It will then follow CE until OE goes Low; thereafter, CEO will stay High until the entire EEPROM is read again. Notes: 1. This pin has an internal 20 KΩ pull-up resistor. 2. This pin has an internal 30 KΩ pull-down resistor. Table 5-2. Address Space Paging Decodes AT17F040 (4 Mbits) AT17F080 (8 Mbits) PAGESEL = 00, PAGE_EN = 1 00000 – 0FFFFh 00000 – 1FFFFh PAGESEL = 01, PAGE_EN = 1 10000 – 1FFFFh 20000 – 3FFFFh PAGESEL = 10, PAGE_EN = 1 20000 – 2FFFFh 40000 – 5FFFFh PAGESEL = 11, PAGE_EN = 1 30000 – 3FFFFh 60000 – 7FFFFh PAGESEL = XX, PAGE_EN = 0 00000 – 3FFFFh 00000 – 7FFFFh

3039I–CNFG–2/05 AT17F040/080 5.9 A2(1) Device selection input, (when SER_EN Low). The input is used to enable (or chip select) the device during programming (i.e., when SER_EN is Low). Refer to the AT17F Programming Specification available on the Atmel web site for additional details. 5.10 READY Open collector reset state indicator. Driven Low during power-up reset, released when power-up is complete. (recommended 4.7 kΩ pull-up on this pin if used). 5.11 SER_EN(1) The serial enable input must remain High during FPGA configuration operations. Bringing SER_EN Low enables the 2-Wire Serial Programming Mode. For non-ISP applications, SER_EN should be tied to VCC. 5.12 VCC +3.3V (±10%). Notes: 1. This pin has an internal 20 KΩ pull-up resistor. 2. This pin has an internal 30 KΩ pull-down resistor.

3039I–CNFG–2/05 AT17F040/080 FPGA Master Serial Mode Summary The I/O and logic functions of any SRAM-based FPGA are established by a configuration pro- gram. The program is loaded either automatically upon power-up, or on command, depending on the state of the FPGA mode pins. In Master mode, the FPGA automatically loads the config- uration program from an external memory. The AT17F Serial Configuration PROM has been designed for compatibility with the Master Serial mode. This document discusses the Atmel AT40K, AT40KAL and AT94KAL applications as well as Xil- inx applications. Control of Configuration Most connections between the FPGA device and the AT17F Serial Configurator PROM are sim- ple and self-explanatory.

• The DATA output of the AT17F Series Configurator drives DIN of the FPGA devices.
• The master FPGA CCLK output drives the CLK input of the AT17F Series Configurator.
• The CEO output of any AT17F Series Configurator drives the CE input of the next Configurator in a cascade chain of configurator devices.
• SER_EN must be connected to VCC (except during ISP).
• The READY pin is available as an open-collector indicator of the device’s reset status; it is driven Low while the device is in its power-on reset cycle and released (tri-stated) when the cycle is complete.
• PAGE_EN must be held Low if download paging is not desired. The PAGESEL[1:0] inputs must be tied off High or Low. If paging is desired, PAGE_EN must be High and the PAGESEL pins must be set to High or Low such that the desired page is selected, see Table 5-2 on page 6. Cascading Serial Configuration Devices For multiple FPGAs configured as a daisy-chain, or for FPGAs requiring larger configuration memories, cascaded configurators provide additional memory. After the last bit from the first configurator is read, the clock signal to the configurator asserts its CEO output Low and disables its DATA line driver. The second configurator recognizes the Low level on its CE input and enables its DATA output. After configuration is complete, the address counters of all cascaded configurators are reset if the RESET/OE on each configurator is driven to its active (Low) level. If the address counters are not to be reset upon completion, then the RESET/OE input can be tied to its inactive (High) level. Programming Mode The programming mode is entered by bringing SER_EN Low. In this mode the chip can be pro- grammed by the 2-wire serial bus. The programming is done at VCC supply only. Programming super voltages are generated inside the chip. The AT17F parts are read/write at 3.3V nominal. Refer to the AT17F Programming Specification available on the Atmel web site (www.atmel.com) for more programming details. AT17F devices are supported by the Atmel ATDH2200 programming system along with many third party programmers.

3039I–CNFG–2/05 AT17F040/080 10. Standby Mode The AT17F Series Configurators enter a low-power standby mode whenever SER_EN is High and CE is asserted High. In this mode, the AT17F Configurator consumes less than 1 mA of cur- rent at 3.3V. The output remains in a high-impedance state regardless of the state of the OE input. 11. Absolute Maximum Ratings* *NOTICE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those listed under oper- ating conditions is not implied. Exposure to Abso- lute Maximum Rating conditions for extended periods of time may affect device reliability. Voltage on Any Pin 12. Operating Conditions Symbol Supply voltage relative to GND -0°C to +70°C 2.97 3.63 V Industrial Supply voltage relative to GND -40°C to +85°C 2.97 3.63 V 13. DC Characteristics Symbol 2.0 VCC 2.0 VCC V VIL Low-level Input Voltage 0.8 0.8 V VOH High-level Output Voltage (IOH = -2.5 mA) Commercial 2.4 2.4 V VOL Low-level Output Voltage (IOL = +3 mA) 0.4 0.4 V VOH High-level Output Voltage (IOH = -2 mA) Industrial 2.4 2.4 V VOL Low-level Output Voltage (IOL = +3 mA) 0.4 0.4 V ICCA Supply Current, Active Mode mA IL Input or Output Leakage Current (VIN = VCC or GND) -10 -10 µA ICCS Supply Current, Standby Mode Commercial mA Industrial mA

3039I–CNFG–2/05 AT17F040/080 14. AC Characteristics 15. AC Characteristics when Cascading CE RESET/OE CLK DATA TSCE TLC THC TCAC TOE TCE TOH THOE TSCE THCE TDF TOH CE RESET/OE CLK DATA CEO TCDF TOCK TOCE TOCE TOOE LAST BIT FIRST BIT

3039I–CNFG–2/05 AT17F040/080 Notes: 1. Preliminary specifications for military operating range only. 2. AC test lead = 50 pF. 3. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steady-state active levels. 4. See the AT17F Programming Specfication for procedural information. 16. AC Characteristics Symbol (2) OE to Data Delay Commercial ns Industrial(1) ns TCE (2) CE to Data Delay Commercial ns Industrial(1) ns TCAC (2) CLK to Data Delay Commercial ns Industrial(1) ns TOH Data Hold from CE, OE, or CLK Commercial ns Industrial(1) ns TDF (3) CE or OE to Data Float Delay Commercial ns Industrial(1) ns TLC CLK Low Time Commercial ns Industrial(1) ns THC CLK High Time Commercial ns Industrial(1) ns TSCE CE Setup Time to CLK (to guarantee proper counting) Commercial ns Industrial(1) ns THCE CE Hold Time from CLK (to guarantee proper counting) Commercial ns Industrial(1) ns THOE RESET/OE Low Time (guarantees counter is reset) Commercial ns Industrial(1) ns FMAX Maximum Input Clock Frequency SEREN = 0 Commercial MHz Industrial(1) MHz FMAX Maximum Input Clock Frequency SEREN = 1 Commercial MHz Industrial(1) MHz TWR Write Cycle Time(4) Commercial µs Industrial(1) µs TEC Erase Cycle Time(4) Commercial s Industrial(1) s

3039I–CNFG–2/05 AT17F040/080 Notes: 1. AC test lead = 50 pF. 2. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steady-state active levels. 16.1 AC Characteristics When Cascading Symbol (3) CLK to Data Float Delay Commercial ns Industrial ns TOCK (2) CLK to CEO Delay Commercial ns Industrial ns TOCE (2) CE to CEO Delay Commercial ns Industrial ns TOOE (2) RESET/OE to CEO Delay Commercial ns Industrial ns FMAX Maximum Input Clock Frequency Commercial MHz Industrial MHz

3039I–CNFG–2/05 AT17F040/080 Note: 1. Airflow = 0 ft/min. 17. Thermal Resistance Coefficients Package Type AT17F040 AT17F080 8CN4 Leadless Array Package (LAP) θJC [°C/W] θJA °C/W 20J Plastic Leaded Chip Carrier (PLCC) θJC [°C/W] θJA °C/W 44A Thin Plastic Quad Flat Package (TQFP) θJC [°C/W] θJA °C/W 44J Plastic Leaded Chip Carrier (PLCC) θJC [°C/W] θJA °C/W

3039I–CNFG–2/05 AT17F040/080 18. Ordering Information Memory Size Ordering Code Package Operation Range 4-Mbit AT17F040-30CC AT17F040-30JC AT17F040-30VJC 8CN4 - 8 LAP 20J - 20 PLCC 20J - 20 PLCC Commercial (0°C to 70°C) AT17F040-30CI AT17F040-30JI AT17F040-30VJI 8CN4 - 8 LAP 20J - 20 PLCC 20J - 20 PLCC Industrial (-40°C to 85°C) AT17F040-30CU AT17F040-30JU 8CN4 - 8 LAP 20J - 20 PLCC LHF Industrial (-40°C to 85°C) 8-Mbit AT17F080-30CC AT17F080-30JC AT17F080-30TQC AT17F080-30BJC 8CN4 - 8 LAP 20J - 20 PLCC 44A - 44 TQFP 44J - 44 PLCC Commercial (0°C to 70°C) AT17F080-30CI AT17F080-30JI AT17F080-30TQI AT17F080-30BJI 8CN4 - 8 LAP 20J - 20 PLCC 44A - 44 TQFP 44J - 44 PLCC Industrial (-40°C to 85°C) AT17F080-30CU AT17F080-30JU 8CN4 - 8 LAP 20J - 20 PLCC LHF Industrial (-40°C to 85°C) Package Type 8CN4 8-lead, 6 mm x 6 mm x 1 mm, Leadless Array Package (LAP) – Pin-compatible with 8-lead SOIC/VOIC Packages 20J 20-lead, Plastic J-leaded Chip Carrier (PLCC) 44A 44-lead, Thin (1.0 mm) Plastic Quad Flat Package Carrier (TQFP) 44J 44-lead, Plastic J-leaded Chip Carrier (PLCC)

3039I–CNFG–2/05 AT17F040/080 19. Packaging Information 19.1 8CN4 – LAP

2325 Orchard Parkway

San Jose, CA 95131 TITLE DRAWING NO. R REV. 8CN4, 8-lead (6 x 6 x 1.04 mm Body), Lead Pitch 1.27 mm, Leadless Array Package (LAP) A 8CN4 11/14/01 Pin1 Corner Marked Pin1 Indentifier 0.10 mm TYP Top View L b e Side View A Bottom View E D COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A 0.94 1.04 1.14 0.30 0.34 0.38 b 0.45 0.50 0.55 D 5.89 5.99 6.09 E 4.89 5.99 6.09 e

1.27 BSC

1.10 REF

L 0.95 1.00 1.05 1.25 1.30 1.35 Note: 1. Metal Pad Dimensions.

3039I–CNFG–2/05 AT17F040/080 19.2 20J – PLCC San Jose, CA 95131 R TITLE DRAWING NO. REV. Notes: 1. This package conforms to JEDEC reference MS-018, Variation AA. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. Lead coplanarity is 0.004" (0.102 mm) maximum. A 4.191 4.572 2.286 3.048 0.508 D 9.779 10.033 8.890 9.042 Note 2 E 9.779 10.033 8.890 9.042 Note 2 D2/E2 7.366 8.382 B 0.660 0.813 0.330 0.533 e

1.270 TYP

(Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE 1.14(0.045) X 45˚ PIN NO. 1 IDENTIFIER 1.14(0.045) X 45˚ 0.51(0.020)MAX 0.318(0.0125) 0.191(0.0075) 45˚ MAX (3X) A D2/E2 B e E D 20J, 20-lead, Plastic J-leaded Chip Carrier (PLCC) B 20J 10/04/01

3039I–CNFG–2/05 AT17F040/080 19.3 44A – TQFP San Jose, CA 95131 TITLE DRAWING NO. R REV. 44A, 44-lead, 10 x 10 mm Body Size, 1.0 mm Body Thickness, 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) B 44A 10/5/2001 PIN 1 IDENTIFIER 0˚~7˚ PIN 1 L C A D e E B COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE Notes: 1. This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum. A 1.20 0.05 0.15 0.95 1.00 1.05 D 11.75 12.00 12.25 9.90 10.00 10.10 Note 2 E 11.75 12.00 12.25 9.90 10.00 10.10 Note 2 B 0.30 0.45 C 0.09 0.20 L 0.45 0.75 e

0.80 TYP

3039I–CNFG–2/05 AT17F040/080 19.4 44J – PLCC Notes: 1. This package conforms to JEDEC reference MS-018, Variation AC. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. Lead coplanarity is 0.004" (0.102 mm) maximum. A 4.191 4.572 2.286 3.048 0.508 D 17.399 17.653 16.510 16.662 Note 2 E 17.399 17.653 16.510 16.662 Note 2 D2/E2 14.986 16.002 B 0.660 0.813 0.330 0.533 e (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE 1.14(0.045) X 45˚ PIN NO. 1 IDENTIFIER 1.14(0.045) X 45˚ 0.51(0.020)MAX 0.318(0.0125) 0.191(0.0075) 45˚ MAX (3X) A D2/E2 B e E D 44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC) B 44J 10/04/01 San Jose, CA 95131 TITLE DRAWING NO. R REV.

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