AT17C65

AT17C65 ATMEL | Alldatasheet

Document overview

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Technical content

Features

• E2 Programmable 65,536 x 1, 131,072 x 1, and 262,144 x 1 bit Serial Memories Designed To Store Configuration Programs For Programmable Gate Arrays
• Simple Interface to SRAM FPGAs Requires Only One User I/O Pin
• Compatible With AT6000 FPGAs, ATT3000 FPGA, EPF8000 FPGAs, ORCA FPGAs, XC2000, XC3000, XC4000, XC5000 FPGAs, MPA1000
• Cascadable To Support Additional Configurations or Future Higher-density Arrays (17C128 and 17C256 only)
• Low-power CMOS EEPROM Process
• Programmable Reset Polarity
• Available In the Space-efficient Plastic DIP or Surface-mount PLCC and SOIC Packages
• In-System Programmable Via 2-Wire Bus
• Emulation of 24CXX Serial EPROMs
• Available in 3.3V ± 10% LV Version

Description

The AT17C65/128/256 and AT17LV65/128/256 (AT17 Series) FPGA Configuration EEPROMS (Configurator) provide an easy-to-use, cost-effective configuration mem- ory for Field Programmable Gate Arrays. The AT17 Series is packaged in the 8-pin DIP and the popular 20-pin PLCC and SOIC. The AT17 Series family uses a simple serial-access procedure to configure one or more FPGA devices. The AT17 Series organization supplies enough memory to configure one or multiple smaller FPGAs. Using a special feature of the AT17 Series, the user can select the polarity of the reset function by programming a special EEPROM bit. The AT17 Series can be programmed with industry standard programmers. 0391E-A–5/97 FPGA Configuration E 2PROM 65K, 128K and 256K AT17C65 AT17C128 AT17C256

Controlling The AT17 Series Serial EEPROMs Most connections between the FPGA device and the Serial EEPROM are simple and self-explanatory.

• The DATA output of the AT17 Series drives DIN of the FPGA devices.
• The master FPGA CCLK output drives the CLK input of the AT17 Series.
• T h e C E O output of any AT17C/LV128/256 drives the CE input of the next AT17C/LV128/256 in a cascade chain of PROMs.
• S E R _ E N must be connected to VCC . There are, however, two different ways to use the inputs CE and OE, as shown in the AC Characteristics wave- forms. Condition 1 The simplest connection is to have the FPGA D/P output drive both CE and RESET/OE in parallel (Figure 1). Due to its simplicity, however, this method will fail if the FPGA receives an external reset condition during the configura- tion cycle. If a system reset is applied to the FPGA, it will abort the original configuration and then reset itself for a new configuration, as intended. Of course, the AT17 Series does not see the external reset signal and will not reset its internal address counters and, consequently, will remain out of sync with the FPGA for the remainder of the configu- ration cycle. Condition 2 The FPGA D/P output drives only the CE input of the AT17 Series, while its OE input is driven by the inversion of the input to the FPGA RESET input pin. This connection works under all normal circumstances, even when the user aborts a configuration before D/P has gone High. A High level on the RESET/OE input to the AT17C/LVxxx – during FPGA reset – clears the Configurator's internal address pointer, so that the reconfiguration starts at the beginning. The AT17 Series does not require an inverter since the RESET polarity is programmable.Block Diagram

Pin Pin Name I/O Description 2 1 DATA I/O Three-state DATA output for reading. Input/Output pin for programming. 42 C L K I Clock input. Used to increment the internal address and bit counter for reading and programming.

63 R E S E T / O E

RESET/Output Enable input (when SER_EN is High). A Low level on both the CE and RESET/OE inputs enables the data output driver. A High level on RESET/OE resets both the addresss and bit counters. A logic polarity of this input is programmable as either RESET/OE or RESET/OE. This document describes the pin as RESET/OE. 84 C E I Chip Enable input. Used for device selection. A Low level on both CE and OE enables the data output driver. A High level on CE disables both the address and bit counters and forces te device into a low power mode. Note this pin will not enable/disable the device in 2-wire Serial mode (ie; when SER_EN is Low). 10 5 GND Ground Pin 14 6 CEO O Chip Enable Out output. This signal is asserted Low on the clock cycle following the last bit read from the memory. It will stay Low as long as CE and OE are both Low. It will then follow CE until OE goes High. Thereafter CEO will stay High until the entire PROM is read again and senses the status of RESET polarity. A2 I Device selection input, A2. This is used to enable (or select) the device during programming and when SER_EN is Low (see Programming Guide for more details). 17 7 SER_EN I Serial enable is normally high during FPGA loading operations. Bringing SER_EN low, enables the 2-wire serial interface for programming. 20 8 V CC +3.3V/+5V power supply pin. Absolute Maximum Ratings* Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Voltage on Any Pin ESD (R

designed for compatibility with the Master Serial Mode. Figure 1. Condition 1 Connection the RESET/OE on each Configurator Active. tion. The AT17C Series parts are read/write at 5V nominal. The AT17LV parts are read/write at 3.0V nominal.

VCC = 5V ± 5% Commercial / 5V ± 10% Ind./Mil. Symbol Description Min Max Units VIH High-level input voltage 2.0 V CC V VIL Low-level input voltage 00 . 8V VOH High-level output voltage (IOH = -4 mA) Commercial 3.7 V VOL Low-level output voltage (IOL = +4 mA) 0.32 V VOH High-level output voltage (IOH = -4 mA) Industrial 3.6 V VOL Low-level output voltage (IOL = +4 mA) 0.37 V VOH High-level output voltage (IOH = -4 mA) Military 3.5 V VOL Low-level output voltage (IOL = +4 mA) 0.4 V ICCA Supply current, active mode 10 mA IL Input or output leakage current (VIN = VCC or GND) -10 10 µA ICCS Supply current, standby mode AT17C256 Commercial 75 µA Industrial/Military 150 µA Supply current, standby mode AT17C128/65 Commercial 1 mA Industrial/Military 2 mA DC Characteristics VCC = 3.3V ± 10% Symbol Description Min Max Units VIH High-level input voltage 2.0 V CC V VIL Low-level input voltage 00 . 8V VOH High-level output voltage (IOH = -2.5 mA) Commercial 2.4 V VOL Low-level output voltage (IOL = +3 mA) 0.4 V VOH High-level output voltage (IOH = -2 mA) Industrial 2.4 V VOL Low-level output voltage (IOL = +3 mA) 0.4 V VOH High-level output voltage (IOH = -2 mA) Military 2.4 V VOL Low-level output voltage (IOL = +2.5 mA) 0.4 V ICCA Supply current, active mode 5m A IL Input or output leakage current (VIN = VCC or GND) -10 10 µA ICCS Supply current, standby mode Commercial 50 µA Industrial/Military 100 µA

AC Characteristics When Cascading

AC Characteristics for AT17C256 VCC = 5V ± 5% Commercial / VCC = 5V ± 10% Ind./Mil. Symbol Description Commercial Industrial/Military UnitsMin Max Min Max TOE (2) OE to Data Delay 25 25 ns TCE (2) CE to Data Delay 45 45 ns TCAC (2) CLK to Data Delay 50 55 ns TOH (2) Data Hold From CE, OE, or CLK 0 0 ns TDF (3) CE or OE to Data Float Delay 50 50 ns TLC CLK Low Time 20 20 ns THC CLK High Time 20 20 ns TSCE CE Setup Time to CLK (to guarantee proper counting) 35 40 ns THCE CE Hold Time to CLk (to guarantee proper counting) 0 0 ns THOE OE High Time (guarantees counter is reset) 20 20 ns FMAX MAX Input Clock Frequency 12.5 12.5 MHz AC Characteristics for AT17C256 When Cascading VCC = 5V± 5% Commercial / VCC = 5V ± 10% Ind./Mil. Notes: 1. Preliminary specifications for military operating range only. 2. AC test load = 50 pf. 3. Float delays are measured with 5 pF AC loads. Transition is measured ±200 mV from steady state active levels. Symbol Description Commercial Industrial/Military UnitsMin Max Min Max TCDF (3) CLK to Data Float Delay 50 50 ns TOCK (2) CLK to CEO Delay 35 40 ns TOCE (2) CE to CEO Delay 35 35 ns TOOE (2) RESET/OE to CEO Delay 30 35 ns

AC Characteristics for AT17C65/128 VCC = 5V ± 5% Commercial / VCC = 5V ± 10% Ind./Mil. Symbol Description Commercial Industrial/Military UnitsMin Max Min Max TOE (2) OE to Data Delay 110 150 ns TCE (2) CE to Data Delay 50 50 ns TCAC (2) CLK to Data Delay 50 55 ns TOH (2) Data Hold From CE, OE, or CLK 0 0 ns TDF (3) CE or OE to Data Float Delay 50 50 ns TLC CLK Low Time 30 35 ns THC CLK High Time 30 35 ns TSCE CE Setup Time to CLK (to guarantee proper counting) 45 50 ns THCE CE Hold Time to CLk (to guarantee proper counting) 0 5 ns THOE OE High Time (guarantees counter is reset) 50 60 ns FMAX (4) MAX Input Clock Frequency 10 10 MHz AC Characteristics for AT17C65/128 When Cascading VCC = 5V± 5% Commercial / VCC = 5V ± 10% Ind./Mil. Notes: 1. Preliminary specifications for military operating range only. 2. AC test load = 50 pf. 3. Float delays are measured with 5 pF AC loads. Transition is measured ±200 mV from steady state active levels. 4. During cascade F MAX = 8 MHz. Symbol Description Commercial Industrial/Military UnitsMin Max Min Max TCDF (3) CLK to Data Float Delay 50 50 ns TOCK (2) CLK to CEO Delay 65 75 ns TOCE (2) CE to CEO Delay 55 60 ns TOE (2) RESET/OE to CEO Delay 55 55 ns

VCC = 3.3V ± 10% Notes: 1. Preliminary specifications for military operating range only. 2. AC test lead = 50 pf. 3. Float delays are measured with 5 pF AC loads. Transition is measured ±200 mV afrom steady state active levels. 4. During cascade F MAX = 8 MHz. Symbol Description Commercial Industrial/Military UnitsMin Max Min Max TOE (2) OE to Data Delay 40 45 ns TCE (2) CE to Data Delay 60 60 ns TCAC (2) CLK to Data Delay 75 80 ns TOH (2) Data Hold From CE, OE, or CLK 0 0 ns TDF (3) CE or OE to Data Float Delay 55 55 ns TLC CLK Low Time 25 25 ns THC CLK High Time 25 25 ns TSCE CE Setup Time to CLK (to guarantee proper counting) 35 60 ns THCE CE Hold Time to CLk (to guarantee proper counting) 0 0 ns THOE OE High Time (guarantees counter is reset) 25 25 ns FMAX (4) MAX Input Clock Frequency 10 8 10 MHz AC Characteristics When Cascading VCC = 3.3V ± 10% Symbol Description Commercial Industrial/Military UnitsMin Max Min Max TCDF (3) CLK to Data Float Delay 60 60 ns TOCK (2) CLK to CEO Delay 55 60 ns TOCE (2) CE to CEO Delay 55 60 ns TOOE (2) RESET/OE to CEO Delay 40 45 ns

Ordering Information - 5V Devices Memory Size (K) Ordering Code Package Operation Range 64K AT17C65-10PC AT17C65-10JC AT17C65-10SC 8P3 20J 20S Commercial (0°C to 70°C) AT17C65-10PI AT17C65-10JI AT17C65-10SI 8P3 20J 20S Industrial (-40°C to 85°C) 128K AT17C128-10PC AT17C128-10JC AT17C128-10SC 8P3 20J 20S Commercial (0°C to 70°C) AT17C128-10PI AT17C128-10JI AT17C128-10SI 8P3 20J 20S Industrial (-40°C to 85°C) 256K AT17C256-10PC AT17C256-10JC AT17C256-10SC 8P3 20J 20S Commercial (0°C to 70°C) AT17C256-10PI AT17C256-10JI AT17C256-10SI 8P3 20J 20S Industrial (-40°C to 85°C) Ordering Information - 3.3V Devices Memory Size (K) Ordering Code Package Operation Range 64K AT17LV65-10PC AT17LV65-10JC AT17LV65-10SC 8P3 20J 20S Commercial (0°C to 70°C) AT17LV65-10PI AT17LV65-10JI AT17LV65-10SI 8P3 20J 20S Industrial (-40°C to 85°C) 128K AT17LV128-10PC AT17LV128-10JC AT17LV128-10SC 8P3 20J 20S Commercial (0°C to 70°C) AT17LV128-10PI AT17LV128-10JI AT17LV128-10SI 8P3 20J 20S Industrial (-40°C to 85°C) 256K AT17LV256-10PC AT17LV256-10JC AT17LV256-10SC 8P3 20J 20S Commercial (0°C to 70°C) AT17LV256-10PI AT17LV256-10JI AT17LV256-10SI 8P3 20J 20S Industrial (-40°C to 85°C) Package Type 8P3 8-Lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 20J 20-Lead, Plastic J-Leaded Chip Carrier (PLCC) 20S 20-Lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC)