AT1731A

AT1731A AIMTRON | Alldatasheet

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Technical content

Preliminary Product Information DC-DC Power IC for TFT Panel Tel: 886-3-563-0878 Fax: 886-3-563-0879 WWW: http://www.aimtron.com.tw 2/8/2006 REV:1.1 Email: service@aimtron.com.tw Feature

• 2.6V to 5.5V Supply Voltage Operating Range.
• 1.2MHz Fixed Switching Frequency.
• Current-Mode PWM Step-Up Regulator Main High-Power Output up to 15V Typical ± 1% Accuracy Built-In N-MOS, Rds(on)≒0.25Ω(Typ.) Current-Limit Comparator
• Negative Charge-Pump Output Voltage Down to –30 V.
• Positive Charge-Pump Output Voltage Up to 30 V.
• Internal Power-On Sequencing , Soft-Start.
• Thermal Protection , Short Circuit Protection.
• 1uA Shutdown Current.
• 1.5mA Quiescent Current.
• 16-pin TSSOP Package. Application
• TFT-LCD Notebook Display
• TFT-LCD Desktop Monitor Panels.
• Car Navigation Systems.

Description

The AT1731A DC-DC converter supply a compact and small power supply solution to provide the regulated voltages required by thin film transistor (TFT) LCD display. A built-in power sequence control. The main step-up DC-DC converter is a high-Frequency 1.2 MHz current-mode PWM regulator with a built-in 0.25ΩN-MOS that allows the use of ultra-small inductors and ceramic capacitor to generate an externally set output voltage up to 15V. It provides fast transient response to pulsed loads while operating with efficiencies over 85%. The two built-in charge-pump regulators are used to generate the TFT gate-on and gate-off supplies and can adjust gate-on and gate-off output voltage with external resistive divider between gate-off/on output voltage and ground. AT1731A is available in TSSOP- 16 package. Block Diagram Logic Control Block Negative Charge-Pump Block Positive Charge-Pump Block Main Step-Up Converter Block Under-Voltage Lockout Soft- Start Thermal Protection Short-Circuit Protection Vin GND SCP LX PGND Reference Voltage REF FB /SHDN VDDN FBN SWN VDDP FBP SWP COMP SS Aimtron reserves the right without notice to change this circuitry and specifications.

Preliminary Product Information DC-DC Power IC for TFT Panel Tel: 886-3-563-0878 Fax: 886-3-563-0879 WWW: http://www.aimtron.com.tw 2/8/2006 REV:1.1 Email: service@aimtron.com.tw Pin Configurations SHDN Vin FB COMP VDDN LX FBN SWP PGND VDDP REF SCP GND SWN SS FBP

Ordering Information

AT1731AP_GRE TSSOP-16 , Green , Date code with one bottom line : Date Code *For more marking information, contact our sales representative directly Pin Description Pin N0. Symbol I / O P Positive Charge-Pump Driver Supply Voltage. Bypass to power ground with 0.1uF capacitor. VDDN P Negative Charge-Pump Driver Supply Voltage. Bypass to power ground with 0.1uF capacitor. LX I Main Step-up Regulator N-MOS Drain. Place output diode and inductor. Vin P Input voltage pin of the device .Vin may range from 2.6V to 5.5V COMP O Compensation pin for the main step-up converter. A series RC is connected to this pin. FB I Main Step-Up Regulator Feedback Input. Connect a resistive divider from main output to FB to analog ground. /SHDN I Active-low shutdown control input. Pull SHDN low to force the controller into shutdown. If unused, connect SHDN to Vin for normal operation. REF O Internal Reference Output. External load capability up to 50uA. GND P Analog Ground. SS I Soft-start input. The capacitor connected to this pin to sets the current-limited start time. FBP I Positive Charge-Pump Regulator Feedback Input. Connect a resistive divider from the positive charge-pump output to FBP to analog ground. SCP I Short Circuit Protection. FBN I Negative Charge-Pump Regulator Feedback Input. Connect a resistive divider from the negative charge-pump output to FBN to the reference. SWN O Negative Charge-Pump Driver Output. Output high level is VDDN and low level is PGND. SWP O Positive Charge-Pump Driver Output. Output high level is VDDP and low level is PGND. PGND P Power Ground.

Preliminary Product Information DC-DC Power IC for TFT Panel Tel: 886-3-563-0878 Fax: 886-3-563-0879 WWW: http://www.aimtron.com.tw 2/8/2006 REV:1.1 Email: service@aimtron.com.tw Absolute Maximum Ratings *1 Parameter Rated Value unit Vin , SHDN , SS Voltage V LX , SWP , SWN Voltage +18 V COMP, REF, FB, FBN, FBP voltage Vin + 0.3 V Quiescent Current 2.5 mA Continuous power dissipation (TSSOP-16,Ta=+70OC) 650 mW Junction Temperature 150 Lead Temperature (Soldering 10 sec) 260 Storage Temperature -40~150 HBM KV ESD Susceptibility *2 MM 200 V 1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. Device are ESD sensitive. Handling precaution recommended. The Human Body model is a 100pF capacitor discharged through a 1.5KΩ resistor into each pin. Recommended Operation Conditions Values Parameter Symbol Min. Typ. Max. Unit Power supply voltage Vcc 2.6 5.5 V Operating temperature Top -30 +25 +85

Preliminary Product Information DC-DC Power IC for TFT Panel Tel: 886-3-563-0878 Fax: 886-3-563-0879 WWW: http://www.aimtron.com.tw 2/8/2006 REV:1.1 Email: service@aimtron.com.tw

Electrical Characteristics

(Vin=3.0V, SHDN=Vin, VDDP=VDDN=10V, Ta=+25℃, unless otherwise noted) Parameter Symbol Test Condition Min. Typ. Max Units Input operating voltage Vin 2.6 5.5 V Input under-voltage threshold VUVLO Vin Rising 2.45 2.5 2.55 V Vin UVLO hysteresis 120 mV Vin Quiescent Current Iin VFB=VFBP=1.23V, VFBN= - 0.2V 1.5 mA Vin Shutdown Current ISHDN SHDN=GND uA VDDP Quiescent Current IVDDP VFBP=1.5V 0.5 0.8 mA VDDP Shutdown Current SHDN=GND, VDDP=15V uA VDDN Quiescent Current IVDDN VFBN= - 0.2V 0.5 0.8 mA VDDN Shutdown Current SHDN=GND, VDDN=15V uA Main Step-Up Converter Main Output Voltage Range VMAIN Vin V Feedback Regulation voltage VFB Ta=+25℃ 1.21 1.23 1.24 V FB Input Bias Current IFB VFB=1.23V -50 nA Operating Frequency fOSC Ta=+25℃ 1.1 1.2 1.3 MHz Oscillator Maximum Duty Cycle Load Regulation 0 mA<ILX<300 mA 0.2 Line Regulation 2.6V < Vin < 5.5V 0.1 %/V Trans-conductance 317 us LX Switch On-Resistance RLX-DS(ON ILX=300mA 0.25 0.5 Ω LX Leakage Current ILX VLX=15V 0.1 uA LX Current Limit ILIM Vin=3.3V 2.0 2.2 2.5 A Maximum RMS LX Current 1.87 A Current Iss uA Soft-Start Reset switch resistance RSS 100 Ω Short- circuit Capacitor charge current 1.0 uA Negative Charge-Pump VDDN Input Supply Range VDDN Vin V Operating Frequency fCHN 0.5 x fOSC Hz FBN Feedback Regulation Voltage VFBN -50 +50 mV FBN Input Bias Current IFBN VFBN=0V -50 +50 nA P-ch On-Resistance RPCH-DS (ON) Ω VFBN=+50mV Ω N-ch On-Resistance RNCH-DS (ON) VFBN=-50mV KΩ Maximum RMS SWN Current mA Positive Charge-Pump VDDP Input Supply Range VDDP Vin V Operating Frequency fCHP 0.5 x fOSC Hz FBP Feedback Regulation Voltage VFBP 1.21 1.23 1.24 V FBP Input Bias Current IFBP VFBP=1.23V -50 +50 nA P-ch On-Resistance RPCH-DS( Ω

Preliminary Product Information DC-DC Power IC for TFT Panel Tel: 886-3-563-0878 Fax: 886-3-563-0879 WWW: http://www.aimtron.com.tw 2/8/2006 REV:1.1 Email: service@aimtron.com.tw ON) VFBP=1.2V Ω N-ch On-Resistance RNCH-DS( ON) VFBP=1.24V KΩ Maximum RMS SWP Current mA Reference Reference Voltage VREF -2uA <IREF <50uA 1.21 1.23 1.24 V Reference Under-voltage Threshold 0.9 1.06 1.16 V Logic Signals SHDN input low voltage 0.4V hysteresis 0.9 V SHDN input high voltage 2.1 V SHDN input current ISHDN 0.01 uA Thermal Shutdown 160

Preliminary Product Information DC-DC Power IC for TFT Panel Tel: 886-3-563-0878 Fax: 886-3-563-0879 WWW: http://www.aimtron.com.tw 2/8/2006 REV:1.1 Email: service@aimtron.com.tw Typical Operating Characteristics Load-Transient Response Vin=3.3V, Vmain=10V Main Boost Step-Up waveform with Load CH1:VMAIN, CH3:ILX, CH4:IMAIN CH1:SHDN, Ch2:VMAIN, CH3:ILX, CH4:IMAIN IMAIN=200mA to 2mA IMAIN=300mA Power-Up Sequence Power-Up Sequence CH1: VMAIN, Ch2: VPOS, CH3: SHDN, CH4:VNEG CH1:VMAIN, CH2: Soft-Start, CH3: VPOS, Ch4: VNEG IMAIN=300mA,INEG=20mA,IPOS=20mA IMAIN=300mA,INEG=20mA,IPOS=20mA

Preliminary Product Information DC-DC Power IC for TFT Panel Tel: 886-3-563-0878 Fax: 886-3-563-0879 WWW: http://www.aimtron.com.tw 2/8/2006 REV:1.1 Email: service@aimtron.com.tw Ripple Waveform CH1:VMAIN, CH2:VPOS, CH3:VNEG, IMAIN=300mA, INEG=20mA,IPOS=20mA EFFICIENCY vs. LOAD CURRENT (BOOST CONVERTER AND CHARGE PUMPS) 100 100 300 Imain (mA) EFFICIENCY (%) Vin=5.0V Vin=3.3V Vin=2.7V

Preliminary Product Information DC-DC Power IC for TFT Panel Tel: 886-3-563-0878 Fax: 886-3-563-0879 WWW: http://www.aimtron.com.tw 2/8/2006 REV:1.1 Email: service@aimtron.com.tw MAIN STEP-UP CONVERTER EFFICIENCY vs. LOAD CURRENT (BOOST ONLY) 100 300 IMAIN (mA) EFFICIENCY (%) Vin=5.0V Vin=3.3V Vin=2.7V SWITCHING FREQUENCY vs. INPUT VOLTAGE 1.18 1.19 1.2 1.21 1.22 1.23 1.24 1.25 2.5 2.8 3.5 4.5 5.5 INPUT VOLTAGE (V) SWITCHING FREQUENCY (MHz)

Preliminary Product Information DC-DC Power IC for TFT Panel Tel: 886-3-563-0878 Fax: 886-3-563-0879 WWW: http://www.aimtron.com.tw 2/8/2006 REV:1.1 Email: service@aimtron.com.tw REFERENCE VOLTAGE vs. REFERENCE LOAD CURRENT 1.222 1.223 1.224 1.225 1.226 1.227 1.228 1.229 1.23 IREF (uA) VREF (V) REFERENCE VOLTAGE vs. TEMPERATURE 1.223 1.224 1.225 1.226 1.227 1.228 1.229 1.23 1.231 1.232 1.233 -20 -10 TEMPERATURE (oC) VREF (V)

Preliminary Product Information DC-DC Power IC for TFT Panel Tel: 886-3-563-0878 Fax: 886-3-563-0879 WWW: http://www.aimtron.com.tw 2/8/2006 REV:1.1 Email: service@aimtron.com.tw SWITCHING FREQUENCY vs. TEMPERATURE 1.05 1.1 1.15 1.2 1.25 1.3 -20 -10 TEMPERATURE (oC) SWITCHING FREQUENCY (MHz

Figure 1. Standard Application Circuit

Preliminary Product Information DC-DC Power IC for TFT Panel Tel: 886-3-563-0878 Fax: 886-3-563-0879 WWW: http://www.aimtron.com.tw 2/8/2006 REV:1.1 Email: service@aimtron.com.tw forces the current through the inductor to ramp back down , transferring the energy stored in the magnetic field to the output capacitor and load. To add higher flexibility to the selection of external component values, the device uses external loop compensation. Negative Charge-Pump Regulator Negative charge-pump contains internal P-channel and N-channel MOSFETs to perform the power transfer. The internal MOSFETs switch at a constant 600kHz (0.5x fOSC). The charge-pump inverts the supply voltage (VDDN) and provides a regulated negative output voltage. Figure 3 shows charge-pump block diagram. During the first half-cycle, the P-channel MOSFET turns on and flying capacitor CCPN charges to VDDN minus a diode drop. During the second half-cycle, the P-channel MOSFET turns off, and the N-channel MOSFET turns on, level shifting CCPN. This connects CCPN in parallel with the reservoir capacitor CNEG. If the voltage across CNEG minus a diode drop is lower than the voltage across CCPN, charge flows from CCPN to CNEG until the diode turns off. The amount of charge transferred to the output is controlled by the variable N-channel on-resistance. Positive Charge-Pump Regulator Positive charge-pump also contains internal P-channel and N-channel MOSFETs to perform the power transfer. The internal MOSFETs switch at a constant 600kHz (0.5x fOSC). The charge-pump inverts the doubles supply voltage (VDDP) and provides a regulated positive output voltage. During the first half-cycle, the N-channel MOSFET turns on and flying capacitor CCPP charges to VDDP minus a diode drop. During the second half-cycle, the N-channel MOSFET turns off, and the P-channel MOSFET turns on, level shifting CCPP by VDDP volts. This connects CCPP in series with the reservoir capacitor CPOS. If the voltage across CPOS plus a diode drop is lower than the level shifted flying capacitor voltage (VCPP+VDDP), charge flows from CCPP to CPOS until the diode turns off. The amount of charge transferred to the output is controlled by the variable N-channel on-resistance. CPP Cout Cout FBN SWN R10 REF V 1.23V R11 NEG C NEG V CPN C Switch Block FBP 1.23V C SWP DDN Vmain V DDP V POS CPOS V VDDP Driver Driver V POS =(1+R3/R4)x VREF VREF =1.23V V V V = -(R10/R11)x NEG =1.23V REF REF

Preliminary Product Information DC-DC Power IC for TFT Panel Tel: 886-3-563-0878 Fax: 886-3-563-0879 WWW: http://www.aimtron.com.tw 2/8/2006 REV:1.1 Email: service@aimtron.com.tw rising rate of output voltage. Short-Circuit Protection If feedback voltage of the main regulator falls below 0.8V, positive charge-pump falls below 1.1V and negative charge-pump falls below 130mV , the built-in constant current will charge external capacitor CSCP . If VSCP reaches 0.8V ,the ready pin goes high impedance and all outputs shut down.; however , the reference remains active. When short- circuit problem is to eliminate, toggle shutdown or cycle the input voltage to clear the fault latch . Voltage Reference The voltage at REF is nominally 1.23V. The reference can source up to 50uA with good regulation. Connect a 0.22uF bypass capacitor between REF and GND. Thermal-Overload Protection Thermal-overload protection limits total power dissipation in the AT1731A. When the junction temperature exceeds Tj=160 ℃, a thermal sensor activates the thermal protection, which shuts down the IC, allowing the IC to cool. Once the device cools down by 15 ℃, IC will automatically recover normal operation. For continuous operation , do not exceed the absolute maximum junction-temperature rating of Tj=150 ℃. Power dissipation consideration The AT1731A maximum power dissipation depends on the thermal resistance of the IC package and circuit board, the temperature difference between the die junction and ambient air, and the rate of any airflow. The power dissipation in the device depends on the operating conditions of each regulator. The step-up converter dissipates power across the internal N-MOS as the controller ramps up the inductor current. In continuous condition, the power dissipated internally can be approximated by : D R L f D V V V I P ON DS OSC in in MAIN MAIN boost MAIN where IMAIN : It includes the primary load current and the input supply current for the charge-pumps. The charge-pumps provide regulated output voltages by dissipating power in the low-side N-MOS, so they could be modeled as linear regulators followed by unregulated charge-pumps. Therefore, their power dissipation is similar to a linear regulator : OUT POS DIODE DDP POS POS OUT NEG DIODE DDN NEG NEG V N V V I P V N V V I P

Preliminary Product Information DC-DC Power IC for TFT Panel Tel: 886-3-563-0878 Fax: 886-3-563-0879 WWW: http://www.aimtron.com.tw 2/8/2006 REV:1.1 Email: service@aimtron.com.tw Where N : It is the number of charge-pump stages. VDIODE : diodes’ forward voltage To find the total power dissipated in the device, the power dissipated by each regulator and the buffer must be added together : POS NEG boost MAIN total P P P P The maximum allowed power dissipation is around 650 mW (16-pin TSSOP) BA JB A MAX j MAX T T P θ θ Where : Tj - TA : It is the temperature difference between the IC’s junction and the surrounding air. ΘJB : the thermal resistance of the package to the board ΘBA : the thermal resistance from the PCB to the surrounding air.

Preliminary Product Information DC-DC Power IC for TFT Panel Tel: 886-3-563-0878 Fax: 886-3-563-0879 WWW: http://www.aimtron.com.tw 2/8/2006 REV:1.1 Email: service@aimtron.com.tw Applications Information External components of main boost converter can be designed by performing simple calculations. It need to follow regulation by the output voltage and the maximum load current, as well as maximum and minimum input voltages. Begin by selecting an inductor value. Once L is know, choose the diode and capacitors. Boost inductor Inductor selection depends on input voltage, output voltage , maximum current , switching frequency and availability of inductor values. The following boost circuit equations are useful in choosing the inductor values based on the application. They allow the trading of peak current and inductor value while allowing for consideration of component availability and cost. The peak inductor current is given by: D I I I I I MAIN LAVG L LAVG Lpeak where: △IL is the inductor peak-to-peak current ripple and is decided by: OSC in L f D L V I D is the MOSFET turn on ratio and is decided by: O in O V V V D fOSC is the switching frequency. The inductor should be chosen to be able to handle this current and inductor saturation current rating should be greater than IPEAK. Diode selection The output diode has average current of IMAIN, and peak current the same as the inductor’s peak current and a voltage rating at least 1.5 times the main output voltage. Schottky diode is recommended and it should be able to handle those current. Feedback Resistor Network An external resistor divider is required to divide the output voltage down to the nominal reference voltage. Current drawn by the resistor network should be limited to maintain the overall converter efficiency . The maximum value of the resistor network is limited by the

Preliminary Product Information DC-DC Power IC for TFT Panel Tel: 886-3-563-0878 Fax: 886-3-563-0879 WWW: http://www.aimtron.com.tw 2/8/2006 REV:1.1 Email: service@aimtron.com.tw feedback input bias current and the potential for noise being coupled into the feedback pin. A resistor network in the order of 200kΩ is recommended. The boost converter output voltage is determined by the following relationship: R R V V REF MAIN where VREF =1.23V as specified. Output Capacitor The AT1731A is specially compensated to be stable with capacitors which have a worst- case minimum value of 10uF at the particular VMAIN being set. Output ripple voltage requirements also determine the minimum value and type of capacitors. Output ripple voltage consists of two components the voltage drop caused by the switching current through the ESR of the output capacitor and the charging and discharging of the output capacitor: OSC OUT MAIN MAIN in MAIN LPEAK RIPPLE f C I V V V ESR I V For low ESR ceramic capacitors, the output ripple is dominated by the charging or discharging of the output capacitor. Compensation The Main step-up loop can be compensated by adjusting the external components connected to the COMP pin. The COMP pin is connected to the output of the internal trans-conductance error amplifier. The compensation capacitor adjusts the low frequency gain , and the series resistor value adjusts the high frequency gain. The following formula calculates at what frequency the resistor increases the high frequency gain. C C Z R C f π If the device operates over the entire input voltage range from 2.7V to 5.5V, a larger compensation capacitor up to 18pF is recommended. For a good load transient where no oscillation should occur, 50 KΩis recommended for RC resistor. Positive and Negative Charge Pump The AT1731 contains two independent charge pump. The regulation of both the negative and positive charge pumps is generated by the internal comparator that senses the output voltage and compares it with and internal reference. The switching frequency of the charge pumps is set to 0.5xfOSC. The pumps use pulse width modulation to adjust the pump period, depending on the load present.

Preliminary Product Information DC-DC Power IC for TFT Panel Tel: 886-3-563-0878 Fax: 886-3-563-0879 WWW: http://www.aimtron.com.tw 2/8/2006 REV:1.1 Email: service@aimtron.com.tw Cout FBN SWN R10 REF V 1.23V R11 NEG C NEG V CPN C Switch Block FBP 1.23V SWP DDN Vmain V DDP V C OUT VDDP Driver Driver DL CDL VDDP Vpos triple output C CPP POS C Vpos triple output CCPP Negative and Positive charge pump function diagram Negative Charge Pump Design Consideration For a single stage charge pump, the maximum VNEG output is determined by the following equation: DDN NEG OSC NEG CPN OSC NEG DIODE ON SWNP ON SWNn NEG MAX NEG V C f I C f I V R R I V 5.0 5.0 where: RSWNN(ON) and RSWNP(ON) resistance values depend on the VDDN voltage levels. Positive Charge Pump Design consideration For two stage charge pumps, the maximum VPOS output is determined by the following equation: where: RSWPP(ON) and RSWPN(ON) resistance values depend on the VDDP voltage levels. 5.0 5.0 5.0 5.0 OUT OSC POS CPP OSC POS DIODE DDP POS OSC POS CPP OSC POS DIODE ON SWPP ON SWPN POS DDP MAX POS C f I C f I V V C f I C f I V R R I V V

Preliminary Product Information DC-DC Power IC for TFT Panel Tel: 886-3-563-0878 Fax: 886-3-563-0879 WWW: http://www.aimtron.com.tw 2/8/2006 REV:1.1 Email: service@aimtron.com.tw PCB layout guidelines Careful printed circuit layout is extremely important to avoid causing parasitical capacitance and line inductance. The following layout guidelines are recommended to achieve optimum performance.

• Please the boost converter diode and inductor close to the LX pin and no via.
• Please ceramic bypass capacitors near the charge-pump input pin.
• Locate all feedback resistive dividers as close to their respective feedback pins as possible.
• Separate GND and PGND areas connected at only one point under the IC.
• Use wide traces and trace length is short as possible.

Preliminary Product Information DC-DC Power IC for TFT Panel Tel: 886-3-563-0878 Fax: 886-3-563-0879 WWW: http://www.aimtron.com.tw 2/8/2006 REV:1.1 Email: service@aimtron.com.tw Package Outline TSSOP-16Pin Unit: mm

Preliminary Product Information DC-DC Power IC for TFT Panel Tel: 886-3-563-0878 Fax: 886-3-563-0879 WWW: http://www.aimtron.com.tw 2/8/2006 REV:1.1 Email: service@aimtron.com.tw Reflow Profiles Sn-Pb Eutectic Assembly Pb-Free Assembly Profile Feature Large Body Pkg. thickness ≥2.5mm or Pkg. volume ≥350mm3 Small Body Pkg. thickness <2.5mm or Pkg. volume <350mm3 Large Body Pkg. thickness ≥2.5mm or Pkg. volume ≥350mm3 Small Body Pkg. thickness ≥2.5mm or Pkg. volume ≥350mm3 Average ramp-up rate (TL to TP) 3°C/second max. 3°C/second max. Preheat -Temperature Min(Tsmin) -Temperature Max (Tsmax) -Time (min to max)(ts) 100°C 150°C 60-120 seconds 150°C 200°C 60-180 seconds Tsmax to TL -Ramp-up Rate 3°C/second max. Time maintained above: -Temperature (TL) -Time (tL) 183°C 60-150 seconds 217°C 60-150 seconds Peak Temperature(TP) 225+0/-5°C 240+0/-5°C 245+0/-5°C 250+0/-5°C Time within 5°C of actual Peak Temperature (tP) 10-30 seconds 10-30 seconds 10-30 seconds 20-40 seconds Ramp-down Rate 6°C/second max. 3°C/second max. Time 25°C to Peak Temperature 6 minutes max. 8 minutes max. *All temperatures refer to topside of the package, measured on the package body surface.