AT1362 AIMTRON | Alldatasheet

Document overview

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Technical content

Features

  • Operation Voltage 2.5V~6.0V
  • Oscillation frequency 1MHz
  • Output Current Maximum 400mA（DC-DC Converter）
  • Built-In 400mA/LDO
  • Power Good Indicator with Time Delay Adjustable
  • Built-In Current Limit
  • Built-In UVLO
  • Built-In Thermal ShutDown

Applications

  • Power Supply for Slim Type devices General Description The AT1362A/B provides complete control for a DC/DC converter optimized for high-performance microprocessor applications. It consists of a synchronous step-down DC/DC converter and a high-speed LDO regulator connected in series with the DC/DC converter output. A power good detector and LDO ON/OFF control is also built-in(metal option). DC/DC converter is operated on current mode architecture for excellent line and load transient response. 1MHz operation frequency is allowing the use of small surface mount inductor and capacitor. The internal synchronous switch increases efficiency and eliminates the need for an external schottky diode. The AT1362A/B is a family of low-noise synchronous step-down DC/DC converters that is ideally suited for systems powered form a 1-cell Li-ion battery or from a 3-cell to 4-cell NiCd, NiMH, or alkaline battery. It can also be used to USB-based power system. Block Diagram Current Sense OSC SLOPE R S Q SW Vref VCC PGND Shoot Throught PG DELAY OUT2 OUT1 Vref Current Limit UVLO VREG Vref 0.7V UVLO *OUT1=2.5V/1.8V Metal Option Auto Discharge VCC 0.7 1uA VBG VBG AGND CTL BPC Aimtron reserves the right without notice to change this circuitry and specifications.

Preliminary Product Information Synchronous Buck Converter With Power Good Detector & LDO 7F, No.9, Park Avenue II, Science-Based Industrial Park, Hsinchu 300,Taiwan, R.O.C. Tel: 886-3-563-0878 Fax: 886-3-563-0879 WWW: http://www.aimtron.com.tw 5/30/2006 REV:1.0 Email: service@aimtron.com.tw Pin Assignment AT1362 AT1362A AT1362B DC/DC 2.5V DC/DC 1.8V LDO 3.3V LDO 3.3V DFN10 (TOP VIEW)

Ordering Information

： A:1362AN B:1362BN ： Date Code *For more marking information, contact our sales representative directly. Pin Description Symbol Pin No. Descript PG Power Good Indicator Output(Ative Hi) OUT1 DC/DC Output (2.5V or 1.8V) VCC Power Supply SW DC/DC Inductor Node PGND Power Ground VBG Reference Output Voltage AGND Analog Ground DELAY The capacitor connection terminal for LDO control and PG delay time setup OUT2 LDO Output (3.3V) BPC LDO Input By-pass Capacitor Node Bottom GND Analog Ground Part Number Package Marking 1362N DFN10,Green

Preliminary Product Information Synchronous Buck Converter With Power Good Detector & LDO 7F, No.9, Park Avenue II, Science-Based Industrial Park, Hsinchu 300,Taiwan, R.O.C. Tel: 886-3-563-0878 Fax: 886-3-563-0879 WWW: http://www.aimtron.com.tw 5/30/2006 REV:1.0 Email: service@aimtron.com.tw Absolute Maximum Ratings*1 Rated Value Parameter Symbol Min. Max. Unit Power Supply Voltage VCC -0.3 +6.5 V OUT1, OUT2 -0.3 VCC V Input Pin Voltage SW, PG -0.3 VCC+0.3 V P-Channel Switch Source Current (DC) 0.5 A N-Channel Switch Sink Current (DC) 0.5 A Peak SW Sink and Source Current 0.75 A Thermal Resistance from Junction to Ambient θJA DFN10 35.25 0C/W Thermal Resistance from Junction to Case θJC DFN10 0C/W Operating temperature TA -20 +85 Storage temperature -20 +150 HBM KV ESD Susceptibility*2 MM 200 V 1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. Device are ESD sensitive. Handling precaution recommended. The Human Body model is a 100pF capacitor discharged through a 1.5KΩ resistor into each pin. Recommended Operating Conditions (Ta=+250C) Values Parameter Symbol Min. Typ. Max. Unit Power supply voltage VIN 2.5 6.0 Ｖ Operating temperature* TOP -20 +25 +85 Operating junction temperature TJ +150 *Using X5R or X7R input capacitors.

Preliminary Product Information Synchronous Buck Converter With Power Good Detector & LDO 7F, No.9, Park Avenue II, Science-Based Industrial Park, Hsinchu 300,Taiwan, R.O.C. Tel: 886-3-563-0878 Fax: 886-3-563-0879 WWW: http://www.aimtron.com.tw 5/30/2006 REV:1.0 Email: service@aimtron.com.tw

Electrical Characteristics

(VCC = 3.6V,Ta =+25℃ , unless otherwise noted. ) Values Parameter Symbol Condition Min. Typ. Max. Unit DC/DC CONVERTER VCC UVLO VUV VCC=3V→2V Sweep 2.4 V UVLO Hysteresis width VUVHY 100 mV Input Supply Range VCC 2.5 6.0 V Quiescent Current IS Active Mode 500 µA Output1 Voltage Accuracy VOUT1 Output1 Voltage line-regulation VOUT1-Line VCC=3.5V to 6.0V 0.1 0.5 Output1 Variation with Temperature Ta =-20℃ to +85℃ 0.5 1.0 Feedback current IOUT1 uA Current Limit ICL1 VIN=5V, VOUT1=2.5V/1.8V 0.6 0.7 0.8 A Maximum Output Current IO VIN=5V, VOUT1=2.5V/1.8V, L=4.7uH 400 mA fosc1 Vout1=2.5V/1.8V 0.8 1.0 1.2 MHz Oscillator Frequency fosc2 Vout1=0V 200 KHz RDS(ON) of P-Channel MOSFET RPFET ILX= 300mA 0.3 0.4 Ω RDS(ON) of N-Channel MOSFET RNFET ILX= -300mA 0.25 0.35 Ω SW Leakage Current ISWL ±0.1 µA CONTROL BLOCK PG on voltage VPGON IPG=1mA 0.4 V PG Hysteresis width VPGTHYS mV PG pin leak current IPGTLK VPG=5.0V uA LDO control on Hysteresis width VLDTHYS mV DELAY Pin Charge Current IDELAY 0.8 1.0 1.2 uA LDO Output2 Voltage Accuracy VOUT2 Current Limit ICL2 450 mA Dropout Voltage VDV IOUT2=400mA 400 600 mV Load Regulation ∆VOUT2 IOUT2=1mA→ 100mA mV Line Regulation LR IOUT2=100mA, VOUT1=3.6V→6.0V 0.05 0.25 Ripple Rejection Rate PSRR IOUT2=100mA, f=1kHz dB OUT2 Leakage Current IOUT2LK uA

Preliminary Product Information Synchronous Buck Converter With Power Good Detector & LDO 7F, No.9, Park Avenue II, Science-Based Industrial Park, Hsinchu 300,Taiwan, R.O.C. Tel: 886-3-563-0878 Fax: 886-3-563-0879 WWW: http://www.aimtron.com.tw 5/30/2006 REV:1.0 Email: service@aimtron.com.tw Typical characteristics Efficiency VS. Output1 Current 100 100 1000 Output1 Current(mA) Efficiency(%) L=2.2uH L=3.3uH L=4.7uH L=6.8uH CH1：Vin, CH2：Vout1 CH3：Vout2, CH4：PG CH1：Vout1, CH2：Vout2, CH4：Iout1 Iout1=100mA~300mA, Iout2=200mA Efficiency VS. Output1 Current 100 100 1000 Output1 Current(mA) Efficiency(%) Vin=5.0V Vin=4.2V Vin=3.8V Vin=3.6V CH1：DELAY, CH2：Vout1 CH3：Vout2, CH4：PG CH1：Vout1, CH2：Vout2, CH4：Iout2 Iout1=200mA, Iout2=100mA~300mA Vin=5V Vout1=1.8V Vout1=1.8V L=4.7uH

Preliminary Product Information Synchronous Buck Converter With Power Good Detector & LDO 7F, No.9, Park Avenue II, Science-Based Industrial Park, Hsinchu 300,Taiwan, R.O.C. Tel: 886-3-563-0878 Fax: 886-3-563-0879 WWW: http://www.aimtron.com.tw 5/30/2006 REV:1.0 Email: service@aimtron.com.tw Typical Application Circuits 2.5V 1.8V 3.3V VDELY PG 90% 90% 0.7V 0.7V UVLO Timing of Power-On Sequencing

Preliminary Product Information Synchronous Buck Converter With Power Good Detector & LDO 7F, No.9, Park Avenue II, Science-Based Industrial Park, Hsinchu 300,Taiwan, R.O.C. Tel: 886-3-563-0878 Fax: 886-3-563-0879 WWW: http://www.aimtron.com.tw 5/30/2006 REV:1.0 Email: service@aimtron.com.tw

Application Information

In continuous mode, the source current of the top MOSFET is square wave of duty cycle. The Primary function of the input capacitor is to provide a low impedance loop for the edges of pulsed current drawn by the AT1362A/B. A load step at the output can induce ringing at the input VIN. This ringing can couple to the output and be mistaken as loop instability. The oscillation can be improved by add the capacitance of the input capacitor. A typical value is 10µF ceramic (X5R or X7R), POSCAP or Aluminum Polymer. These capacitors will provide good high frequency bypassing and their low ESR will reduce resistive losses for higher efficiency. The input capacitor RMS current varies with the input voltage and the output voltage. The equation for the maximum RMS current in the input capacitor is: The output capacitor depends on the suitable ripple voltage. Low ripple voltage corresponds to lower effective series resistance (ESR). The output ripple voltage is determined by: The output capacitor RMS ripple current is given by: VBG Capacitor A VBG pin is provided to decouple the bandgap reference voltage. An external capacitor connected form VBG to GND reduces noise present on the internal reference voltage, which in turn significantly reduces output noise and also improves PSRR. Larger capacitor values may be used to further improve PSRR, but result in a longer time period (slower turn on) to settle output voltage when power is initially applied. IN O IN O OMAX RMS V V V V I I OUT L OUT fC ESR I V IN OUT IN OUT RMS V f L V V V I

Preliminary Product Information Synchronous Buck Converter With Power Good Detector & LDO 7F, No.9, Park Avenue II, Science-Based Industrial Park, Hsinchu 300,Taiwan, R.O.C. Tel: 886-3-563-0878 Fax: 886-3-563-0879 WWW: http://www.aimtron.com.tw 5/30/2006 REV:1.0 Email: service@aimtron.com.tw LDO For general purposes, use a 2.2uF capacitor on the LDO output. Larger capacitor values and lower ESR provide better supply noise rejection and transient response. A higher value input capacitor may be necessary if large, fast transients are anticipated . Ceramic capacitors have the lowest ESR, and will offer the best AC performance. When choosing the input and output ceramic capacitors, choose the X5R or X7R dielectric formulations. These dielectrics have the best temperature and voltage characteristics of all the ceramics for a given value and size. Inductor Selection The inductor is chosen based on the desired ripple current. Large value inductors lower ripple current and small value inductors result in higher ripple current. Always consider the losses associated with the DCR and its effect on the total converter efficiency when selecting an inductor. The inductor is selected to limit the ripple current to some predetermined value, typically 20~40% of the full load current at the maximum input voltage. The formula of inductance value is as below: 4.0 2.0 MAX OUT L I I IN OUT L OUT V V I f V L L t V V I I I I ON OUT IN O L O PK Power Good Indicator with Adjustable Time Delay When OUT1 pin is above 2.25V or 1.62V (typ.) and with a delay time (t1) the OUT2 is start to regulation. The PG pin terminal is an open drain output of N-MOS. Connect a resistor from PG pin to VCC or OUT2 to create a logic signal. If OUT2 pin is less and with a delay time (t2) this pin is open. PG pin is forced low when in UVLO. The formula of adjustable delay time is as below: DELAY I V C t t time delay 7.0

Preliminary Product Information Synchronous Buck Converter With Power Good Detector & LDO 7F, No.9, Park Avenue II, Science-Based Industrial Park, Hsinchu 300,Taiwan, R.O.C. Tel: 886-3-563-0878 Fax: 886-3-563-0879 WWW: http://www.aimtron.com.tw 5/30/2006 REV:1.0 Email: service@aimtron.com.tw The Dissipation The power loss is given by: IN s s f r OUT IN N ON DS OUT P ON DS OUT DC DC LOSS V I f t t I V D R I D R I P OUT IN OUT LDO LOSS V V I P LDO LOSS DC DC LOSS JA A MAX J P P T T θ Inductors Surface Mount Inductance(µH) Manufacturer/Part No. Manufacturer Website 3.3 Sumida CDRH4D28-3R3 4.7 Sumida CDRH5D18-4R7 www.sumida.com 3.3 Mitsumi C3-K1.8L-3R3 Mitsumi C4-K1.8L-3R3 www.mitsumi.co.jp 3.3 ABC SH40283R3YSB 4.7 ABC SH40284R7YSB www.atec-group.com Capacitors Surface Mount Capacitance(µF) Manufacturer/Part No. Manufacturer Website TDK C3216X5R0J226M www.tdk.com TDK C3225X5R0J46M www.tdk.com GRM42-6X5R 106K6.3 www.murata.com 2.2 TAIYO LMK212BJ225MD www.t-yuden.com 4.7 TAIYO JMK212BJ475MG www.t-yuden.com

Preliminary Product Information Synchronous Buck Converter With Power Good Detector & LDO 7F, No.9, Park Avenue II, Science-Based Industrial Park, Hsinchu 300,Taiwan, R.O.C. Tel: 886-3-563-0878 Fax: 886-3-563-0879 WWW: http://www.aimtron.com.tw 5/30/2006 REV:1.0 Email: service@aimtron.com.tw PC Board Layout 1. The most critical aspect of the layout is the placement of the input capacitor C2. It must be placed as close as possible to the AT1362A/B to reduce the input ripple voltage. 2. Power loops on the input and output of the converter should be laid out with the shortest and widest traces possible. The longer and narrower the trace, the higher resistance and inductance it will have. The length of traces in series with the capacitors increases its ESR and ESL and reduces their effectiveness at high frequency. 3. The OUT1 pin should connect to C1 directly. And the route should be away from the noise source, such as inductor of SW line. 4. Grounding all components at the same point may effectively reduce the occurrence of loop.

Preliminary Product Information Synchronous Buck Converter With Power Good Detector & LDO 7F, No.9, Park Avenue II, Science-Based Industrial Park, Hsinchu 300,Taiwan, R.O.C. Tel: 886-3-563-0878 Fax: 886-3-563-0879 WWW: http://www.aimtron.com.tw 5/30/2006 REV:1.0 Email: service@aimtron.com.tw

7F, No.9, Park Avenue II, Science-Based Industrial Park, Hsinchu 300,Taiwan, R.O.C. *All temperatures refer to topside of the package, measured on the package body surface. Table 1. SnPb Entectic Process –Package Peak Reflow Temperatures Table 2. Pb-free Process –Package Classification Reflow Temperatures example 260˚С+0˚С) at the rated MSL level.