ASDL-7021

ASDL-7021 LITEON | Alldatasheet

Document overview

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Technical content

Features

• Interfaces with IrDA Compliant IR Transceiver up to VFIR
• Miniature 48 pin TFBGA Package Height : 1.2 mm Width : 4.0 mm Depth : 4.0 mm
• 8-bit Memory Mapped Interface
• Input clock of 48 MHz
• 4 transmission speed in 3 Blocks - SIR Block (2.4 to 115.2Kbps) - FIR Block (1.152Mbps for MIR and 4Mbps for FIR) - VFIR Block (16Mbps)
• Operating temperature from -40° C ~ 85°C - Critical parameters are guaranteed over temperature and supply voltage
• Core Power Supply = 1.8V Clock Power Supply = 3.3V IO Power Supply =1.8V, 2.5V, 3.3V
• RAM Block with On-Chip buffer memory of 8KByte x 2 Bank Configuration - 1 bank for external access x 8 bit width - 1 bank for internal access x 8 bit width through on-chip DMA block - These 2 banks can be switched - Each transmit and receive have their own buffer memory of 8KByte x 2

Description

The ASDL-7021 is a new generation large scale integra - tion (LSI) IrDA controller supporting speeds of SIR (up to 115Kbps), MIR(1.152Mbps), FIR(4Mbps) and VFIR (16Mbps). It consists of IrDA Control Block, Remote Control Block, Timer Control Block, Global Control block including Buffer Memory and Direct Memory Access Control Block (DMA) integrated into one single chip. It has all the hardware including Buffer Memory and Direct Memory Access (DMA) that enables convenient access to its peripheral IO and memories from system bus which is similar to simple memory devices. ASDL-7021 is a class of its own as unlike conventional LSI which utilizes external DMA for implementing fast infrared transfer, complicated bus timing and required additional logic for its interface. ASDL-7021 utilizes two memory banks for external access and internal DMA access; these 2 banks are interchange - able to prevent bus contention. These two banks can be switched using memory select function of the internal register and separates internal bus from external, which enables parallel operation of external microcontroller operation and internal IrDA data transfer operation. ASDL-7021 has embedded Universal Remote Control (RC) function for general purpose remote control communica- tion. Together with Lite-On FIR transceiver and IrSimple software, ASDL-7021 is designed to provide Industry a total solution for high speed wireless connectivity solution in miniature packaging.

Applications

• Mobile Data Communication and Universal Remote Control - Mobile Phones - PDAs - Digital Still Camera - Printer - Notebooks - Handy Terminal - Dongles - Industrial and Medical Instrument BANK1 FIR block CPU DMA BANK0 BANK1 FIR block CPU DMA

Application Support Information The Application Engineering Group is available to assist you with the application design associated with ASDL-7021 FIR/VFIR Controller. You can contact them through your local sales representatives for additional details. Order Information Part Number Packaging Type Quantity ASDL-70 Tape and Reel 4000 I/O Pins Configuration Table Pins Description Symbol Pin(s) Type Buffer Type (Refer to Figure 2) Description Power VDDK C4,C5,C6 POWER .8V Power VDDC C POWER .V Power VIO E4,F5 POWER .8V, .5V, .V VIO D6 POWER .8V, .5V, .V VIO B POWER .8V, .5V, .V GND A,B,C,D,E POWER GND Bus Interface Signals (VIO1 Voltage) A0-A7 D,D,E,E, G,G,F,F I I An 8-bit address signal line connects itself directly with an external address bus. It selects the internal buffer memory and the register addresses of each function module. With the assertion of the CS signal, A0 - A7 turn out to be valid, which decides the internal addresses. D0-D7 G,F,F4,G4 G5,F7,G6,G7 I/O IO4 An 8-bit data signal line connects itself directly with an external data bus. It is a signal that performs data conversion with the internal buffer memory and each function module.The bus direction is determined by WE and OE. /CS F6 I I CS is a chip select signal for the IC. Asserting CS activates the external bus of this LSI. /WE E5 I I The WE signal turns the direction of a data bus to the input direction, and takes it into the IC for the internal buffer memory and registers designated by the address bus, at the start-up of the signal. /OE E6 I I The OE signal turns the data bus direction to the output direction, and outputs to the data bus the contents of the internal buffer memory and register designated by the address bus. /IRQ D7 O O4 This is a signal line that notifies to the outside that ASDL-70 requests an interrupt.

Other Signals (VIO1 Voltage) /RESET D5 I I This RESET signal resets ASDL-70. /SD E7 I I (internal PullDown) . Low: Shutdown IC is suspending the clock supply to the core. The output signal retains the condition. . High: IC is keeping the clock supply to the core. However, when the externally connected quartz crystal is used with CLKSEL=Low, the oscillation of the quartz crystal is kept performed under the condition of CLKSEL=Low, and SD: Low. When you want to stop the quartz crystal oscillation, you must set CLKSEL=High. . After wake up from SD, the IC must be reset. CLKSEL C I I This is used for selecting whether the input signal from CLKIN should be used for the clock input or whether the quartz crystal should be used at XTALIN and XTALOUT. Using quartz crystal, CLKSEL = Low, external quartz crystal is kept under oscillation CLKSEL = High, external quartz crystal is suspending oscillation Using CLKIN signal, set CLKSEL = High Infrared Interface Signal (VIO2 voltage) IrTXD0 B6 O O4 This outputs the IrDA infrared signal and remote control send signal. IrTXD C7 O O4 This outputs the IrDA infrared signal and remote control send signal. IrRXD0 A6 I I This inputs a signal from the infrared module. IrOUT0 B7 O O4 This is an output signal for controlling the infrared module. IrOUT A7 O O4 This is an output signal for controlling the infrared module. Clock Signal (VIO3 voltage) CLKIN B I I Clock input Clock Signal (VDDC Voltage) /XTALIN A I You must connect quartz crystal to create a basic clock or input the clock from outside. Usually you must connect the quartz crystal between XTALIN and XTALOUT. The oscillation frequency of the crystal must be 48MHz. /XTALOUT A O TEST Signal TEST B5 I I (Internal PullDown) Test signal (Set to N.C). TEST A5 I I (Internal PullDown) Test signal (Set to N.C). TEST A4 I I (Internal PullDown) Test signal (Set to N.C). TESTSE B4 I I (Internal PullDown) Test signal (Set to N.C).

Block Name Base Address Offset Register Name IrDA 0x0000 0000h IRBA0R(IR Base Address0 Register) 000h IRBAR(IR Base Address Register) 000h IRBAR(IR Base Address Register) 000h IRRSR(IR Ring Size Register) 0004h IRPLC0R(IR Physical Layer Config0 Register) (unused) 0005h IRPLCR(IR Physical Layer Config Register) (unused) 0006h IRPLCR(IR Physical Layer Config Register) 0007h IRPLCR(IR Physical Layer Config Register) 0008h IRC0R(IR Config0 Register) 0009h IRCR (IR Config Register) 000Ah IRCR (IR Config Register) 000Bh IRCR (IR Config Register)(unused) 000Ch IRE0R(IR Enable0 REG.) 000Dh IRER (IR EnableREG.) 000Eh IRMPL0R(IR Max Packet Length0 REG.) 000Fh IRMPLR (IR Max Packet LengthREG.) 000h IRRP0R(IR Ring Prompt0 REG.) 00h IRRPR (IR Ring Prompt Register REG.) (unused) 00h IRRPR (IR Ring Prompt Register REG.) (unused) 00h IRRPR (IR Ring Prompt Register REG.) (unused) 004h IRRBC0R(IR Receive Byte Count0 REG.) 005h IRRBCR (IR Receive Byte Count REG.) 006h IRRRPR0R(IR Rx Ring Pointer Readback REG.) 007h IRTRPR0R (IR Tx Ring Pointer Readback REG.) 008h IRSF0R(IR SIR Flags0 REG.) 009h IRSFR (IR SIR Flags REG.) 00Ah IRLPC0R(IR Latched Phy Config0 REG.) 00Bh IRLPCR (IR Latched Phy Config REG.) 00Ch IRAC0R(IR Address Compare0 REG.) 00Dh IRACR (IR Address Compare REG.) 00Eh IRACR (IR Address Compare REG.) 00Fh IRACR (IR Address Compare REG.) 000h IRLT0R(IR Latency Timer0 REG.) 00h IRLTR (IR Latency Timer REG.) 00h IRLTR (IR Latency Timer REG.) 00h IRLTR (IR Latency Timer REG.) 004h IRLIV0R(IR LED Indicator and Rx value0 REG.) 005h IRLIVR (IR LED Indicator and Rx value REG.) (unused) 006h IRLIVR (IR LED Indicator and Rx value REG.) (unused) 007h IRLIVR (IR LED Indicator and Rx value REG.) (unused) 008h IRCS0R(IR Clock Speed0 REG.) 009h IRCSR (IR Clock Speed REG.) 00Ah IRCSR (IR Clock Speed REG.) (unused) 00Bh IRCSR (IR Clock Speed REG.) (unused) 00Ch IRPM0R(IR Power management REG.) 00Dh IRPMR (IR Power management REG.) (unused) 00Eh IRPMR (IR Power management REG.) (unused) 00Fh IRPMR (IR Power management REG.) (unused) 000h IRIS0R(Interrupt status read back0 REG.) 00h IRISR (Interrupt status read back REG.) (unused) 00h IRISR (Interrupt status read back REG.) (unused) 00h IRISR (Interrupt status read back REG.) (unused) 004h IRIE0R (Interrupt enable read back0 REG.) 005h IRIER (Interrupt enable read back REG.) (unused) 006h IRIER (Interrupt enable read back REG.) (unused) 007h IRIER (Interrupt enable read back REG.) (unused) Registers Descriptions

Block Name Base Address Offset Register Name IrDA 0x0080 (TXFL FIFO) 0000h TXFL0R(TX Frame Length0 REG.) 000h TXFLR(TX Frame Length REG.) 000h Unused 000h TXSR(TX Status REG.) 0004h TXFA0R(TX Frame Address0 REG.) 0005h TXFAR(TX Frame Address REG.) 0006h TXFAR(TX Frame Address REG.) 0007h TXFAR(TX Frame Address REG.) 0008h TXSIR(TX Status IncrementREG.) 0009h TXFCR(TX Frame Count REG) IrDA 0x0090 (RXFL FIFO) 0000h RXFL0R(RX Frame Length0 REG.) 000h RXFLR(RX Frame Length REG.) 000h Unused 000h RXSR(RX Status REG.) 0004h RXFA0R(RX Frame Address0 REG.) 0005h RXFAR(RX Frame Address REG.) 0006h RXFAR(RX Frame Address REG.) 0007h RXFAR(RX Frame Address REG.) 0008h RXSIR(RX Status IncrementREG.) Global Control 0x00A0 0000h MTDR (Memory Transmit Data REG) Write Only 0000h MRDR(Memory Receive Data REG) Read Only 000h MCR(Memory Control REG.) 000h GISR(Global Interrupt Status REG.) 000h IRSR (IR Select REG.) 0004h IOR(Ir Output REG) 0005h IIR(Ir Input REG) 0006h ISIER(Ir Sir Interupt Enable REG) 0007h ISISR(Ir Sir Interupt Status REG) DMA Control 0x00B0 0000h DMACR(DMA Control REG) Remote Control 0x00C0 0000h RCCCLR(Remote Control Carrier Count Low REG) 000h RCCCHR(Remote Control Carrier Count High REG) 000h RCLLR(Remote Control Length Low REG.) 000h RCLHR(Remote Control Length High REG.) 0004h RCCR(Remote Control Control REG) 0005h RCCRCLR(Remote Control Carrier RX Count Low REG) 0006h RCCRCHR (Remote Control Carrier RX Count High REG) Timer Control 0x00D0 0000h TSSR0(Timer Source Setting REG.0) 000h TIER0(Timer Interrupt Enable REG.0) 000h TCSR0(Timer Contorol Status REG.0) 000h TCMLR0(Timer Compare Mach Low REG.0) 0004h TCMHR0(Timer Compare Mach High REG.0) 0005h TCLR0(Timer Count Low REG.0) 0006h TCHR0(Timer Count High REG.0) 0x00E0 0000h TSSR(Timer Source Setting REG.) 000h TIER(Timer Interrupt Enable REG.) 000h TCSR(Timer Contorol Status REG.) 000h TCMLR(Timer Compare Mach Low REG.) 0004h TCMHR(Timer Compare Mach High REG.) 0005h TCLR(Timer Count Low REG.) 0006h TCHR(Timer Count High REG.) 0x00F0 0000h TSSR(Timer Source Setting REG.) 000h TIER(Timer Interrupt Enable REG.) 000h TCSR(Timer Contorol Status REG.) 000h TCMLR(Timer Compare Mach Low REG.) 0004h TCMHR(Timer Compare Mach High REG.) 0005h TCLR(Timer Count Low REG.) 0006h TCHR(Timer Count High REG.)

For implementations where case to ambient thermal resistance is ≤ 50°C/W. Parameter Symbol Min. Max. Units Core Power Supply Voltage VDDK -0. VIO+0. V Clock Power Supply Voltage VDDC -0. .6 V IO Power Supply Voltage VIO -0. .6 V Input Output Voltage VI/VO -0. .6 V Operating Environnent Temperature TA -40 85 °C Storage Temperature TS -40 50 °C Electrical Specifications (DC) Specifications (Min. & Max. values) hold over the recommended operating conditions unless otherwise noted. Unspecified test conditions may be anywhere in their operating range and VIO = 3.3+0.33V VIO= 3.3+/-0.33V, TA=-40 to +85°C Parameter Symbol Min. Typ. Max. Units Conditions Core Power Supply VDDK .6 .8 .98 V Clock Power Supply VDDC .97 . .6 V IO Power Supply VIO .97 . .6 V Input Low Voltage VIL 0.8 V LVTTL Input High Voltage VIH .0 V LVTTL Switch Threshold Vt .5 V LVTTL Schmitt-Trigger –ve Threshold Voltage Vt- 0.8 . V LVTTL Schmitt- Trigger +ve Threshold Voltage Vt+ .6 .0 V LVTTL Input Leakage Current IIN -0 ± 0 µA VI=VIO or GND Tri-State Output Leakage Current IOZ -0 ± 0 µA VI=VIO or GND Output Low Voltage VOL 0.4 V IOL = ~6mA Output High Voltage VOH .4 V IOH = ~6mA Input Pull-Down Resistance RPD 40 75 90 kΩ VIN =VIO Current (VFIR running state) – VDDK Iozk 8.6 0.5 .5 mA SD:High Current (IDLE state) – VDDK IOZk 8.0 0. .0 mA SD:High Current (VFIR running state) – VIO IOZIO 940 µA SD:High Current (IDLE state) – VIO IOZIO 4 0 µA SD:High Current (VFIR running state) – VIO IOZIO 5 µA SD:High Current (IDLE state) – VIO IOZIO 0. µA SD:High Current (IDLE state) – VIO IOZIO 8 µA SD:High Clock Power Supply Current-VDDC IOZC 4.0 4.8 5.9 mA Capacitor 0pF

VIO= 2.5+/-0.25V, TA=-40 to +85°C Parameter Symbol Min. Typ. Max. Units Conditions Core Power Supply VDDK .6 .8 .98 V Clock Power Supply VDDC .97 . .6 V IO Power Supply VIO .5 .5 .75 V Input Low Voltage VIL 0.5*VIO V CMOS Input High Voltage VIH 0.65*VIO V CMOS Switch Threshold Vt .5 V CMOS Schmitt-Trigger –ve Threshold Voltage Vt- 0.5*VIO 0.94 V CMOS Schmitt- Trigger +ve Threshold Voltage Vt+ .4 0.65*VIO V CMOS Input Leakage Current IIN -0 ± 0 µA VI=VIO or GND Tri-State Output Leakage Current IOZ -0 ± 0 µA VI=VIO or GND Output Low Voltage VOL 0.4 V IOL = . ~8.8mA Output High Voltage VOH .85 V IOH = . ~8.8mA Input Pull-Down Resistance RPD 45 5 90 kΩ VIN =VIO VIO= 1.8+/-0.18V, TA=-40 to +85°C Parameter Symbol Min. Typ. Max. Units Conditions Core Power Supply VDDK .6 .8 .98 V Clock Power Supply VDDC .97 . .6 V IO Power Supply VIO .6 .8 .98 V Input Low Voltage VIL 0.*VIO V CMOS Input High Voltage VIH 0.7*VIO V CMOS Switch Threshold Vt 0.85 V CMOS Schmitt-Trigger –ve Threshold Voltage Vt- 0.*VIO 0.65 V CMOS Schmitt- Trigger +ve Threshold Voltage Vt+ .08 0.7*VIO V CMOS Input Leakage Current IIN -0 ± 0 µA VI=VIO or GND Tri-State Output Leakage Current IOZ -0 ± 0 µA VI=VIO or GND Output Low Voltage VOL 0.4 V IOL = 0.7 ~5.6mA Output High Voltage VOH 0.75*VIO V IOH = 0.7 ~5.6mA Input Pull-Down Resistance RPD 80 0 50 kΩ VIN =VIO

Shutdown Currents (Internal Clock is Used) [1] Parameter Min. Typ. Max. Unit Conditions Note Shutdown Current (VDDK) 7.8 8.8 9.7 mA /SD: LOW CLKSEL: LOW CLKIN: LOW External quartz crystal is kept under oscillation Shutdown Current (VDDK) 0.4 mA /SD: LOW CLKSEL: HIGH CLKIN: LOW External quartz crystal is suspending oscillation Clock Power Supply Current (VDDC) 0. mA /SD: LOW CLKSEL: HIGH CLKIN: LOW Shutdown Current (VIO) 0. mA /SD: LOW CLKSEL: HIGH CLKIN: LOW Shutdown Current (VIO) 0. mA /SD: LOW CLKSEL: HIGH CLKIN: LOW Shutdown Current (VIO) 0. mA /SD: LOW CLKSEL: HIGH CLKIN: LOW Shutdown Currents (External Clock is Used) [1] Parameter Min. Typ. Max. Unit Conditions Note Shutdown Current (VDDK) . .9 mA /SD: LOW CLKSEL: HIGH CLKIN: 48MHz /XTALIN: LOW Clock Power Supply Current (VDDC) 0. mA /SD: LOW CLKSEL: HIGH LKIN: 48MHz /XTALIN: LOW Shutdown Current (VIO) 0. mA /SD: LOW CLKSEL: HIGH CLKIN: 48MHz /XTALIN: LOW Shutdown Current (VIO) 0. mA /SD: LOW CLKSEL: HIGH CLKIN: 48MHz /XTALIN: LOW Shutdown Current (VIO) 8.5 mA /SD: LOW CLKSEL: HIGH CLKIN: 48MHz /XTALIN: LOW (1) Test Conditions: - /RESET = HIGH (VIO1) - A[7:0] = Must be driven either HIGH (VIO1) or LOW (0V) - D[7:0] = Must be driven either HIGH (VIO1) or LOW (0V) - /CS = HIGH (VIO1) - /WE = HIGH (VIO1) - /OE = HIGH (VIO1) - IrRXD0 = HIGH (VIO2)

Standard values of the system clock input Frequency: 48MHz ± 100ppm Input Duty: Must be within 50% ± 5%. Power-up Procedures V t VDDK(=1.8V) VDDC,VIO(=1.8 to 3.3V) V t VDDK(=1.8V) VDDC,VIO(=1.8 to 3.3V) V V Recommended Power-Up Procedure Allowable Limit of Power-Up Procedure Turn on the core power supply VDDK before you turn on the VDDC and VIO power supply and shut it down later If you want to turn on the core power supply VDDK after you turn on VDDC and VIO power supply, you must keep V = VIO-VDDK < 0.5V during the time before VDDK becomes stable

2) Stabilization Time of Power-on Oscillation (Internal Clock is Used) A.C Timing 1) Reset Input Timing Item Symbol Min Typ Max Unit Reset Pulse Width tRST 50 ns /RESET -on Oscillation tRST Oscillation Stabilization Term Internal clock VCC /RESET SOC1 t RST /SD t Parameter Symbol Typical Value Power-on Oscillation stabilization time tSOC 0ms Reset Pulse Width tRST 50ns

3) Return Oscillation Stabilization Time via CLKSEL Item Symbol Min Typ Max Unit CLKSEL return oscillation stabilization time TSOC 0 msec Oscillation stabilization time when the quartz crystal is connected Oscillation stabilization term Internal clock CLKSEL /RESET tSOC1 tRST Stabilization Time of Power-on Oscillation (External Clock is Used) Parameter Symbol Typical Value Power-on Oscillation stabilization time tSOC 50ns Reset Pulse Width tRST 50ns Oscillation Stabilization Term External clock VCC /RESET SOC1 t RST /SD t

4) Read Operations Item Symbol Min Max Unit Address setting time tASR 0 ns Address retaining time tAHR 0 ns Data delay time tDRD 80 ns Read pulse amplitude tRDW 80 ns Output retaining time tDHW 0 ns Turnaround time tOET 50 ns /CS A[7:0] /OE D[7:0] /OE Valid data tDRD tDHW tWTH tRDW tASR tAHR Valid data tOET

5) Write Operations Item Symbol Min Max Unit Address setting time tASW 0 ns Address retaining time tAHW 0 ns Write pulse amplitude tWRW 50 ns Data setting time tDSW 0 ns Data retaining time tDHW 0 ns Turnaround time tWET 70 ns /CS A[7:0] /WR D[7:0] /WE Valid data tDSW tDHW tASW tAHW Valid data tWRW tWET

6) Send Pulse Amplitude Item Symbol Conditions Min Typ Max Unit SIR send pulse amplitude 9,600bps tTSPW /6 pulse amplitude 0.7 0.8 0.9 μs 9,00bps 0. 0.4 0.5 μs 8,400bps 5.6 5.8 5.9 μs 57,600bps .4 .40 .47 μs 5,00bps .70 .7 .74 μs .6μS pulse amplitude .6μs fixed Typ register IRPLCR,IRPLCR PW[4:0] = 0x4E 0.8nsec Step changeable .665 .7 .769 μs SIR send cycle 9,600bps tTSRT 04.0 04. 04. μs 9,00bps 5.0 5. 5. μs 8,400bps 5. 6.0 6. μs 57,600bps 7. 7. 7.4 μs 5,00bps 8.5 8.6 8.7 μs MIR send pulse amplitude .5Mbps tTMPW Typ register IRPLCR,IRPLCR PW[4:0] = 0x4E 0.8nsec Step changeable 6 7 8 ｎs MIR send cycle .5Mbps tTMRT 854 868 875 ｎs FIR send pulse amplitude 4Mbps tTFPW 4 5 6 ｎs FIR send cycle 4Mbps tTFRT 500 ｎs VFIR send pulse amplitude 6Mbps tTFPW 4.0 4.7 4.0 ｎs

ASDL-7021 Tape and Reel Dimension:

Figure 4. Baking Conditions Chart Baking should only be done once. must be stored in a dry box. package. Once opened, moisture absorption begins. This part is compliant to JEDEC Level 3.

Recommended Reflow Profile Process Zone Symbol DT Maximum DT/Dtime or Duration Heat Up P, R 5°C to 50°C °C/s Solder Paste Dry P, R 50°C to 00°C 60s to 80s Solder Reflow P, R P, R4 00°C to 55°C 55°C to 00°C °C/s -6°C/s Cool Down P4, R5 00°C to 5°C -6°C/s Time maintained above 7°C > 7°C 60s to 50s Peak Temperature 60°C Time within 5°C of actual Peak Temperature > 55°C 0s to 40s Time 5°C to Peak Temperature 5°C to 60°C 8mins The reflow profile is a straight-line representation of a nominal temperature profile for a convective reflow solder process. The temperature profile is divided into four process zones, each with different DT/Dtime tem - perature change rates or duration. The DT/Dtime rates or duration are detailed in the above table. The tempera - tures are measured at the component to printed circuit board connections. In process zone P1 , the PC board and ASDL-7021 pins are heated to a temperature of 150°C to activate the flux in the solder paste. The temperature ramp up rate, R1, is limited to 3°C per second to allow for even heating of both the PC board and ASDL-7021 pins. Process zone P2 should be of sufficient time duration (100 to 180 seconds) to dry the solder paste. The temper - ature is raised to a level just below the liquidus point of the solder, usually 200°C (392°F). Process zone P3 is the solder reflow zone. In zone P3, the temperature is quickly raised above the liquidus point of solder to 255°C (491°F) for optimum results. The dwell time above the liquidus point of solder should be between 20 and 40 seconds. It usually takes about 20 seconds to assure proper coalescing of the solder balls into liquid solder and the formation of good solder con - nections. Beyond a dwell time of 40 seconds, the inter - metallic growth within the solder connections becomes excessive, resulting in the formation of weak and un - reliable connections. The temperature is then rapidly reduced to a point below the solidus temperature of the solder, usually 200°C (392°F), to allow the solder within the connections to freeze solid. Process zone P4 is the cool down after solder freeze. The cool down rate, R5, from the liquidus point of the solder to 25°C (77°F) should not exceed 6°C per second maximum. This limitation is necessary to allow the PC board and ASDL-7021 pins to change dimensions evenly, putting minimal stresses on the ASDL-7021. 50 100 150 200 250 300 t-TIME (SECONDS) 120 150 180 200 230 255 T - TEMPERATURE (°C) R3 R4 217 MAX 260C 60 sec to 180 sec Above 217 C HEAT UP SOLDER PASTE DRY SOLDER REFLOW COOL DOWN

Figure A1. Block Diagram of ASDL-7021 interface with Recommended Transceiver and Host Microcontroller Appendix A: General Application Guide for the ASDL-7021 Integrated FIR/VFIR IrDA Controller ASDL-7021 FIR/VFIR IrDA Controller Host Microcontroller Address Bus Data Bus /CS /OE /WE /IRQ /SD /RESET CLKSEL CLKIN IrTX0(IrDA) IrTX1(Remote IrRXD0 IrOUT0(IrMode/S CLK) IrOUT1 (SD) IrDA Transceiver (can be STC or non-STC with/without RC) RECOMMENDED FIR HW: ASDL-3023, HSDL-3021, HSDL-3020 and HSDL-3220 For company and product information, please go to our web site: WWW.liteon.com or http://optodatabook.liteon.com/databook/databook.aspx Data subject to change. Copyright © 007 Lite-On Technology Corporation. All rights reserved.