AS8ERLC128K32

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Rev. 2.1 11/10 Micross Components reserves the right to change products or specifi cations without notice. GENERAL DESCRIPTION The AS8ERLC128K32 is a 4 Megabit Radiation Tolerant EEPROM Module organized as 128K x 32 bit. User con fi gurable to 256K x16 or 512Kx 8. The module achieves high speed access, low power consumption and high reliability by employing advanced CMOS memory technology. The military grade product is manufactured in compliance to MIL- STD 883, making the AS8ERLC128K32 ideally suited for military or space applications. The module is offered as a 68 lead 0.880 inch square ceramic quad fl at pack. It has a max. height of 0.200 inch (non-shielded). This package design is targeted for those applications which require low profi le SMT Packaging. * Contact factory for more information. 2-sided shielding provided via Tungsten lids on both sides. 6.5X typ. TID boost due to shielding. (Geostationary orbit) Proven total dose 40K to 100K RADS. Micross can perform TID lot testing.

FEATURES

• Access time of 250ns , 300ns
• Operation with single 3.3V (+ .3V) supply
• LOW Power Dissipation: Active(Worst case): 300mW (MAX), Max Speed Operation Standby(Worst case): 7.2mW(MAX), Battery Back-up Mode
• Automatic Byte Write: 15 ms (MAX)
• Automatic Page Write (128 bytes): 15 ms (MAX)
• Data protection circuit on power -on/off
• Low power CMOS MNOS cell Technology
• 10

4 Erase/Write cycles (in Page Mode)

• Software data protection
• TTL Compatible Inputs and Outputs
• Data Retention: 10 years
• Ready/Busy\\ and Data Polling Signals
• Write protection by RES\\ pin
• Radiation Tolerant: Proven total dose 40K to 100K RADS*
• Shielded Package for Best Radiation Immunity
• Operating Temperature Ranges: Military: -55 oC to +125oC Industrial: -40 oC to +85oC OPTIONS MARKINGS
• Timing 250 ns -250 300 ns -300
• Package Ceramic Quad Flat pack w/ formed leads Q No. 703Q Ceramic Quad Flat pack w/ tie bar QB No. 703QB Shielded Ceramic Quad Flat pack SQ No. 703SF Shielded Ceramic Quad Flat pack SQB No. 703SQB AVAILABLE AS MILITARY SPECIFICATIONS
• MIL-PRF-38534 PIN ASSIGNMENT (Top View)

68 Lead CQFP

128K x 32 Radiation Tolerant EEPROM For more products and information please visit our web site at www.micross.com I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 GND I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 RES\\ CS3\\ GND CS4\\ WE1\\ A10 Vcc 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43Vcc A11 A12 A13 *A15 *A14 A16 CS1\\ OE\\ CS2\\ NC WE2\\ WE3\\ WE4\\ NC NC RDY I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 GND I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 PIN NAME FUNCTION A0 to A16 Address Input I/O0 to I/O31 Data Input/Output OE\\ Output Enable CE\\ Chip Enable WE\\ Write Enable V CC Power Supply VSS Ground RDY/BUSY\\ Ready Busy RES\\ Reset FUNCTIONAL BLOCK DIAGRAM *Pin #'s 31 and 32, A15 and A14 respectively, are reversed from the AS8E128K32. Correct use of these address lines is required for operation of the SDP mode to work properly. FUNCTION FUNCTIONFUNCTION FUNCTIONFUNCTION FUNCTIONFUNCTION FUNCTIONFUNCTION RDY/ BUSY\\ RES\\

Rev. 2.1 11/10 Micross Components reserves the right to change products or specifi cations without notice. NOTES: 1. RDY/Busy\\ output has only active LOW VOL and high impedance state. It can not go to HIGH (VOH) state. 2. V CC - 0.5V < VH < VCC+0.5V 3. X : DON'T CARE TRUTH TABLE MODE CE\\ OE\\ WE\\ RES\\ RDY/BUSY\\1 I/O Read VIL VIL VIH VH

2 High-Z Dout

Standby VIH X3 X X High-Z High-Z Write VIL VIH VIL VH High-Z to VOL Din Deselect VIL VIH VIH VH High-Z High-Z XX VIH X --- --- X VIL X X --- --- Data\\ Polling VIL VIL VIH VH VOL Dout (I/O7) Program Reset X X X VIL High-Z High-Z Wirte Inhibit

Rev. 2.1 11/10 Micross Components reserves the right to change products or specifi cations without notice. *Stresses greater than those listed under "Absolute Maxi- mum Ratings" may cause permanent damage to the de- vice. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this specifi cation is not implied. Exposure to absolute maximum rating condi- tions for extended periods may affect reliability. **Junction temperature depends upon package type, cycle time, loading, ambient temperature and air fl ow, and humidity (plastics). ABSOLUTE MAXIMUM RATINGS* V oltage on Vcc Supply Relative to Vss Operating Temperature Range Thermal Resistance junction to case (JC): NOTES: 1) Including electrical characteristics and data retention. 2) VIN MIN = -1.0V for pulse width < 20ns. ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS (-55oC<TA<125oC or -40oC to +85oC; Vcc = 3.3V +/-.3V) NOTE: 1) VIL (MIN): -1.0V for pulse width < 20ns. 2) All other Signal pins except RES\\ PARAMETER CONDITIONS SYMBOL MIN MA X UNITS Input High Voltage VIH 2.2 VCC +0.3 V Input High Voltage (RES\\) VH VCC -0.3 V CC +.3 V Input Low Voltage VIL -0.31 0.8 V Input Low Voltage (RES\\) VL -0.31 0.4 V LOW INPUT Leakage(RES\\ Signal) RES\\=0V, VCC=3.6V ILI(RES) -300 P$ HIGH INPUT Leakage(RES\\ Signal) RES\\=3.6V, VCC=3.6V IHI(RES) -10.0 P$ HIGH INPUT Leakage(RES\\ Signal) RES\\=3.3V, VCC=3.3V IHI(RES) -30.0 P$ INPUT LEAKAGE CURRENT2 OV < VIN < VCC ILI -10 10 P$ OUTPUT LEAKAGE CURRENT2 Outputs(s) Disabled, OV < VOUT < VCC ILO -10 10 P$ Output High Voltage IOH = -0.4mA V OH VCCx.8 -- V Output High Voltage IOH = -0.1mA V OH VCC-0.3 -- V Output Low Voltage IOL = 2.1mA V OL -- 0.4 V Output Low Voltage IOL = 0.1mA V OL -- 0.2 V Supply Voltage VCC 33 . 6V MAX MAX CONDITIONS SYM -250 -300 UNITS Iout = 0mA, VCC = 3.6V Cycle = 1μS, Duty = 100% 30 30 Iout = 0mA, VCC = 3.6V Cycle = MIN, Duty = 100% 80 70 CE\\ = VCC, VCC = 3.6V I CC1 0.4 0.4 mA CE\\ = VIH, VCC = 3.6V I CC2 44 m A Power Supply Current: Standby Icc3 mA PARAMETER Power Supply Current: Operating

Rev. 2.1 11/10 Micross Components reserves the right to change products or specifi cations without notice. NOTE: 1. This parameter is guaranteed but not tested. CAPACITANCE TABLE1 (VIN = 0V, f = 1 MHz, TA = 25oC, VCC=3.3V) SYMBOL P ARAMETER MAX UNITS CADD A0 - A16 Capacitance 40 pF COE OE\\, RES\\, RDY Capacitance 40 pF CWE, CCE WE\\ and CE\\ Capacitance 12 pF CIO I/O 0- I/O 31 Capacitance 20 pF ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (-55oC < TA < +125oC or -40oC to +85oC; Vcc = 3.3V +.3V) AC TEST CHARACTERISTICS TEST SPECIFICATIONS NOTES: Vz is programmable from -2V to + 5V . I OL and IOH programmable from 0 to 16 mA. Vz is typically the midpoint of VOH and VOL. IOL and IOH are adjusted to simulate a typical resistive load circuit. Figure 1 MIN MA X MIN MA X Address to Output Delay CE\\ = OE\\ = VIL, WE\\ = VIH tACC 250 300 ns CE\\ to Output Delay OE\\ = V IL, WE\\ = VIH tCE 250 300 ns OE\\ to Output Delay OE\\ = VIL, WE\\ = VIH tOE 10 120 10 130 ns Address to Output Hold CE\\ = OE\\ = VIL, WE\\ = VIH tOH 00 n s CE\\ or OE\\ high to Output Float (1) OE\\ = V IL, WE\\ = VIH tDF 0 50 0 50 ns RES\\ low to Output Float (1) CE\\ = OE\\ = VIL, WE\\ = VIH tDFR 0 350 0 350 ns RES\\ to Output Delay CE\\ = OE\\ = VIL, WE\\ = VIH tRR 0 600 0 600 ns -300DESCRIPTION -250 SYMBOL UNITSTEST CONDITIONS SYMBOL PARAMETER MAX OH OLI ICurrent Source Current Source Vz = 1.5V (Bipolar Supply) Device Under Test Ceff = 50pf

Rev. 2.1 11/10 Micross Components reserves the right to change products or specifi cations without notice. ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC WRITE CHARACTERISTICS (-55oC < TA < +125oC; Vcc = 3.3V +.3V) READ TIMING WAVEFORM tACC tCE tOE tOH tDF tDFR tRR HIGH-Z ADDRESS CE\\ OE\\ WE\\ Data Out RES\\ DATA OUT V ALID VIH SYMBOL PARAMETER MIN(2) MAX UNITS tAS Address Setup Time 0 ms tAH Address Hold Time 150 ns tCS CE\\ to Write Setup Time (WE\\ controlled) 0 ns tCH CE\\ Hold Time (WE\\ controlled) 0 ns tWS WE\\ to Write Setup Time (CE\\ controlled) 0 ns tWH WE\\ to Hold Time (CE\\ controlled) 0 ns tOES OE\\ to Write Setup Time 0 ns tOEH OE\\ to Hold Time 0 ns tDS Data Setup Time 100 ns tDH Data Hold Time 10 ns tWP WE\\ Pulse Width (WE\\ controlled) 250 ns tCW CE\\ Pulse Width (CE\\ controlled) 250 ns tDL Data Latch Time 750 ns tBLC Byte Load Cycle 1 30 μs tBL Byte Load Window 100 μs tWC Write Cycle Time 15 (3) ms tDB Time to Device Busy 150 ns tDW Write Start Time 250 (4) ns tRP Reset Protect Time 100 μs tRES Reset High Time (5) 2 μs

Rev. 2.1 11/10 Micross Components reserves the right to change products or specifi cations without notice. BYTE WRITE TIMING WAVEFORM (WE\\ CONTROLLED) BYTE WRITE TIMING WAVEFORM (CE\\ CONTROLLED) tRES tRP HIGH-Z tOES tAS tCS tAH tWC tCH tBL tOEH tWP tDS tDH tDB tDW HIGH-Z VCC RES\\ RDY/Busy\\ Din OE\\ WE\\ CE\\ Address VOL tRES tRP HIGH-Z tOES tAS tWS tAH tWC tWH tBL tOEH tCW tDS tDH tDB tDW HIGH-Z VCC RES\\ RDY/Busy\\ Din OE\\ WE\\ CE\\ Address VOL

Rev. 2.1 11/10 Micross Components reserves the right to change products or specifi cations without notice. PAGE WRITE TIMING WAVEFORM (WE\\ CONTROLLED) PAGE WRITE TIMING WAVEFORM (CE\\ CONTROLLED) HIGH-Z HIGH-Z VCC RES\\ RDY/Busy\\ Din OE\\ CE\\ WE\\ Address(6) A0 to A16 tRES tRP tDB tDS tDH tOES tCS tCH tBLC tDL tWP tAS tAH tBL tWC tOEH tDW HIGH-Z HIGH-Z VCC RES\\ RDY/Busy\\ Din OE\\ WE\\ CE\\ Address(6) A0 to A16 tRES tRP tDB tDS tDH tOES tWS tWH tBLC tDL tCW tAS tAH tBL tWC tOEH tDW

Rev. 2.1 11/10 Micross Components reserves the right to change products or specifi cations without notice. DATA POLLING TIMING WAVEFORM AnAn Din X Dout X Dout X tOE (7) tWC tOEH tCE (7) tOES tDW Address CE\\ WE\\ OE\\ I\\O7 NOTES: 1. tDF and tDFR are defi ned as the time at which the outputs achieve the open circuit conditions and are no longer driven. 2. Use this device in longer cycle than this value. 3. t WC must be longer than this value unless polling techniques or RDY/Busy\\ are used. This device automatically completes the internal write operation within this value. 4. Next read or write operation can be initiated after t DW if polling techniques or RDY/Busy\\ are used. 5. This parameter is sampled and not 100% tested. 6. A7 to A16 are page addresses and must be same (i.e. Not Change) during the page write operation. 7. See AC read characteristics.

Rev. 2.1 11/10 Micross Components reserves the right to change products or specifi cations without notice. TOGGLE BIT This device provides another function to determine the internal programming cycle. If the EEPROM is set to read mode during the internal programming cycle, I/O6 will charge from "1" to "0" (toggling) for each read. When the internal program- ming cycle is fi nished, toggling of I/O6 will stop and the device can be accessible for next read or program. TOGGLE BIT WAVEFORM NOTES: 1) I/O6 beginning state is "1". 2) I/O6 ending state will vary. 3) See AC read characteristics. 4) Any locations can be used, but the address must be fi xed. Dout Dout DoutDout Din tCE tOE tOEH tWC tDW 4Next Mode tOES Address CE\\ WE\\ OE\\ I/O6 SOFTWARE DATA PROTECTION TIMING WAVEFORM (In protection mode) tWCtBLC {Address Data (each byte) 5555 AA AAAA or 2AAA 5555 Write Address* Write Data V CC CE\\ WE\\ tBLCtBLC * During this write cycle, data is physically written to the address provided.

Rev. 2.1 11/10 Micross Components reserves the right to change products or specifi cations without notice. SOFTWARE DATA PROTECTION TIMING WAVEFORM (In non-protection mode) FUNCTIONAL DESCRIPTION Automatic Page Write Page-mode write feature allows 1 to 128 bytes of data to be written into the EEPROM in a single write cycle. Following the initial byte cycle, an additional 1 to 128 bytes can be written in the same manner. Each additional byte load cycle must be started within 30μs from the preceding falling edge of WE\\ or CE\\. When CE\\ or WE\\ is kept high for 100μs after data input, the EEPROM enters write mode automatically and the input data are written into the EEPROM. DATA\\ Polling DATA\\ polling allows the status of the EEPROM to be de- termined. If EEPROM is set to read mode during the write cycle, an inversion of the last byte of data to be loaded outputs from I/O's 7, 15, 23, and 31 to indicate that the EEPROM is performing a write operation. RDY/Busy\\ Signal RDY/Busy\\ signal also allows status of the EEPROM to be determined. The RDY/Busy\\ signal has high impedance except in write cycle and is lowered to V OL after the fi rst write signal. At the end of write cycle, the RDY/Busy\\ signal changes state to high impedance. RES\\ Signal When RES\\ is low, the EEPROM cannot be read or pro- grammed. Therefore, data can be protected by keeping RES\\ low when V CC is switched. RES\\ should be high during read and programming because it doesn't provide a latch function. See timing diagram below. Program inhibit Program inhibit Read inhibitRead inhibit VCC RES\\1 RES\\ Signal Diagram tWC Address Data (each byte) 5555 AA AAAA or 2AAA 5555 AAAA or 2AAA V CC CE\\ WE\\ 5555 AA 5555 Normal ac- tive mode Note(s): 1- RES\\=TRUE=V L >/=-0.3v </=0.4v

Rev. 2.1 11/10 Micross Components reserves the right to change products or specifi cations without notice. WE\\, CE\\ Pin Operation During a write cycle, address are latched by the falling edge of WE\\ or CE\\, and data is latched by the rising edge of WE\\ or CE\\. Write/Erase Endurance and Data Retention Time The endurance is 10 4 cycles in case of the page programming and 103 cycles in case of the byte programming (1% cumulative failure rate). The data retention time is more than 10 years when a device is page-programmed less than 104 cycles. RDY/Busy\\ SIGNAL RDY/Busy\\ signal also allows status of the EEPROM to be determined. The RDY/Busy\\ signal has high impedance except in write cycle and is lowered to VOL after the fi rst write signal. At the end of the write cycle, the RDY/Busy\\ signal changes state to high impedance. This allows many AS8ERLC128K32 devices RDY/Busy\\ signal lines to be wired-OR together. PROGRAMMING/ERASE The AS8ERLC128K32 does NOT employ a BULK- erase function. The memory cells can be programmed ‘0’ or ‘1’. A write cycle performs the function of erase & write on every cycle with the erase being transparent to the user. The internal erase data state is considered to be ‘1’. To program the memory array with background of ALL 0’s or All 1’s, the user would program this data using the page mode write operation to program all 1024 128-byte pages. Data Protection 1. Data Protection against Noise on Control Pins (CE\\, OE\\, WE\\) During Operation During readout or standby, noise on the control pins may act as a trigger and turn the EEPROM to programming mode by mistake. To prevent this phenomenon, this device has a noise cancellation function that cuts noise if its width is 20ns or less in program mode. Be careful not to allow noise of a width more than 20ns on the control pins. See Diagram 1 below. 2. Data Protection at V CC On/Off When V CC is turned on or off, noise on the control pins generated by external circuits (CPU, etc.) may act as a trigger and turn the EEPROM to program mode by mistake. To prevent this unintentional programming, the EEPROM must be kept in an unprogrammable state while the CPR is in an unstable state. NOTE: The EEPROM should be kept in unprogram- mable state during V CC on/off by using CPU RESET signal. See the timing diagram below. DIAGRAM 1 DATA PROTECTION AT VCC ON/OFF *Unprogrammable VCC CPU RESET *Unprogrammable

Rev. 2.1 11/10 Micross Components reserves the right to change products or specifi cations without notice. Data Protection Cont. a. Protection by RES\\ The unprogrammable state can be realized by the CPU's reset signal inputs directly to the EEPROM's RES pin. RES should be kept VSS level during VCC on/off. The EEPROM brakes off programming operation when RES becomes low, programming operation doesn't fi n- ish correctly in case that RES falls low during programming operation. RES should be kept high for 10ms after the last data inputs. See the timing diagram below. 3. Software data protection To prevent unintentional programming, this device has the software data protection (SDP) mode. The SDP is enabled by inputting the 3 bytes code and write data in Chart 1. SDP is not enabled if only the 3 bytes code is input. To program data in the SDP enable mode, 3 bytes code must be input before write data. This 4th cycle during write is required to initiate the SDP and physically writes the address and data. While in SDP the entire array is protected in which writes can only oc- cur if the exact SDP sequence is re-executed or the unprotect sequence is executed. The SDP is disabled by inputting the 6 bytes code in Chart 2. Note that, if data is input in the SDP disable cycle, data can not be written. The software data protection is not enabled at the shipment. NOTE: These are some differences between Micross and other company's for enable/disable sequence of software data protection. If these are any questions, please contact Micross. PROTECTION BY RES\\ Program inhibit VCC RES\\ Program inhibit WE\\ or CE\\ 1μ min 100μ min 10 ms min CHART 1 Address 5555 AAAA or 2AAA 5555 Write Address Data (each Byte) AA Write Data} Normal data input CHART 2 Address 5555 AAAA or 2AAA 5555 5555 AAAA or 2AAA 5555 Data (each Byte) AA AA

Rev. 2.1 11/10 Micross Components reserves the right to change products or specifi cations without notice. Micross Case #703 (Package Designator Q) MECHANICAL DEFINITIONS* *All measurements are in inches. 4 x D2 4 x D1 4 x D b e Pin 1 DETAIL A 0o - 7o R B SEE DETAIL A A MIN MAX A 0.123 0.200 A1 0.118 0.186 A2 0.000 0.020 b 0.013 0.017 B D D1 0.870 0.890 D2 0.980 1.000 D3 0.936 0.956 e R 0.005 --- L1 0.035 0.045

0.050 BSC

SYMBOL MICROSS PACKAGE SPECIFICATIONS

0.010 REF

0.800 BSC

Rev. 2.1 11/10 Micross Components reserves the right to change products or specifi cations without notice. MECHANICAL DEFINITIONS* Micross Case #703SQ MIN MAX A 0.190 0.235 A1 0.180 0.220 A2 0.005 0.020 b 0.013 0.017 B D D1 0.870 0.890 D2 0.980 1.000 D3 0.930 0.960 e R 0.005 --- L1 0.035 0.045 SYMBOL MICROSS PACKAGE SPECIFICATIONS

Rev. 2.1 11/10 Micross Components reserves the right to change products or specifi cations without notice. MECHANICAL DEFINITIONS* Micross Case #703SQB MIN MAX A0 . 2 3 5 A1 0.180 0.220 A2 0.005 0.020 b 0.013 0.017 D/E 1.500 1.540 D1 / E1 0.870 0.890 D2 / E2 1.920 2.000 e j 0.190 0.210 k 0.890 0.910 L 0.310 0.330 SYMBOL MICROSS PACKAGE SPECIFICATIONS Dimensions in Inches .040 BSC

Rev. 2.1 11/10 Micross Components reserves the right to change products or specifi cations without notice. Micross Case (Package Designator QB) MECHANICAL DEFINITIONS* *All measurements are in inches. MIN MAX A 0.157 0.190 A1 0.142 0.175 A2 0.005 0.020 b 0.013 0.017 c 0.009 0.012 D/E 1.500 1.540 D1 / E1 0.870 0.890 D2 / E2 1.920 2.000 e j 0.190 0.210 k 0.890 0.910 L 0.310 0.330 SYMBOL MICROSS PACKAGE SPECIFICATIONS Dimensions in Inches .040 BSC

Rev. 2.1 11/10 Micross Components reserves the right to change products or specifi cations without notice. *AVAILABLE PROCESSES IT = Industrial Temperature Range -40 oC to +85oC XT = Extended Temperature Range -55 oC to +125oC Q = MIL-PRF-38534, Class H compliant -55 oC to +125oC

ORDERING INFORMATION

EXAMPLE: AS8ERLC128K32Q-250/ Q Device Number Package Type Speed ns Process AS8ERLC128K32 Q -250 /* AS8ERLC128K32 Q -300 /* AS8ERLC128K32 QB -250 /* AS8ERLC128K32 QB -300 /* AS8ERLC128K32 SQ -250 /* AS8ERLC128K32 SQ -300 /* AS8ERLC128K32 SQB -250 /* AS8ERLC128K32 SQB -300 /*

Rev. 2.1 11/10 Micross Components reserves the right to change products or specifi cations without notice. MICROSS TO DSCC PART NUMBER CROSS REFERENCE* * Micross part number is for reference only. Orders received referencing the SMD part number will be processed per the SMD. Package Designator Q Micross Part # SMD Part AS8ERLC128K32Q to be determined AS8ERLC128K32Q to be determined Package Designator QB Micross Part # SMD Part AS8ERLC128K32QB to be determined AS8ERLC128K32QB to be determined

Rev. 2.1 11/10 Micross Components reserves the right to change products or specifi cations without notice. DOCUMENT TITLE 128K x 32 Radiation Tolerant EEPROM Rev # History Release Date Status

2.1 Fixed Pin Assignment formatting November 2010 Release

issues and added RES\\ and RDY/BUSY\\ signals to the block diagram, updated order chart and note at bottom of page 1. Deleted "Preliminary Speci fi cation" from the top of each page, making the datasheet "Release" status.