AS8E128K32 MICROSS | Alldatasheet
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Technical content
Rev. 8.2 07/10 Micross Components reserves the right to change products or specifi cations without notice. GENERAL DESCRIPTION The AS8E128K32 is a 4 Megabit EEPROM Module organized as 128K x 32 bit. User con fi gurable to 256K x16 or 512Kx 8. The module achieves high speed access, low power consumption and high reliability by employing advanced CMOS memory technology. The military grade product is manufactured in compliance to the SMD and MIL-STD 883, making the AS8E128K32 ideally suited for military or space applications. The module is offered in a 1.075 inch square ceramic pin grid array substrate. This package design provides the optimum space saving solution for boards that accept through hole packaging. The module is also offered as a 68 lead 0.990 inch square ceramic quad fl at pack. It has a max. height of 0.200 inch. This package de- sign is targeted for those applications which require low profi le SMT Packaging.
FEATURES
- Access times of 120, 140, 150, 200, 250, and 300 ns
- Built in decoupling caps for low noise operation
- Organized as 128K x32; User con fi gurable as 256K x16 or 512K x8
- Operation with single 5 volt supply
- Low power CMOS
- TTL Compatible Inputs and Outputs
- Operating Temperature Ranges: Military: -55 oC to +125oC Industrial: -40 oC to +85oC OPTIONS MARKINGS
- Timing 120 ns -120 140 ns -140 150 ns -150 200 ns -200 250 ns -250 300 ns -300
- Package Ceramic Quad Flat Pack Q Ceramic Quad Flat Pack Q3 Pin Grid Array- 8 Series P Pin Grid Array- 8 Series PN AVAILABLE AS MILITARY SPECIFICATIONS
- SMD 5962-94585
- MIL-STD-883 128K x 32 EEPROM EEPROM Memory Array For more products and information please visit our web site at www.micross.com PIN ASSIGNMENT (Top View)
66 Lead PGA
(Pins 8, 21, 28, 39 are no connects on the PN package)
68 Lead CQFP
(Pins 8, 21, 28, 39 are grounds on the P package)
Rev. 8.2 07/10 Micross Components reserves the right to change products or specifi cations without notice. of the last byte written will result in the complement of the written data to be presented on I/O7. Once the write cycle has been completed, true data is valid on all outputs, and the next write cycle may begin. DATA Polling may begin at anytime during the write cycle. TOGGLE BIT In addition to DATA Polling the module provides another method for determining the end of a write cycle. During the write operation, successive attempts to read data from the device will result in I/O6 of the accessed die toggling between one and zero. Once the write has completed, I/O6 will stop toggling and valid data will be read. Reading the toggle bit may begin at any time during the write cycle. DATA PROTECTION If precautions are not taken, inadvertent writes may occur during transitions of the host power supply. The E 2 module has incorporated both hardware and software features that will protect the memory against inadvertent writes. HARDWARE PROTECTION Hardware features protect against inadvertent writes to the module in the following ways: (a) Vcc sense - if Vcc is below 3.8 V (typical) the write function is inhibited; (b) Vcc power-on delay - once Vcc has reached 3.8 V the device will automatically time out 5 ms (typical) before allowing a write; (c) write inhibit - holding any one of OE\\ low, CE\\ high or WE\\ high inhibits write cycles; (d) noise fi lter - pulses of less than 15 ns (typical) on the WE\\ or CE\\ inputs will not initiate a write cycle. SOFTWARE DATA PROTECTION A software controlled data protection feature has been imple- mented on the memory module. When enabled, the software data protection (SDP), will prevent inadvertent writes. The SDP feature may be enabled or disabled by the user and is shipped with SDP dis- abled, SDP is enabled by the host system issuing a series of three write commands; three speci fi c bytes of data are written to three speci fi c addresses (refer to Software Data Protection Algorithm). After writing the three byte command sequence and after t WC the entire module will be protected from inadvertent write operations. It should be noted, that once protected the host may still perform a byte of page write to the module. This is done by preceding the data to be written by the same three byte command sequence used to enable SDP. Once set, SDP will remain active unless the disable command sequence is issued. Power transitions do not disable SDP and SDP will protect the 128K x 32 EEPROM during power-up and Power-down conditions. All com- mand sequences must conform to the page write timing specifi cations. The data in the enable and disable command sequences is not written to the device and the memory addresses used in the sequence may be written with data in either a byte or page write operation. After setting SDP, any attempt to write to the device without the three byte command sequence will start the internal write timers. No data will be written to the device; however, for the duration of t WC, read operations will effectively be polling operations. DEVICE IDENTIFICATION An extra 128 bytes of EEPROM memory is available on each die for user identifi cation. By raising A9 to 12V + 0.5V and using address locations 1FF80H to 1FFFFH the bytes may be written to or read from in the same manner as the regular memory array. DEVICE OPERATION The 128K x 32 EEPROM memory solution is an electrically erasable and programmable memory module that is accessed like a Static RAM for the read or write cycle without the need for external components. The device contains a 128-byte-page register to allow writing of up to 128 bytes of data simultaneously. During a write cycle, the address and 1 to 128 bytes of data are internally latched, freeing the address and data bus for other operations. Following the initia- tion of a write cycle, the device will automatically write the latched data using an internal control timer. The end of a write cycle can be detected by DATA polling of I/O7. Once the end of a write cycle has been detected a new access for a read or write can begin. READ The memory module is accessed like a Static RAM. When CE\\ and OE\\ are low and WE\\ is High, the data stored at the memory loca- tion determined by the address pins is asserted on the outputs. The module can be read as a 32 bit, 16 bit or 8 bit device. The outputs are put in the high impedance state when either CE\\ or OE\\ is high. This dual-line control gives designers fl exibility in preventing bus conten- tion in their system. BYTE WRITE A low pulse on the WE\\ or CE\\ input with CE\\ or WE\\ low (re- spectively) and OE\\ high initiates a write cycle. The address is latched on the falling edge of CE\\ or WE\\, whichever occurs last. The data is latched by the fi rst rising edge of CE\\ or WE\\. Once a BWDW (byte, word or double word) write has been started it will automatically time itself to completion. PAGE WRITE The page write operation of the 128K x 32 EEPROM allows 1 to 128 BWDWs of data to be written into the device during a single internal programming period. Each new BWDW must be written within 150-μ sec (t BLC) of the previous BWDW. If the t BLC limit is exceeded the memory module will cease accepting data and commence the internal programming operation. For each WE high to low transi- tion during the page write operation, A7-A16 must be the same. The A0-A6 inputs are used to specify which bytes within the page are to be written. The bytes may be loaded in any order and may be altered within the same load period. Only bytes which are speci fi ed for writing will be written; unnecessary cycling of other bytes within the page does not occur. DATA POLLING This memory module features DATA Polling to indicate the end of a write cycle. During a byte or page write cycle an attempted read
Rev. 8.2 07/10 Micross Components reserves the right to change products or specifi cations without notice. *Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this speci fi cation is not implied. Ex- posure to absolute maximum rating conditions for extended periods may affect reliability. **Junction temperature depends upon package type, cycle time, loading, ambient temperature and airfl ow, and humid- ity (plastics). ABSOLUTE MAXIMUM RATINGS* V oltage on Vcc Supply Relative to Vss Thermal Resistance junction to case (θ JC): ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS (-55 oC<TA<125oC or -40oC to +85oC; Vcc = 5V + 10%) μΑ μΑ MAX CONDITIONS SYM For All Speed Options UNITS CE\\<VIL; VCC=MAX, f = MAX = 1/tRC (MIN) Outputs Open Icc 250 mA CE\\>VIH; All Other Inputs <VIL or >VIH; VCC=MAX, f =0 Hz ISBT1 15 mA CE\\>VCC-0.2V; VCC=MAX, VIL<VSS +0.2V or VIH>VCC -0.2V; f = 0 Hz ISBT2 1m A CE\\=VCC, OE\\=VIH; I/O 0 through 31 = open; Input=VCC=5.5Vdc.; A0 through A16 change at 5 MHz; CMOS levels ISBT3 5m A Power Supply Current: Operating PARAMETER Power Supply Current: Standby
Rev. 8.2 07/10 Micross Components reserves the right to change products or specifi cations without notice. AC TEST CONDITIONS TEST SPECIFICATIONS NOTES: Vz is programmable from -2V to + 7V . I OL and IOH programmable from 0 to 16 mA. Vz is typically the midpoint of VOH and VOL. IOL and IOH are adjusted to simulate a typical resistive load circuit. NOTE: 1. This parameter is guaranteed but not tested. CAPACITANCE TABLE1 (VIN = 0V, f = 1 MHz, TA = 25oC) SYMBOL P ARAMETER MAX UNITS CADD A0 - A16 Capacitance 40 pF COE OE\\ Capacitance 40 pF CWE, CCE WE\\ and CE\\ Capacitance 10 pF CIO I/O 0- I/O 31 Capacitance 12 pF Figure 1 NOTES: 1. X can be VIL or VIH 2. Refer to AC Programming Waveforms TRUTH TABLE MODE CE OE WE I/O Read VIL VIL VIH DOUT Write (2) VIL VIH VIL DIN Standby/Write VIH X (1) X High Z Write Inhibit X X VIH Write Inhibit X VIL X Output Disable X VIH X High Z
Rev. 8.2 07/10 Micross Components reserves the right to change products or specifi cations without notice. AC READ WAVEFORMS(1,2,3) NOTES: 1. CE\\ may be delayed to tACC-tCE after the address transition without impact on tACC. 2. OE\\ may be delayed to tCE-tOE after the falling edge of CE\\ without impact on tCE or by tACC-tOE after an address change without inpact on tACC. 3. tDF is specifi ed from OE\\ or CE\\ whichever occurs fi rst (CL = 5pF). ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (-55oC < TA < +125oC or -40oC to +85oC; Vcc = 5V +10%) MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX Address to Output Delay tACC 120 140 150 200 250 300 ns CE\\ to Output Delay tCE 120 140 150 200 250 300 ns OE\\ to Output Delay tOE 0 50 0 55 0 55 0 55 0 55 0 55 ns CE\\ or OE\\ to Output Float tDF 55 55 55 55 55 55 ns Output Hold from OE\\, CE\\ or Address, whichever comes first tOH 0 0 0000 n s UNITS 200 250 300DESCRIPTION 140120 150 SYMBOL tACC tOHtOE tDFtCE tRCtRC OUTPUT VALID ADDRESS VALIDADDRESS CE/ OE\\ DQ tCE tOE tACC tOH tDF
Rev. 8.2 07/10 Micross Components reserves the right to change products or specifi cations without notice. WRITE CYCLE NO 1. (Chip Enable Controlled) WRITE CYCLE NO 2. (Write Enable Controlled) ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC WRITE CHARACTERISTICS (-55oC < TA < +125oC; Vcc = 5V +10%) Symbol Parameter Min Max Units tWC Write Cyce Time 10 ms tAS Address Set-up Time 4 ns tAH Address Hold Time 50 ns tDS Data Set-up Time 50 ns tDH Data Hold Time 10 ns tWP Write Pulse Width 100 ns tBLC Byte Load Cycle Time 150 μs tWPH Write Pulse Width High 50 ns tDH tDS tWPHtWPHtWPtWP tCHtCS tWC tAH tWC tAS tOEHtOES DATA VALID ADDRESS VALID OE\\ ADDRESS WE\\ CE\\ DQ tOES tAS tCS tWP tDS tDH tWPH tCH tOEH tWC tAH tDH tDS tWPHtWPHtWPtWP tCHtCS tAH tAS tOEHtOES DATA VALID OE\\ ADDRESS CE\\ WE\\ DQ tOES tAS tCS tWP tAH tDS tDH tWPH tCH tOEH
Rev. 8.2 07/10 Micross Components reserves the right to change products or specifi cations without notice. PAGE MODE WRITE WAVEFORMS(1,2) NOTES: 1. A7 through A16 must specify the page address during each high to low transition of WE\\ (or CE\\). 2. OE\\ must be high only when WE\\ and CE\\ are both low. 3. VD - Valid Data 4. V A - Valid Address PAGE MODE CHARACTERISTICS Symbol Parameter Min Max Unit tAS, tOES Address, OE\\ Set-Up time 4 ns tAH Address, Hold time 50 ns tCS Chip Select Set-up Time 0 ns tCH Chip Select Hold Time 0 ns tWP Write Pulse Width (WE\\ or CE\\) 100 ns tDS Data Set-up Time 50 ns tDH, tOEH Data, OE\\ Hold Time 10 ns CHIP ERASE WAVEFORMS tS = 5 msec (min.) tW = tH = 10 msec (min.) VH = 12.0V + 0.5V VIH VIL VH VIH VIH VIL CE\\ OE\\ WE\\ tW tS tH tWC tDH tDS tAH tAS tBLCtBLCtWPHtWPHtWPtWP BYTE 0 BYTE 1 BYTE 2 BYTE 3 BYTE127 BYTE 126 VA VA VA VAVA VA VD VD VD VD VD VDVD VA VD VD OE CE\\ WE\\ A0 - A16 DATA tWP tAH tAS tDS tDH tWPH tBLC tWC
Rev. 8.2 07/10 Micross Components reserves the right to change products or specifi cations without notice. Software Data Protection Enable Algorithm(1) Software Data Protection Disable Algorithm(1) NOTES: 1. Byte Data Format: I/O7 - I/O0, I/ Address Format: A14 - A0 (Hex) 2. Write Protect state will be active at end of write even if no other data is loaded. 3. Write Protect state will be deactivated at end of period even if no other data is loaded. 4. 1 to 128 bytes of data are loaded. Load Data 55 to Address 2AAA Writes Enabled(2) Enter Data Protect State Load Data AA to Address 5555 Load Data XX to Any Address (4) Load Data A0 to Address 5555 Load Last Byte to Last Address 1. A0-A14 of the selected I/O bytes must conform to the addressing sequence for the first three bytes as shown above. 2. After the command sequence has been issued and a page write operation follows, the page address inputs (A7-A16) of the selec ted I/O bytes must be the same for each high to low transition of WE\\ (or CE\\). 3. OE Must be high only when WE\\ and CE\\ are both low. SOFTWARE PROTECTED PROGRAM CYCLE WAVEFORM(1)(2)(3) BYTE ADDRESS PAGE ADDRESS WE\\ A0-A6 A7-A16 DA TA tWC BYTE 127BYTE 126BYTE 0 A055AA tDHtDS 5555 2AAA 5555 tAS tAH tBLCtWPHtWP OE\\ CE\\ Load Last Byte(s) ;Exit Data Protect State(3) Load Data >AA Address >5555 Load Data >55 Address >2AAA Load Data >80 Address >5555 Load Data >AA Address >5555 Load Data >55 Address >2AAA Load Data >20 Address >5555 Load Data XX Any Address (4) Load Last Byte(s) Last Address
Rev. 8.2 07/10 Micross Components reserves the right to change products or specifi cations without notice. DATA POLLING CHARACTERISTICS(1) NOTES: 1. Toggling either OE or CE or Both OE and CE will operate toggle bit. 2. Beginning and ending state of I/O6 will vary. 3. Any address location may be used but the address should not vary. NOTES: 1. These parameters are characterized and not 100% tested. 2. See AC Read Characteristics. DATA POLLING WAVEFORMS TOGGLE BIT WAVEFORMS(1,2,3) NOTES: 1. These parameters are characterized and not 100% tested. 2. See AC Read Characteristics. TOGGLE BIT CHARACTERISTICS(1) WE\\ CE\\ OE\\ I/O7 A0 - A16 tOEH tDH tOE tWR High-Z An An An An An Symbol Parameter Min Max Units tDH Data Hold Time 10 ns tOEH OE\\ Hold Time 10 ns tOE OE\\ to Output Delay (2) 100 ns tWR Write Recovery Time 0 ns Symbol Parameter Min Max Units tDH Data Hold Time 10 ns tOEH OE\\ Hold Time 10 ns tOE OE\\ to Output Delay(2) 100 ns tOEPH OE\\ High Pulse 150 ns ICC Write Recovery Time 0 nstWR tOEHP tWRtWRtOEtDH tOEH HIGH Z WE\\ CE\\ OE\\ I/O 6 tOEH tDH tOE tWR tOEHP
Rev. 8.2 07/10 Micross Components reserves the right to change products or specifi cations without notice. Micross Case #703 (Package Designator Q) SMD 5962-94585, Case Outline M MECHANICAL DEFINITIONS* *All measurements are in inches. 4 x D2 4 x D1 4 x D b e Pin 1 SEE DETAIL A A DETAIL A MIN MAX A 0.123 0.200 A1 0.118 0.186 A2 0.005 0.020 b 0.013 0.017 B D D1 0.870 0.890 D2 0.980 1.000 D3 0.936 0.956 e R 0.005 --- L1 0.035 0.045
0.050 BSC
SYMBOL MICROSS PACKAGE SPECIFICATIONS
0.010 REF
0.800 BSC
B
Rev. 8.2 07/10 Micross Components reserves the right to change products or specifi cations without notice. Micross Package Designator Q3 MECHANICAL DEFINITIONS* *All measurements are in inches. D b e 0.015 Symbol Min Max A .200 A2 .010 .025 A3 .070 .080 b .013 .017 B D .800 BSC D1 .870 .890 D2 .980 1.00 e R L1 .035 .045 Dimensionsareininches. PACKAGESPECIFICATION .010REF .010TYP .050BSC AR B
Rev. 8.2 07/10 Micross Components reserves the right to change products or specifi cations without notice. MECHANICAL DEFINITIONS* *All measurements are in inches. Micross Case #904 (Package Designator P & PN) SMD 5962-94585, Case Outline 4 and 5 A L φb e φb1 4 x D Pin 66 e Pin 11 Pin 1 (identifi ed by 0.060 square pad) Pin 56 66 x φb2 MIN MAX A 0.135 0.181 A1 0.025 0.035 φb 0.016 0.020 φb1 0.045 0.055 φb2 0.065 0.075 D 1.065 1.085 D1/E1 e L 0.132 0.155
0.600 BSC
0.100 BSC
1.000 BSC
Rev. 8.2 07/10 Micross Components reserves the right to change products or specifi cations without notice. *AVAILABLE PROCESSES IT = Industrial Temperature Range -40 oC to +85oC XT = Extended Temperature Range -55 oC to +125oC 883C = Full Military Processing -55 oC to +125oC PACKAGE NOTES P = Pins 8, 21, 28, and 39 are grounds. PN = Pins 8, 21, 28, and 39 are no connects.
ORDERING INFORMATION
AS8E128K32 Q -120 /* AS8E128K32 Q3 -120 /* AS8E128K32 Q -140 /* AS8E128K32 Q3 -140 /* AS8E128K32 Q -150 /* AS8E128K32 Q3 -150 /* AS8E128K32 Q -200 /* AS8E128K32 Q3 -200 /* AS8E128K32 Q -250 /* AS8E128K32 Q3 -250 /* AS8E128K32 Q -300 /* AS8E128K32 Q3 -300 /* Device Number Package Type Speed ns Process AS8E128K32 AS8E128K32 P PN -120 -120 AS8E128K32 AS8E128K32 P PN -140 -140 AS8E128K32 AS8E128K32 P PN -150 -150 AS8E128K32 AS8E128K32 P PN -200 -200 AS8E128K32 AS8E128K32 P PN -250 -250 AS8E128K32 AS8E128K32 P PN -300 -300 EXAMPLE: AS8E128K32Q-250/XT EXAMPLE: AS8E128K32P-200/883C
Rev. 8.2 07/10 Micross Components reserves the right to change products or specifi cations without notice. MICROSS TO DSCC PART NUMBER CROSS REFERENCE* Micross Package Designator Q Micross Part # SMD Part # AS8E128K32Q-120/883C 5962-9458506HMA AS8E128K32Q-120/883C 5962-9458506HMC AS8E128K32Q-140/883C 5962-9458505HMA AS8E128K32Q-140/883C 5962-9458505HMC AS8E128K32Q-150/883C 5962-9458504HMA AS8E128K32Q-150/883C 5962-9458504HMC AS8E128K32Q-200/883C 5962-9458503HMA AS8E128K32Q-200/883C 5962-9458503HMC AS8E128K32Q-250/883C 5962-9458502HMA AS8E128K32Q-250/883C 5962-9458502HMC AS8E128K32Q-300/883C 5962-9458501HMA AS8E128K32Q-300/883C 5962-9458501HMC Micross Part # SMD Part # AS8E128K32P-120/883C 5962-9458506H5A AS8E128K32P-120/883C 5962-9458506H5C AS8E128K32P-140/883C 5962-9458505H5A AS8E128K32P-140/883C 5962-9458505H5C AS8E128K32P-150/883C 5962-9458504H5A AS8E128K32P-150/883C 5962-9458504H5C AS8E128K32P-200/883C 5962-9458503H5A AS8E128K32P-200/883C 5962-9458503H5C AS8E128K32P-250/883C 5962-9458502H5A AS8E128K32P-250/883C 5962-9458502H5C AS8E128K32P-300/883C 5962-9458501H5A AS8E128K32P-300/883C 5962-9458501H5C AS8E128K32PN-120/883C 5962-9458506H4A AS8E128K32PN-120/883C 5962-9458506H4C AS8E128K32PN-140/883C 5962-9458505H4A AS8E128K32PN-140/883C 5962-9458505H4C AS8E128K32PN-150/883C 5962-9458504H4A AS8E128K32PN-150/883C 5962-9458504H4C AS8E128K32PN-200/883C 5962-9458503H4A AS8E128K32PN-200/883C 5962-9458503H4C AS8E128K32PN-250/883C 5962-9458502H4A AS8E128K32PN-250/883C 5962-9458502H4C AS8E128K32PN-300/883C 5962-9458501H4A AS8E128K32PN-300/883C 5962-9458501H4C *Micross part number is for reference only. Orders received referencing the SMD part number will be processed per the SMD.
Rev. 8.2 07/10 Micross Components reserves the right to change products or specifi cations without notice. DOCUMENT TITLE 128K x 32 EEPROM EEPROM Memory Array Rev # History Release Date Status