AS73211-AQFM

AS73211 OSRAM | Alldatasheet

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Technical content

XYZ True Color Sensor with I²C Interface v3-01 • 2018-Feb-07

Datasheet • PUBLIC DS000556 • v3-01 • 2018-Feb-07 65 │ 2 Content Guide 6 Typical Optical Characteristics .. 13 7.5 Continuous Measurement Mode – CONT.. 16

7.7 Synchronous Measurement Mode – SYNS 19

7.8 Synchronous Measurement Start and End

7.15 Conversion Time Measurement in SYND

7.21 I²C General Procedure to start with the

8.4 Configuration Register - CREG1, CREG2

12 Soldering & Storage Information 60

Datasheet • PUBLIC DS000556 • v3-01 • 2018-Feb-07 65 │ 3

1 General Description

The AS73211 is a low power, low noise integrated color sensor. Three channels convert light signals via photodiodes to a digital result and realize a continuous or triggered measurement. In front of the three photodiodes there are optical filter mounted for X-, Y- and Z-signals respectively. The irradiance responsivity can be set in a range of 12 steps by a factor of two for each step. The conversion time is internally controlled over a wide range of 15 steps by a factor of two for each step. With the input pin (SYN) the conversion time can be externally controlled to adapt the measurement to the given environment and time base. With its irradiance responsivity factor and conversion time the AS73211 supports an overall huge dynamic range up to 3.43E+10 (resolution multiplied by gain range). It achieves an accuracy of up to 24-bit signal resolution (internal via I²C and shifter 16 bit) with an irradiance responsivity per count down to 0.5pW/cm². 𝐷𝑦𝑛𝑎𝑚𝑖𝑐 𝑅𝑎𝑛𝑔𝑒 = 𝑀𝐴𝑋 𝑚𝑒𝑎𝑠𝑢𝑟𝑒𝑎𝑏𝑙𝑒 𝑣𝑎𝑙𝑢𝑒 = 𝑀𝑎𝑥. 𝐹𝑢𝑙𝑙 𝑆𝑐𝑎𝑙𝑒 𝑅𝑎𝑛𝑔𝑒 𝑀𝐼𝑁 𝑚𝑒𝑎𝑠𝑢𝑟𝑒𝑎𝑏𝑙𝑒 𝑣𝑎𝑙𝑢𝑒 = 𝑀𝑖𝑛. 𝐿𝑒𝑎𝑠𝑡 𝑆𝑖𝑔𝑛𝑖𝑓𝑖𝑐𝑎𝑛𝑡 𝐵𝑖𝑡 For high robustness at high sensitivity, the AS73211 has an inherent ripple rejection of the 50Hz / 60Hz external disturbances. Automatic Power Down (sleep function) between subsequent measurements offers operation with very low current consumption. Further, a synchronized mode and other control modes adjustable by user programming can be used. The supported operating modes of the AS73211 are:

• CMD Mode – single measurement and conversion (controlled via I²C interface),
• CONT Mode – continuous measurement and conversion (periodically recurring measuring cycles) start and stop controlled via I²C interface,
• SYN[x] Modes - synchronized measurement and conversion:
• [SYNS Mode] synchronization of start via control signal at pin SYN,
• [SYND Mode] synchronization of start and stop of measuring cycles via control signal at pin SYN. The conversion data is accessed by the I²C interface with programmable slave addresses via 16-bit / 400 kHz fast mode. The measurement of the actual conversion time for an external triggered measurement can be performed. The measurement modes will not affect the settings of the irradiance responsivity and conversion time. Further, the converter supports functions like Power Down and Standby, therefore it is suitable for mobile applications. Based on the high flexibility the AS73211 is suitable as an optical converter for three different wave­lengths. The device achieves a high dynamic range in back light applications and in the measurements of integral intensity of pulsed light. That makes the color sensors excellently suited for photometry applications (brightness, color coordinate and/or color temperature), for determining current values for control of spectrally mixed LED light sources or as sensors for display and (back)light calibration and mobile devices for light measurement. The AS73211 contains an integrated temperature sensor for rough compensation of the thermic behavior of light sources. The device is available in a small SMD package.

Datasheet • PUBLIC DS000556 • v3-01 • 2018-Feb-07 65 │ 4

1.1 Key Benefits & Features

The benefits and features of AS73211, XYZ True Color Sensor with I²C Interface, are listed below: Figure 1: Added Value of Using AS73211 Benefits Features Light control measurement based on CIE 1931/DIN 5033 JENCOLOR® interference filter technology Brightness, color coordinate and/or color temperature control High dynamic range up to 3.43E+10 (16 … 24 Bit ADC) Usable under poor lighting conditions High sensitivity up to 2.1M counts/(µW/cm²) Smallest LSB 0.5pW/cm² Mobile applications Low power operation, Power on Reset, Power down and standby, small QFN package Harsh environmental applications -40°C up to 125°C operation temperature range Temperature compensation On-chip temperature sensor

1.2 Applications

• LED lighting control management for solid-state lighting applications (SSL)
• Cabin lighting, daylight management / Human and Color Centric Lighting (HCL and CCL)
• Ambient light color detection / correction
• (O)LED display aging compensation and dynamic display color balancing
• Portable light color measurement
• Digital light projection (DLP)
• Printer, Smartphone, PDA, tablet PCs, LCD-TVs, digital picture, frames, digital cameras color enhancement
• Photometry (brightness, color coordinate and/or color temperature)

1.3 Block Diagram

Figure 2 shows the main components of the AS73211. The photodiodes convert the incoming light to a photo current and with subsequent current-to-digital converter to digital data. An internal reference generator provides all necessary references for the A/D conversion and the photodiodes by using an external resistor REXT at pin REXT. The results of the A/D conversion are stored in three 16-bit registers and can be accessed via I²C interface. For the externally triggered start or start and stop of the measurement, the input pin SYN can be used. The output READY reflects the status of the conversion. The internal temperature sensor delivers the on-chip temperature, stored as 12-bit value in a 16-bit register, which can be accessed via I²C interface, too. The pins A0 and A1 set the I²C slave address. Separated analog and digital power supply and ground pins reduces noise coupling.

Datasheet • PUBLIC DS000556 • v3-01 • 2018-Feb-07 65 │ 5 Figure 2: Functional Blocks of AS73211

Ordering Information

Datasheet • PUBLIC DS000556 • v3-01 • 2018-Feb-07 65 │ 6

2 Ordering Information

Ordering Code Package Marking Delivery Form Delivery Quantity AS73211-AQFM QFN16 AS73211 Tape & Reel 500pcs/reel AS73211-AQFT QFN16 AS73211 Tape & Reel 3000pcs/reel

Datasheet • PUBLIC DS000556 • v3-01 • 2018-Feb-07 65 │ 7

3 Pin Assignment

3.1 Pin Diagram

Figure 3: Pin Diagram of AS73211 in QFN16 Package (top view)

Datasheet • PUBLIC DS000556 • v3-01 • 2018-Feb-07 65 │ 8

3.2 Pin Description

Figure 4: Pin Description of AS73211 Pin Number Pin Name Pin Type (1) Description 1 - 2 VSSA P Analog ground

3 A0 DI Variable I²C slave address bit 0

4 SCL DI I²C clock input

5 SDA D_I/O_OD I²C data input / output; open drain output stage

6 VSSD P Digital ground

7 VDDD P Digital power supply

8 READY DO Conversion status; configurable as push pull or open

drain output stage (default push pull)

9 SYN DI Input for external controlled conversion

10 A1 DI Variable I²C slave address bit 1

11 – 12 VSSA P Analog ground

13 REXT A_I/O External reference resistor

14 VDDA P Analog power supply

15 – 17 VSSA P Analog ground (1) Explanation of abbreviations: DI Digital input DO Digital output D_I/O_OD Digital input / output open drain P Power pin A_I/O Analog

Datasheet • PUBLIC DS000556 • v3-01 • 2018-Feb-07 65 │ 9

4 Absolute Maximum Ratings

Stresses beyond those listed under “Absolute Maximum Ratings“ may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated under “Operating Conditions” is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Figure 5: Symbol Parameter Min Max Unit Comments Electrical Parameters VDD Power Supply Voltage -0.5 5.0 V VDDA and VDDD DIFFVDD Supply Voltage Difference -0.3 0.3 V VDDD-VDDA Input and Output Voltages -0.5 VDD+0.5 V A0, A1, SCL, SDA, SYN, READY Electrostatic Discharge ESDHBM Electrostatic Discharge HBM ± 500 V JS-001-2014 ESDCDM Electrostatic Discharge CDM ± 500 V JEDEC JESD22-C101F Oct 2013 Temperature Ranges and Storage Conditions TA Operating Ambient Temperature -40 125 °C TSTRG Storage Temperature Range -55 125 °C RHNC Relative Humidity (non- condensing) 5 85 % MSL Moisture Sensitivity Level 3 Maximum floor life time of 168h (1) The reflow peak soldering temperature (body temperature) is specified according to IPC/JEDEC J-STD-020 “Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices.” The lead finish for Pb- free leaded packages is “Matte Tin” (100 % Sn)

Electrical Characteristics

Datasheet • PUBLIC DS000556 • v3-01 • 2018-Feb-07 65 │ 10

5 Electrical Characteristics

All limits are guaranteed. The parameters with Min and Max values are guaranteed with production tests or SQC (Statistical Quality Control) methods. All voltages with respect to ground (GND). Device parameter are guaranteed at VDD=3.3V and TA=25°C unless otherwise noted. Figure 6: Symbol Description Condition Min Typ Max Unit TOP Operating Temperature -40 125 °C VDD Power Supply Voltage VDDA and VDDD 2.7 3.3 3.6 V DIFFVDD Supply Voltage Difference VDDD-VDDA -0.3 0 0.3 V REXT External Resistor at Pin REXT REXT (TCREXT ≤ 50ppm/K) 3.267 3.3 3.333 MΩ IVDD Current Consumption Active mode during measurement 1.5 2 mA IVDDSB Standby Current Consumption Standby state 800 µA IVDDPD Power Down Current Consumption Power down state 1 µA VIH Input High Level A0, A1, SCL, SYN 0.7 VDDD VIL Input Low Level A0, A1, SCL, SYN 0.3 VDDD VOH Output High Level READY IOHL ≤ 3mA 0.8 VDDD VOL Output Low Level SDA, READY IOHL ≤ 4mA 0.4 V SDA, READY IOHL ≤ 4mA 0.6 V IOHL Output Drive Strength Concerning to VOH and VOL 3 6 mA IILEAK Input Leakage Current VSSD ≤ VIN ≤ VDDD -10 10 µA fCLKMIN Min. Internal Clock Frequency CREG3:CCLK = 00b 0.75 1 1.3 MHz fCLKMAX Max. Internal Clock Frequency CREG3:CCLK = 11b 6 8.2 10 MHz TSTARTSB Startup Time after Standby state Until start of first measurement 4 5 µs TSTARTPD Startup Time after Power Down state Until start of first measurement 1.2 2 ms TSYNDEL SYN Trigger Delay From falling SYN-edge to start of measurement 3 1/fCLK TSYN SYN Negative or Positive Pulse Width SYN recognized as start or end pulse of measurement 3 1/fCLK T_abs_err Temperature Absolute Error -10 10 K

Datasheet • PUBLIC DS000556 • v3-01 • 2018-Feb-07 65 │ 12 Symbol Description Condition Min Typ Max Unit DDARK Dark ADC Count Value Ee = 0; GAIN = 2048x TCONV = 64ms @ fCLKMIN; 8 counts ENOB Effective Number of Bits GAIN = 64x TCONV = 64ms @ fCLKMIN; 15.4 bit Figure 10: Optical Characteristics of AS73211 Symbol Description Condition Min Typ Max Unit ReGAIN2048 Irradiance Responsivity for CREG1:GAIN = 2048x X channel λ = 600nm 4730 counts/ (µW/cm²) Y channel λ = 555nm 4392 Z channel λ = 445nm 8179 ReGAIN1 Irradiance Responsivity for CREG1:GAIN = 1x X channel λ = 600nm 2.309 counts/ (µW/cm²) Y channel λ = 555nm 2.145 Z channel λ = 445nm 3.994 FSRGAIN2048 Full Scale Range of detectable Irradiance for CREG1:GAIN = 2048x X channel λ = 600nm 13.854 µW/cm² Y channel λ = 555nm 14.919 Z channel λ = 445nm 8.012 FSRGAIN1 Full Scale Range of detectable Irradiance for CREG1:GAIN = 1x X channel λ = 600nm 28372 µW/cm² Y channel λ = 555nm 30554 Z channel λ = 445nm 16408

Typical Optical Characteristics Datasheet • PUBLIC DS000556 • v3-01 • 2018-Feb-07 65 │ 13

6 Typical Optical Characteristics

The filter response curves based on the CIE 1931 standard are shown in the figure below. Figure 11: Typical Spectral Sensitivity of XYZ True Color Sensor AS73211 (1) Typical characteristic sensitivity. Spectral tolerance filter curve Δλ(λ) typ. <±1%*λ determined by the deviation between the filter curve’s centroid wavelength and the CIE 1931 2° Standard Observer centroid wavelength. (2) See chapter 13.2 Angle of Incidence Figure 12: Photodiode Array

Datasheet • PUBLIC DS000556 • v3-01 • 2018-Feb-07 65 │ 14

7 Functional Description

Three internal photodiodes with different spectral sensitivity with three A/D converters. The irradiance responsivity Re and the time of conversion TCONV are user defined and determined by registers CREG1:GAIN and CREG1:TIME and should be adapted to the application of interest. At the end of each conversion, the digital equivalents of the filtered input light signal regarding to the sensors area are stored in the output registers (MRES1 … MRES3). Additionally a temperature sensor works in parallel to the three optical channels, delivering the on-chip temperature at the end of conversion. The pin READY remains at low logic level all the time during the conversion. The rising edge and the following high logic level of READY signalize the end of conversion. Internal information related to the conversion is available in a status register, too.

7.1 Operational States

The AS73211 operates in two different states “Configuration” and “Measurement”. The three least significant bits of the Operational State Register (OSR) as Device Operational State (DOS) defined the current state. After applying the power supply voltage including power-on reset or after software reset the AS73211 stays in Power Down state. It is ready to be programmed via I²C interface. Switching off Power Down (OSR:PD set to ‚0‘) the AS73211 starts up in Configuration state (CONFIG) or in Measurement state (MMODE) according to its DOS programming.

7.2 Configuration State

This state enables the access to the configuration registers (CREG1, CREG2, CREG3). Irradiance responsivity Re and conversion time TCONV can be determined by settings of registers CREG1:GAIN and CREG1:TIME as well as the kind of measurement mode can be chosen via register CREG3:MMODE. A measurement is not possible in this state and therefore no access to any measurement result registers.

7.3 Measurement State

In this state the light-to-digital conversion can be performed. The access to the output result registers is enabled, but at this time, there is no access possible to the configuration registers. Specific settings for the measuring task should be performed by programming the configuration registers before the measurement is started (see chapter 8.5). The change between Configuration and Measurement state can be performed by programming the DOS value of the operational state register OSR (see Figure 45). A change from Measurement state to Configuration state takes place immediately. Any active measurement is stopped and all output result registers and the status register are reset as well.

Datasheet • PUBLIC DS000556 • v3-01 • 2018-Feb-07 65 │ 15 Figure 13: Simplified State Diagram

7.4 Measurement Modes

There are four different modes available to perform the measurement. The register CREG3:MMODE (see Figure 50) defines the measurement mode that is performed by the device. It is generally recommended not to communicate via I²C during the conversion. Use pause times between two conversion cycles for data transfer via I²C interface. To support such a behavior a variable pause time TBREAK is implemented (register BREAK in Figure 52), which delays the start of the next conversion cycle in the measurement modes CONT, SYNS and SYND. I²C commands sent to the AS73211 always take effect after the complete I²C write cycle with an I²C Stop condition at the end. Power On VDD > VDD-POR Power down Configuration Measurement PD: “0” DOS: “010” PD: “0” DOS: “011” End of conversion DOS: “011”

Datasheet • PUBLIC DS000556 • v3-01 • 2018-Feb-07 65 │ 16

7.5 Continuous Measurement Mode – CONT

The A/D conversion is sequentially performed. The first conversion starts by setting the bit OSR:SS to ‚1‘. If the Power Down or Standby option is switched on, the device deactivates it and initializes the continuous measurement. The measurement can only be stopped by resetting the bit OSR:SS bit. Figure 14: State Machine CONT Mode The conversion time (TCONV) is determined by the content of the register CREG1:TIME (see Figure 48). The rising edge of READY signalizes the end of each conversion and its available valid results Figure 48 shows the principle sequence for a measurement start in CONT mode, while waiting in Measurement state shows IDLE: CONT PAUSE CONFIG POWDOWN PD = 0 MMODE = 0 SB = 0 PD = 0 MMODE = 0 SB = 0 M_IDLE STANDBY PD = 0 SS = 1 MMODE = 1 SB = 1 PD = 0 MMODE = 0 SB = 0 PD = 0 MMODE = 1 SB = 1PD = 0 SS = 1 MMODE = 1 SB = 0 PD = 0 MMODE = 1 SB = 0 PD = 1PD = 0 SS = 1 MMODE = 1 SB = 0 PD = 0 SS = 1 MMODE = 1 SB = 1 PD = 1 PD = 1 PD = 0 MMODE = 0 PD = 1 PD = 0 MMODE = 0 SB = 1 SS = 1 SB = 0 PD = 1 PD = 0 SS = 0 MMODE = 1 SB = 0 MMODE = 1 PD = 1 Power-up PD = 0 MMODE = 0 SB = 0

Datasheet • PUBLIC DS000556 • v3-01 • 2018-Feb-07 65 │ 17 1. OSR programming: 83h, start of continuous measurement via OSR:SS = ‚1‘, while device is already in measurement mode (OSR:DOS = 011b), 2. OSR programming: 03h, abortion of continuous measurement via OSR:SS = ‚0‘ – here while pause time TBREAK is already activated to get the last measurement results. It is recommended to read the measurement results during the break between two consecutive con- versions. This pause time TBREAK can be configured in steps of 8μs up to 2040μs long (see Figure 52). Please note that the break time should be long enough to prevent overlapping of data fetch activities with the measurement for avoiding measurement disturbances, which could cause distortions of the measurement results Figure 15: Principles Sequence for a Measurement Start in CONT Mode

7.6 Command Measurement Mode – CMD

The CMD mode enables a start of a single conversion. Each conversion starts by setting the bit OSR:SS to ‚1‘. The conversion time (TCONV) is determined by the content of the register CREG1:TIME (see Figure 48). Figure 16 shows the first measurement starting from the Configuration state by setting the bits of the Device Operational State (OSR:DOS) and Start/Stop (OSR:SS) at the same time with OSR = 83h. For the next measurement start OSR = 80h is set (only bit OSR:SS, OSR:DOS = 000b corresponds to NOP – no operation, see also Figure 45. The rising edge of READY signalizes the end of conversion and its valid output data can be read via the I²C interface (data fetch). IDLEPPAUSE MRES1 … MRES3 READY STATE I²C activity MEASUREMENT 1 data fetch start (OSR:SS ← ,1') IDLE RESULTS 1 RESULTS 2 data fetch stop (OSR:SS ← ,0') MEASUREMENT 2 TCONV TCONV TBREAK TBREAK aborted PAUSE

Datasheet • PUBLIC DS000556 • v3-01 • 2018-Feb-07 65 │ 18 Figure 16: State Machine CMD Mode

Datasheet • PUBLIC DS000556 • v3-01 • 2018-Feb-07 65 │ 19 Figure 17 shows the principle sequence for a measurement start in CMD mode coming from Configuration state and waiting in Measurement state between the measurements is shown as IDLE: 1. OSR programming: 83h, change to Measurement state, start of measurement via OSR:SS = ‚1‘, 2. “Automatically” OSR programming: 03h, to reset bit OSR:SS to ‚0‘ at the end of conversion. Figure 17: Principle Sequence for a Measurement Start in CMD Mode Coming From Configuration State

7.7 Synchronous Measurement Mode – SYNS

In this measurement mode, the input pin SYN acts as a trigger event for the start of A/D conversion. The falling edge at pin SYN starts the measurement. The conversion time (TCONV) is determined by the content of the register CREG1:TIME (see Figure 48). The pin READY signalizes the progress of conversion (see Figure 18) and its rising edge shows the end of conversion and its available valid results. The data fetch should be performed between the rising edge of signal READY and the next falling edge of signal SYN in order to allow distortion free measurement. SYN pulses during the programmed pause time TBREAK are ignored to avoid a start of the measurement during a running data fetch (see also Figure 52). The bit OSR:SS also takes effect in the SYNS mode, because the start of the measurement is only possible with OSR:SS = ‚1‘. Figure 18 shows the principle sequence for a measurement start in SYNS mode, OSR:DOS = 011b and OSR:SS = ‚1‘ already set and waiting in Measurement state is shown as IDLE. IDLEMEASUREMENT 2 RESULTS 1 MEASUREMENT 1CONFIGURATION IDLE TCONV data fetch MRES1 … MRES3 READY STATE I²C activity RESULTS 2 TCONV data fetch OSR:DOS = 011b start (OSR:SS ← ,1') clear (OSR:SS ← ,0') start (OSR:SS ← ,1')

Datasheet • PUBLIC DS000556 • v3-01 • 2018-Feb-07 65 │ 20 Figure 18: Principle Sequence for a Measurement Start in SYNS Mode, OSR:DOS = 011b and OSR:SS = ‚1‘

7.8 Synchronous Measurement Start and End Mode – SYND

In this mode, the signal at pin SYN controls the start and stop of a measurement completely. When the device is waiting in Measurement state and OSR:SS is set to ‚1‘ the first falling edge at pin SYN starts the measurement. Each following falling edge of signal SYN, which occurs within the conversion time, can continue or stop the measurement. The content of the register EDGES determines, which edge is the stopping one. That means the measurement will not stop until a certain number of falling edges at pin SYN passed within the conversion time. The value of register EDGES determines the number of edges (see Figure 19 and chapter “Register - EDGES”). Figure 19 shows the principle sequence for a measurement start in SYND mode. While waiting in Measurement state is shown as IDLE, after OSR:SS is set to ‚1‘ (see Figure 45) the AS73211 waits for signal SYN to start. The conversion time is set to 06h in register EDGES, during the pause time TBREAK falling edges at pin SYN are ignored. IDLESTATE MRES1 … MRES3 READY I²C activity SYN IDLE start MEASURMENT 2PAUSEMEASUREMENT 1 data fetch RESULTS 1 TCONV start TBREAK

Datasheet • PUBLIC DS000556 • v3-01 • 2018-Feb-07 65 │ 21 Figure 19: Principle Sequence for a Measurement Start in SYND Mode The conversion time (TCONV) is determined by the duration between the edges of start and stop of the signal SYN. If CREG2:EN_TM is set to ‚1‘, the register OUTCONV contains an equivalent amount of TCONV as counts of the internal clock. With the value of OUTCONV, the measurement results can be calculated more precisely (see chapter “Conversion Time Measurement in SYND Mode”).

7.9 Energy Saving Options

The usage of the energy saving options is consistent for all measurement modes. The signal path at pin READY always represents independent of wake-up times or synchronizing events at pin SYN concerning the internal clock, the real measurement process. Every measurement mode can be terminated with OSR:SS = ‚0‘ or changing to Configuration state at every time, whereas not completed A/D conversions are not stored. In case of both energy saving options Power Down state (POWDOWN) and Standby state (STANDBY) are switched on (OSR:PD = ‚1‘ and CREG3:SB = ‚1‘). The startup times (TSTARTPD and TSTARTSB) run one after the other after Power Down and Standby is switched off.

7.10 Power Down

Power Down is an option to reduce the power consumption. After applying the power supply voltage including power-on reset or after software reset the AS73211 stays in Power Down state. The clock generator and all analog parts of the device are turned off. The power consumption of the device is close to zero. The digital part of the AS73211 stays idle, but a full communication via the I²C interface is granted in Configuration state and Measurement state as well. IDSTATE READY I²C activity OSR 80h SYN IDLE PAUSE MEASUREMENT 2 TCONV MEASUREMENT 1 TBREAK RESULTS 1 data fetch RESULT 1 MRES1 … MRES3 IDLE OUTCONV

Datasheet • PUBLIC DS000556 • v3-01 • 2018-Feb-07 65 │ 23 2. OSR programming: 80h, start of the measurement as stated in the device’s configuration. Coming from Power Down state activated by OSR:PD = ‚1‘ the AS73211 is active switched on not until OSR:SS is set to ‚1‘ (together while or with OSR:DOS = 011b). That means the bit OSR:SS is a direct start condition for the CMD and CONT modes whereas for both SYN modes also the falling edge at pin SYN is necessary for the startup. The programmed measurement mode follows after startup marked by the falling edge of the signal path at pin READY. If the configuration even contains CREG3:SB = ‚1‘ (as the example of Figure 21shows), additionally after startup time TSTARTPD the wake-up time TSTARTSB of 4µs follows before the measurement starts. Figure 21: Principle Start of the Measurement from OSR:PD = ‚1‘ and CREG3:SB = ‚1‘ Figure 21 shows the principle start of the measurement from OSR:PD = ‚1‘ and CREG3:SB = ‚1‘: a) CREG3 programming: bit CREG3:SB = ‚1‘, b) OSR programming: C3h, start of the measurement with prior run of TSTARTPD and TSTARTS. The programmed energy saving option (before or when measurement is started or while the measurement runs) is switched on after the regular end of the measurement and storing of the results within the buffer registers. In case of an abortion of the measurement with OSR:SS = ‚0‘ or switching to Configuration state the energy saving option is switched on without saving any results.

7.11 Standby

Standby is another option for reducing the power consumption, but compared to Power Down less internal analog components are switched off to be able to get back active in a very short time. The digital part of the AS73211 stays idle, but a full communication via the I²C interface is granted in Configuration state and Measurement state as well. The bit CREG3:SB can only be changed in Configuration mode. The wake-up process is possible in combination with the start condition of the configured Measurement mode. Standby is automatically deactivated by starting the CMD or CONT TSTARTSB MEASUREMENTSCONFIGURATION POWDOWNSTATE I²C activity OSR C3h CREG3:SB ← ‚1' TSTARTPD STANDBY

Datasheet • PUBLIC DS000556 • v3-01 • 2018-Feb-07 65 │ 24 measurement mode by setting the bit OSR:SS to ‚1‘. In addition, for the measurement modes SYNS and SYND an initiated start is necessary by the falling edge of the signal at pin SYN. While starting the measurement the A/D conversion follows immediately after the wake-up time TSTARTSB of about 4µs. Figure 22 shows the principle start and stop sequence of a measurement after startup with OSR:PD = ‚0‘ and CREG3:SB = ‚1: a) CREG3 programming: bit CREG3:SB = ‚1‘, b) OSR programming: 02h, after startup continuing with Configuration mode, c) OSR programming: 83h, measurement start, wake-up and conversion, return to standby after measurement ends. Figure 22: Principle Start and Stop Sequence of a Measurement After Startup with OSR:PD = ‚0‘ and CREG3:SB = ‚1‘

7.12 Examples

For both modes CONT and SYN it is recommended to configure a pause time TBREAK (register BREAK of Figure 52) to avoid disturbances during the A/D conversion caused by I²C interface communication. The selectable pause time using register BREAK should be long enough, that all output results are read before the next conversion starts (automatically in CONT modus or synchronized via pin SYN in SYN modes). While the pause time TBREAK is running it is possible to save energy if the bit CREG3:SB is configured to ‚1‘. The wake-up time TSTARTSB of about 4µs is short compared to the necessary time for the I²C communication protocol represented by register BREAK. Figure 23 shows the principle sequence of CONT mode: if CREG3:SB is set to ‚1‘, saving energy is possible while the pause time TBREAK is activated for I²C interface communication. STANDBY CONFIGURATION POWDOWN MEASUREMENT STANDBYSTATE I²C activity OSR 83h OSR:PD ← ‚0' CREG3:SB ← ‚1' TSTARTPD TSTARTSB

Datasheet • PUBLIC DS000556 • v3-01 • 2018-Feb-07 65 │ 27 The following example of a SYNS mode shows a correct measurement procedure but with an unfavorable chosen application. After start of measurement with bit OSR:SS = ‚1‘ only the red marked falling edges (see Figure 27) at pin SYN are accepted as start condition, because of the too tight distances of the SYN edges a lot of falling edges are ignored during startup phase (TSTARTPD), conversion time (TCONV) and pause time (TBREAK). Figure 27: Principle Sequence of Measurement in SYNS Mode (OSR:PD , OSR:SS are set to ‚1‘) Continuously occurring SYN pulses (e.g. generated by a PWM controlling in measurement mode SYND) are ignored in Configuration state and while pause time TBREAK (see Figure 28) is activated. It is recommended to increase the default value of register BREAK accordingly, if the time reference result OUTCONV must be read via I²C interface. The conversion time is given by register EDGES, but as shown in Figure 28 the real conversion time is always represented by TCONV at pin READY. Furthermore, the output result OUTCONV can be used to get the right measurement result (see also chapters “Transfer Function” and “Conversion Time Measurement in SYND Mode”). Figure 28 shows the principle sequence of measurement in SYND mode ready for wake-up after switch off Power Down state with OSR:PD = ‚0‘ and setting of OSR:SS to ‚1‘ in Configuration state, then waiting for start via pin SYN (with exemplary settings of EDGES = 06h and CREG3:SB = ‚1‘ for energy saving while pause time TBREAK). READY SYN MRES1 … MRES3 start start RESULTS 1 POWDOWNSTATE MEASPAUSE POWDOWNMEASUREMENT 1 TBREAK I²C activity OSR C0h data fetch TCONV TSTARTPD TSTARTPD

Datasheet • PUBLIC DS000556 • v3-01 • 2018-Feb-07 65 │ 28 Figure 28: Principle Sequence of Measurement in SYND Mode Ready for Wake-Up After Switch Off Power Down State

7.13 Transfer Function

In generally the implemented A/D converter represents a delta-sigma converter, which performs charge balancing between the input light at the photodiodes and an internal reference. The input currents of the photodiodes result in pulse density modulated digital signals, further filtered by counters up to 24 bits. At the end, each channel’s counter status represents a digital equivalent of the average input light irradiance regarding to the channel’s sensor area within the conversion time interval. The input light irradiance can be calculated from the measurement result by: Equation 1: MRESN FSR R MRESE CLK E e e e  Equation 2: MRESfT FSR E CLKCONV E e e  STANDBYSB PAUSE MEASUREMENT 2CSTATE READY TCONV MEASUREMENT 1 TSTARTSB TBREAK MRES1 … MRES3 RESULTS 1 I²C activity data fetch RESULT 1 OSR 83h SYN TSTARTSB CONFIGURATION STANDBY OUTCONV

Datasheet • PUBLIC DS000556 • v3-01 • 2018-Feb-07 65 │ 29 MRES: Digital output value of the conversion (content of output registers MRES1 to MRES3) Ee: Input light irradiance regarding to the photodiode’s area within the conversion time interval FSREe: Full Scale Range of detectable input light irradiance Ee Re: Irradiance responsivity (see Figure 14) TCONV: Conversion time interval NCLK: Number of clock cycles within the conversion time interval TCONV (see Figure 13) fCLK: Clock frequency In the CONT, CMD and SYNS modes the conversion time TCONV is internally generated1.In the SYND mode the conversion time is defined by the timing of the external pulses at SYN pin and the number of pulses stored in the register EDGES (see Figure 19 chapter “Conversion time measurements in SYND mode” and chapter “Register - EDGES”). The number of clock counts within this interval is a constant number, which keeps the output result independent of the internal clock frequency. In this case the input light irradiance Ee regarding to the photodiodes area of the channel can be represented by the Equation 1. In SYND mode, the Equation 2 represents the externally generated conversion time TCONV and the conversion result. If the conversion time measurement is activated (CREG2:EN_TM = ‚1‘) the number of clock counts within the externally given conversion time can also be internally captured. So the input light irradiance Ee regarding to the photodiode’s area of the channel can be calculated as: Equation 3: MRESOUTCONV FSRE eE e  MRES: Digital output value of the conversion (content of output registers MRES1 to MRES3) Ee: Input light irradiance regarding to the photodiode’s area within the conversion time interval FSREe: Full Scale Range of detectable input light irradiance Ee OUTCONV: Conversion time duration expressed as the number of clock counts within this time. In this way, the input light irradiance can be measured independently of the internal frequency and furthermore external conversion time variations in SYND mode. The calculation of the input light irradiance by Equation 3 is more precise than the result of Equation 2 because the tolerances of the clock frequency fCLK are eliminated. The irradiance responsivity Re and 1 The system clock is internally generated and is subject to technological tolerances. So the clock frequency may vary, which must be considered when calculating the time to be programmed (e. g. registers BREAK for pause time TBREAK or CREG1:TIME for conversion time TCONV).

Datasheet • PUBLIC DS000556 • v3-01 • 2018-Feb-07 65 │ 30 internal conversion time TCONV are determined by the content of register bits CREG1:GAIN and CREG1:TIME (see Figure 48). Their values directly determine the sensitivity, the LSB value and the full-scale range (FSR) of the detectable irradiance Ee of the A/D conversion. Figure 29: X-Channel (λ = 600nm) Programmable FSR and LSB of the Detectable Input Light Irradiance Ee with CREG1:TIME Programming from 0 to 7 and CREG1:GAIN Programming from 0 to 11 – CONT, CMD and SYNS Mode TIME (1) 0 1 2 3 4 5 6 7 NCLK(1) 1024 2048 4096 8192 16384 32768 65536 131072 TCONVms 1 2 4 8 16 32 64 128 RESOLbit 10 11 12 13 14 15 16 17 GAIN(1) FSR [µW/cm²] of detectable irradiance Ee (channel X) 2048x 13.854 6.927 1024x 27.707 13.854 512x 55.414 27.707 256x 110.828 55.414 128x 221.657 110.828 64x 443.314 221.657 32x 886.628 443.314 16x 1773.255 886.628 8x 3546.510 1773.255 4x 7093.020 3546.510 2x 14186.041 7093.020 1x 28372.081 14186.041 GAIN (1) LSB [nW/cm²] – least significant bit of FSR (channel X) (1) TIME (TCONV) – given by CREG1:TIME = 0 … 7 dec, NCLK – number of clock cycle within conversion time TCONV, RESOL – Resolution of internal A/D conversion, GAIN = 1x given by CREG1:GAIN = 11dec up to GAIN = 2048x given by CREG1:GAIN = 0dec (see Figure 48)

Datasheet • PUBLIC DS000556 • v3-01 • 2018-Feb-07 65 │ 31 Figure 30: X-Channel (λ = 600nm) Programmable FSR and LSB of the Detectable Input Light Irradiance Ee with CREG1:TIME Programming from 8 to and CREG1:GAIN Programming from 0 to 11 – CONT, CMD and SYNS Mode TIME (1) 8 9 10 11 12 13 14 15 RESOLbit 18 19 20 21 22 23 24 10 GAIN(1) FSR [µW/cm²] of detectable irradiance Ee (channel X) GAIN(1) LSB [nW/cm²] – least significant bit of FSR (channel X) (1) TIME (TCONV) – given by CREG1:TIME = 8 … 15 dec, NCLK – number of clock cycle within conversion time TCONV, RESOL – Resolution of internal A/D conversion, GAIN = 1x given by CREG1:GAIN = 11dec up to GAIN = 2048x given by CREG1:GAIN = 0dec (see Figure 48)

Datasheet • PUBLIC DS000556 • v3-01 • 2018-Feb-07 65 │ 32 Figure 31: Y-Channel (λ = 555nm) Programmable FSR and LSB of the Detectable Input Light Irradiance Ee with CREG1:TIME Programming from 0 to 7 and CREG1:GAIN Programming from 0 to 11 – CONT, CMD and SYNS Mode TIME(1) 0 1 2 3 4 5 6 7 NCLK(1) 1024 2048 4096 8192 16384 32768 65536 131072 TCONVms 1 2 4 8 16 32 64 128 RESOLbit 10 11 12 13 14 15 16 17 GAIN(1) FSR [µW/cm²] of detectable irradiance Ee (channel Y) 2048x 14.919 7.460 1024x 29.838 14.919 512x 59.677 29.838 256x 119.354 59.677 128x 238.707 119.354 64x 477.415 238.707 32x 954.830 477.415 16x 1909.659 954.830 8x 3819.319 1909.659 4x 7638.637 3819.319 2x 15277.275 7638.637 1x 30554.549 15277.275 GAIN(1) LSB [nW/cm²] – least significant bit of FSR (channel Y) (1) TIME (TCONV) – given by CREG1:TIME = 0 … 7 dec, NCLK – number of clock cycle within conversion time TCONV, RESOL – Resolution of internal A/D conversion, GAIN = 1x given by CREG1:GAIN = 11dec up to GAIN = 2048x given by CREG1:GAIN = 0dec (see Figure 48).

Datasheet • PUBLIC DS000556 • v3-01 • 2018-Feb-07 65 │ 33 Figure 32: Y-Channel (λ = 555nm) Programmable FSR and LSB of the Detectable Input Light Irradiance Ee with CREG1:TIME Programming from 8 to 15 and CREG1:GAIN Programming from 0 to 11 – CONT, CMD and SYNS Mode TIME(1) 8 9 10 11 12 13 14 15 RESOLbit 18 19 20 21 22 23 24 10 GAIN(1) FSR [µW/cm²] of detectable irradiance Ee (channel Y) GAIN(1) LSB [nW/cm²] – least significant bit of FSR (channel Y) (1) TIME (TCONV) – given by CREG1:TIME = 8 … 15 dec, NCLK – number of clock cycle within conversion time TCONV, RESOL – Resolution of internal A/D conversion, GAIN = 1x given by CREG1:GAIN = 11dec up to GAIN = 2048x given by CREG1:GAIN = 0dec (see Figure 48).

Datasheet • PUBLIC DS000556 • v3-01 • 2018-Feb-07 65 │ 34 Figure 33: Z-Channel (λ = 445nm) Programmable FSR and LSB of the Detectable Input Light Irradiance Ee with CREG1:TIME Programming from 0 to 7 and CREG1:GAIN Programming from 0 to 11 – CONT, CMD and SYNS Mode TIME(1) 0 1 2 3 4 5 6 7 NCLK(1) 1024 2048 4096 8192 16384 32768 65536 131072 TCONVms 1 2 4 8 16 32 64 128 RESOLbit 10 11 12 13 14 15 16 17 GAIN(1) FSR [µW/cm²] of detectable irradiance Ee (channel Z) 2048x 8.012 4.006 1024x 16.024 8.012 512x 32.048 16.024 256x 64.097 32.048 128x 128.194 64.097 64x 256.387 128.194 32x 512.774 256.387 16x 1025.548 512.774 8x 2051.097 1025.548 4x 4102.193 2051.097 2x 8204.387 4102.193 1x 16408.773 8204.387 GAIN(1) LSB [nW/cm²] – least significant bit of FSR (channel Z) (1) TIME (TCONV) – given by CREG1:TIME = 0 … 7 dec, NCLK – number of clock cycle within conversion time TCONV, RESOL – Resolution of internal A/D conversion, GAIN = 1x given by CREG1:GAIN = 11dec up to GAIN = 2048x given by CREG1:GAIN = 0dec (see Figure 48).

Datasheet • PUBLIC DS000556 • v3-01 • 2018-Feb-07 65 │ 35 Figure 34: Z-Channel (λ = 445nm) Programmable FSR and LSB of the Detectable Input Light Irradiance Ee with CREG1:TIME Programming from 8 to 15 and CREG1:GAIN Programming from 0 to 11 – CONT, CMD and SYNS Mode TIME(1) 8 9 10 11 12 13 14 15 RESOLbit 18 19 20 21 22 23 24 10 GAIN(1) FSR [µW/cm²] of detectable irradiance Ee (channel Z) GAIN(1) LSB [nW/cm²] – least significant bit of FSR (channel Z) (1) TIME (TCONV) – given by CREG1:TIME = 8 … 15 dec, NCLK – number of clock cycle within conversion time TCONV, RESOL – Resolution of internal A/D conversion, GAIN = 1x given by CREG1:GAIN = 11dec up to GAIN = 2048x given by CREG1:GAIN = 0dec (see Figure 48).

Datasheet • PUBLIC DS000556 • v3-01 • 2018-Feb-07 65 │ 36 In the SYND mode, the maximum value of the conversion result depends on the external controlled conversion time. This maximum achievable count is equal to OUTCONV and differs from the full-scale count achievable in CMD, CONT and SYNS mode. The value of CREG1:TIME defines the number of clock counts during the conversion time. It defines the conversion time duration and maximal resolution of the A/D conversion. This is valid for the CONT, CMD and SYNS mode. In the SYND mode the value of CREG1:TIME does not have any meaning for the conversion time duration, because this time is externally defined. For values of CREG1:TIME higher than 6dec (0110b) TCONV becomes bigger than 216, which results in A/D conversions with a higher resolution starting from 17 bit up to 24 bit. Only the least 16 significant bits are further processed and stored in the result registers. Using the implemented divider (see chapter ”Divider”) helps to access the upper 8 bits, too. The value of CREG1:GAIN defines the A/D converter’s gain (see Figure 48 and FSR values in Figure 29 to Figure 34), which determines the sensor’s irradiance responsivity Re. The values of CREG1:GAIN of the referred tables are only valid for a clock frequency fCLK of 1MHz. For higher clock frequencies, some gain increments are not accessible. Figure 45 shows the valid gains in dependency of the chosen internal system clock via CREG3:CCLK. Figure 35: Achievable GAIN for Different Internal Clock Frequencies Chosen by CREG3:CCLK CREG3:CCLK [dec] 0 1 2 3 fCLK [MHz] 1.024 2.048 4.096 8.192 CREG1:GAIN [dec] adjustable GAIN 0 2048x 1024x 512x 256x 1 1024x 2 512x 512x 3 256x 256x 256x 4 128x 128x 128x 64x 5 64x 64x 64x 6 32x 32x 32x 16x 7 16x 16x 16x 8 8x 8x 8x 4x 9 4x 4x 4x 10 2x 2x 2x 1x 11 1x 1x 1x

Datasheet • PUBLIC DS000556 • v3-01 • 2018-Feb-07 65 │ 37 During the measurement cycle within the conversion time TCONV an input signal overdriving must be avoided, even if it occurs limited in time related to TCONV. In this case, the input light is too much concerning the chosen irradiance responsivity Re of the AS73211 tolerates. An internal function of the analog conversion monitors all channels during the conversion process in terms of the relation of input light and chosen irradiance responsivity Re determined via CREG1:GAIN. In case the input light of at least one of the channels is too much, the status bit STATUS:ADCOF (see Figure 54) is set to signalize the problem and the chosen GAIN of the A/D converter (CREG1:GAIN) has to be decreased for reducing the irradiance responsivity Re of the sensor.

7.14 Divider

For the purpose to expand the measurement ranges, an internal implemented divider or prescaler can be used to scale the results. This might be necessary if the resolution of the conversion is set to a value higher than 16 bits. If the digital divider is used the conversion result is downscaled according to: Equation 4: MRESN FSR R MRESE DIV CLK E e DIV e e [dec]1 [dec]1 MRES: Digital output value of the conversion (content of output registers MRES1 to MRES3) Ee: Input light irradiance regarding to the photodiode’s area within the conversion time interval FSREe: Full Scale Range of detectable input light irradiance Ee Re: Irradiance responsivity (see Figure 48) NCLK: Number of clock cycles within the conversion time interval TCONV (see Figure 48) 21+DIV[dec]: Value of the divider factor respectively prescaler (CREG2:DIV = 7…0), see Figure 49. The A/D converters of the AS73211 operate with a resolution of 24 bits, but their results are only provided as 16-bit wide values. The divider allows to read out the otherwise not available upper 8 bits, depending on the value of CREG2:DIV, if CREG2:EN_DIV is set to ‚1‘. Therefore, the divider acts as feature to digitally downscale the converter gain, but with a larger full scale range (FSR). The effective dynamic range of the device is increased without changing the conversion time.

Datasheet • PUBLIC DS000556 • v3-01 • 2018-Feb-07 65 │ 38 Figure 36: Relation of the Measurement Result to the Conversion Time Without Divider Respectively Prescaler Figure 36 shows the width of the register for the conversion time (OUTCONV), which represents the internal resolution of the A/D conversion. Furthermore the measurement result (MRES[1…3]) is shown, which is 16 bits wide. For all conversion times from 210 to 216 there is no need to use the divider, because OUTCONV is limited to the conversion time length. For conversion times bigger than 216 the conversion result is longer than 16 bits. Without the function of the divider, the result contains always the 16 least significant bits. Now the divider makes it possible to access most significant bits by shifting the 16-bit resolution of the measurement result over the possible range of the resolution given by the conversion time register (OUTCONV). Figure 37 shows an example, where CREG2:DIV = 2dec and therefore the divider factor is 23. MRES corresponds now to the bits 18 to 3 of register OUTCONV and therefore the Least Significant Bits and the Full Scale Range are 8 times higher than in case of the divider is not used. Figure 37: Relation of the Measurement Result to the Conversion Time with Enabled and Set Divider

7.15 Conversion Time Measurement in SYND Mode

In case of SYND measurement mode the conversion time is fully controlled by the external signal at pin SYN. The relative deviation of this time to the internal clock frequency2 can produce some deviations in the conversion result. However, this time can be measured in time units of the internal system clock extended up to 24 bits. It gives the opportunity to recalculate the measured input light more precisely (see chapter “Transfer Function”). Even further, the measurement result can be compensated for any deviation, which can occur in the clock frequency due to temperature or supply 2 The system clock is internally generated and is subject to technological tolerances, which means that clock frequencies of different devices may vary 012 11 10 9 8 7 6 5 4 3 2 119 18 17 16 15 14 132023 22 21 012 11 10 9 8 7 6 5 4 3 2 115 14 13 OUTCONV MRESCREG2:EN_DIV = ‚0' 012 11 10 9 8 7 6 5 4 3 2 119 18 17 16 15 14 132023 22 21 012 11 10 9 8 7 6 5 4 3 2 115 14 13 OUTCONV MRESCREG2:EN_DIV = ‚1' CREG2:DIV = 2 dec DIV = 7 … 2 … 0

Datasheet • PUBLIC DS000556 • v3-01 • 2018-Feb-07 65 │ 39 voltage variations. The conversion time measurement can be enabled by setting bit CREG2:EN_TM bit to ‚1‘ (see Figure 49). At the end of the conversion the result is stored into the output register OUTCONV (see Figure 53) synchronously with the measurement results (MRES). The stored value follows the relation: Equation 5: CLKCONV fTOUTCONV  The bit STATUS:OUTCONVOF of the status register (see Figure 54) shows an overflow of the conversion time counter OUTCONV. In case it happens and the conversion is still in process, the counter OUTCONV starts again at 0. For the calculation of the full scale range (FSR) see formula 1, 2 and 3 in chapter “Transfer function.

7.16 Temperature Measurement

Additional to the three optical channels a temperature measurement is done in parallel. The measurement result is available as TEMP of the output result registers. The resolution of the temperature measurement is 12 bits by a step size of 0.05 K per bit, which means 20 counts per Kelvin. The value of the chip temperature (silicon – measured in °C) is equal to: Equation 6: CCTEMPTCHIP  9.6605.0 With other words TEMP = 922h (2338dec) corresponds to 50°C as a reference point to start calculations. The temperature measurement is available in the measurement modes CONT, CMD and SYNS. By values of CREG1:TIME < 2dec the resolution of the temperature measurement is reduced, but in this case the output value of TEMP is internally corrected. In the SYND measurement mode it is important to enable the conversion time measurement (CREG2:EN_TM = ‚1‘) to get any result of the temperature measurement. In addition, the value of output register OUTCONV has to be more than 212 given by the external conversion time at pin SYN!

7.17 I²C Communication

The two wire serial interface is compatible to the fast mode I²C protocol with a bit rate up to 400kbit/s. The AS73211 exclusively operates as slave with its slave address [6:0] = (1, 1, 1, 0, 1, A1, A0). The two lowest-order bits are defined by the input pins A1 and A0, which allows to run four AS73211 on the same I²C bus at the same time. Within the AS73211 the pin SCL of the I²C interface is realized as input pin, wherefore in single master applications the I²C master could drive the SCL line with a push- pull stage. In all other cases the requirements for bus termination using standard pull-up according to

Datasheet • PUBLIC DS000556 • v3-01 • 2018-Feb-07 65 │ 41 Figure 40: I²C Write and Read Sequences

7.18 I²C Write Protocol

The start byte consists of the slave address followed by the bit R/W set to ‚0‘ for the write direction. The first byte after the start byte is always the device (see Figure 43) sends the address pointer to the internal register, which the master wants to write and acknowledge. When the master sends the next byte, it is stored in the internal register addressed before by the address pointer (REG ADDR.). Then acknowledge is sent by the device and it internally increments the address pointer to the next internal register address. Each next data byte, which is transferred by the master, is sequentially stored in the internal register. If the master generates a stop condition, the transfer is aborted and a new write sequence must be started from the beginning.

7.19 I²C Read Protocol

The start byte consists of the slave address followed by the bit R/W set to ‚0‘ for the write direction. The first byte after the start byte is always the device (see Figure 40) sends the address pointer to the internal register, which the master wants to read and acknowledge. After that, the master sends a repeated start condition and repeats the slave address but with the bit R/W reversed. Acknowledge is sent by the slave, which starts the data transfer to the master. The first transferred byte is the content of the internal register, which was pointed by the address pointer. The master acknowledges each transferred byte. The internal address pointer of the AS73211 automatically increments after each transferred register, which allows a sequentially read out of internal registers. If a not acknowledge occurs from the master it sends the stop condition next and the transfer is finished. read sequence: P: STOP cond. S SLAVE ADDR. R/W A REG ADDR. A A: acknowledge NA: not acknowledge S: START cond. Sr: repeated START cond. DATA A DATA NA P. . .Sr SLAVE ADDR.R/W A S: START cond. P: STOP cond. S SLAVE ADDR. R/W A REG ADDR. A DATA A DATA A P write sequence: . . . data transferred from slave to master data transferred from master to slave A: acknowledge DATA A DATA NA P. . .S SLAVE ADDR. R/W A short read sequence: S: START cond. P: STOP cond. A: acknowledge data transferred from slave to master data transferred from master to slave data transferred from slave to master data transferred from master to slave

Datasheet • PUBLIC DS000556 • v3-01 • 2018-Feb-07 65 │ 42 A shortened read sequence is also possible as shown in Figure 52. With the default of the bit OPTREG:INIT_IDX = ‚1‘ (see Figure 52) the internal address pointer starts at register address 2h if Measurement state is activated (OSR:DOS = 011b) and if Configuration state is activated (OSR:DOS = 010b) the internal address pointer starts at register address 0h.

7.20 I²C Addressable Register Space

Figure 41 shows the overview of the internal registers of the AS73211, which can be accessed via I²C interface. The control register bank can only be accessed in the configuration state and the registers are all 8 bits long. The output registers can only be accessed in the measurement state. They are read-only registers and 16 bits long, except OUTCONV, which is 24 bits long. OUTCONV is separated into two parts to fit into the output register’s structure. OUTCONV_L contains the first lower bytes and OUTCONV_H contains the most significant byte of OUTCONV in the first byte. The second byte is 00h. The AS73211 transfers the output data registers with the least significant byte first. The output register data transfer can start at any address. If during the sequential data read the highest possible address is achieved (CREG2:EN_TM = ‚0‘: address 4h; CREG2:EN_TM = ‚1‘: address 6h), the internal pointer is reset to the address 2h so that the next transferred data byte corresponds to the low byte of MRES1. However, the maximum number of output data transferred must not exceed a total number of bytes accessible at all (6 bytes if conversion time measurement (CREG2:EN_TM) is not activated otherwise 10 bytes). The register OUTCONV is only available in case of bit CREG2:EN_TM is set to ‚1‘. Figure 41: Register Overview ADDRESS (1) [hex] ACCESS IN CONFIGURATION STATE ACCESS IN MEASUREMENT STATE WRITE READ WRITE (1 BYTE) READ (2 BYTES)

0 OSR OSR OSR + STATUS

1 – – TEMP 2 – – – MRES1 (X) 3 – – MRES2 (Y) 4 – – MRES3 (Z) 5 – – OUTCONV_L (2)

6 CREG1 – OUTCONV_H (2)

7 CREG2 – –

8 CREG3 – –

9 BREAK – –

A EDGES – – B OPTREG – – (1) The 4 MSB bits of the register address are ignored. (2) OUTCONV is only available in SYND measurement mode with bit CREG2:EN_TM = ‚1‘. The least significant byte comes first.

Datasheet • PUBLIC DS000556 • v3-01 • 2018-Feb-07 65 │ 43

7.21 I²C General Procedure to start with the AS73211

After applying the power supply voltage the AS73211 is in the Configuration state, but in Power Down. The User can now set up the device for the application by writing the control registers. The success of the configuration can be proven by reading the control registers. Before a measurement can be started the state must be changed to the Measurement state. The last three bits (DOS) of the register OSR should be loaded with 011b. Now a conversion can be started with the measurement mode, which is selected by CREG3:MMODE. A falling slope of the output pin READY indicates the start. The rising edge at pin READY signalizes the end of conversion and the measurement results can be read via I²C communication. If a new configuration should be implemented, the device’s state has to be changed to Configuration state. Therefore the value 010b should be written into the bits OSR:DOS. This operation resets all measurement result registers to 00h, while the configuration registers keep their actual values. The new configuration can be done now. Figure 42: Example of Addressing the AS73211 to Read the Configuration Registers Starting at Address 0h with “automatically incremented values” After Power-On Reset or Software Reset (OSR:SW_RES) Figure 43: Example of Addressing the AS73211 to Read the Measurement Result Registers Starting at Address 4h The access of the result register bank with 2 byte each address (starting with the low byte), which is only possible within the Measurement state, has a special feature (see Figure 43). Reaching the last valid result register address (4h or 6h if SYND mode is activated with CREG2:EN_TM = ‚1‘) the next result register address is the default one 2h during read on. The setback to result register address 2h in Measurement mode does not take place if an address was set above the valid addressable space. S A0 06h A 9Ch A CBh SLAVE ADDR. R/W 1 1 1 0 1 0 0 E8h address CREG1 A write EDGESwrite BREAK 6h 7h P10h A 52h A 01h A Ahregister address: data transferred from slave to master data transferred from master to slave A: acknowledge NA: not acknowledge write CREG1 write CREG2 write CREG3 S: START cond. Sr: repeated START condition P: STOP cond. S A0 A SLAVE ADDR. R/W 1 1 1 0 1 0 0 E8h 04h address MRES3 Sr SLAVE ADDR. 1 1 1 0 1 0 0 E9h MRES1 A MRES1 read low byte read high byte R/W MRES3 AA MRES3 A reg. addr.: 4h read low byte read high byte . . . NA PA data transferred from slave to master data transferred from master to slave A: acknowledge NA: not acknowledge P: STOP cond.

Datasheet • PUBLIC DS000556 • v3-01 • 2018-Feb-07 65 │ 44

8 Register Description

The register contents defined in Figure 44 controls the AS73211 configuration and operational state.

8.1 Register Overview

Figure 44: Control Register Bank Address (1) [hex] Access (2) Name Reset Value (3) Description 0 rw OSR 42h Operational State Register 1 - - 00h (4) Reserved 2 ro AGEN 21h API generation 3 - - 00h Reserved 4 - - FFh Reserved 5 - - 80h Reserved 6 rw CREG1 A6h Configuration register 1 7 rw CREG2 40h Configuration register 2 8 rw CREG3 40h Configuration register 3 9 rw BREAK 19h Break time after measurement A rw EDGES 01h Edge count value in SYND mode B rw OPTREG 73h Options register (1) The 4 MSB bit of the register address are ignored. (2) ro: read-only, wo: write-only, rw: read-write (3) Default value after power-on reset and software reset. (4) Default value after power-on reset and software reset, but different, not relevant values after Power Down state is switched off.

8.2 Operational State Register – OSR

The register OSR defines the fundamental function (Device Operational State – DOS) of the AS73211 according to Figure 45. The register’s access is possible and necessary in both operational states – configuration and measurement. Here the initializing, wake up, switch to and start of measurement take place.

Datasheet • PUBLIC DS000556 • v3-01 • 2018-Feb-07 65 │ 45 Figure 45: Operational State Register (OSR) ¬– Address 0h OPERATIONAL STATE REGISTER NAME VALUE [b] OPERATIONAL STATE bit 7 SS 0 (1) Stop of the measurement

1 Start of the measurement (only possible with DOS =

MEASUREMENT) bit 6 PD 0 Power Down state switched OFF 1 (2) Power Down state switched ON bit 5 and 4 Reserved (3) bit 3 (4) SW_RES 0 (5) -

1 Software reset

bit 2 to 0 Device Operational State (6) (DOS) 00X NOP (no change of DOS) 010 (7) Operational state: CONFIGURATION

011 Operational state: MEASUREMENT

1XX NOP (no change of DOS) (1) Default value after power-on reset, software reset and change into Configuration state. (2) Default value after power-on reset and software reset. (3) The read value is always 00b as well as the recommended write value. (4) Bit 3 (SW_RES) is only active during write access, a read access always returns ‚0‘. (5) Default value after power-on reset and software reset (6) The OSR result of a register read process always returns 010b or 011b for the DOS bits. (7) Default value after power-on-reset, software reset or after mode change from measurement mode to configuration mode. DOS switches the operational state of the AS73211 between configuration and measurement. The configuration state enables the access to the control register bank (Figure 44) and no measurement takes place. The measurement the access to the result registers can only be performed in the measurement state. Then any access to the control register bank (except OSR) is not possible. If the operational state is switched back to the configuration state by DOS = 010b, the control registers keep their values. The measurement result registers are cleared. Any ongoing measurement is stopped immediately. The DOS sequence “NOP” (00Xb or 1XXb) does not change the operational state, but the values of the other written OSR bits are effective. SW_RES = ‚1‘ causes a software reset of the AS73211. A running measurement is stopped immediately and the AS73211 is set to configuration state. All registers are reset to their initial values. The start of a measurement is controlled by the value of bit SS. This bit is only interpreted in the measurement state. The Power Down state is controlled by the value of bit PD. The Power Down takes effect in both operational states: configuration and measurement. If the Power Down state is switched on while the device is in measurement state, the power down is only performed during the breaks between two conversions.

Datasheet • PUBLIC DS000556 • v3-01 • 2018-Feb-07 65 │ 46 Figure 46: Examples for Programming the Operational State Registers at Address 0h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SS PD SW_RES DOS Operational State 0 1 - - 0 0 1 0 Configuration state (Power Down state switched on) 42h 0 0 - - 0 0 1 0 Configuration state (Power Down state switched off) 02h 0 0 - - 0 0 1 1 Measurement state (Power Down state switched off) 03h 1 0 - - 0 0 1 1 Measurement state and Start of measurement (Power Down state switched off) 83h 1 0 - - 0 0 0 0 Provided that Measurement state is active – Start of measurement (Power Down state switched off) 80h 0 1 - - 0 0 1 1 Measurement state (Power Down state switched on) 43h 1 1 - - 0 0 1 1 Measurement state, Start of measurement and internal startup (“overwrite” of PD = ‚1‘) C3h 1 1 - - 0 0 0 0 Provided that Measurement state is active – Start of measurement and internal startup (“overwrite” of PD = ‚1‘) C0h (0) (1) - - 1 (0) (1) (0) Software reset 0Ah

8.3 API Generation Register – AGEN

The value of this read only register indicates the generation of the Control Register Bank. The register’s value changes whenever any formal modification is introduced to the Control Register Bank. This case indicates that the Application Programming Interface (API) has been changed. The default value for the AS73211 is 21h. Figure 47: API Generation Register (AGEN) – Address 2h AGEN NAME VALUE [b] DESCRIPTION bit 7 to 4 DEVID 0010 Device ID number bit 3 to 0 MUT 0001 Mutation number of Control Register Bank

Datasheet • PUBLIC DS000556 • v3-01 • 2018-Feb-07 65 │ 47

8.4 Configuration Register - CREG1, CREG2 and CREG3

CREG1:GAIN determines the irradiance responsivity of the sensor, which is different regarding to the channels X, Y and Z and in each case regarding to the used wave length λ. Internally the A/D converter runs with different gain factors concerning to the bit CREG1:GAIN (see also Figure 35). CREG1:TIME controls the conversion time duration as a multiple of the internal clock periods. In case of the start and end of a measurement are controlled externally via input trigger signal at pin SYN (equal to SYND mode), CREG1:TIME has no influence to the conversion time. In general the registers CREG2 and CREG3 define the measurement modes and additional device specific options. Figure 48: Configuration Register 1 (CREG1) – Address 6h CREG1 NAME VALUE [b] CONFIGURATION bit 7 to 4 GAIN INDEX X-channel λ = 0nm Y-channel λ = 555nm Z-channel λ = 445nm CREG1:TIME = 1010b (1024ms) CREG3:CCLK = 00b (1MHz) Full Scale Range of detectable irradiance Ee [µW/cm²] Effective Least Significant Bit (LSB) of Full Scale Range [nW/cm²] 0000 GAINX = 2048x 0.866 0.0132 GAINY = 2048x 0.932 0.0142 GAINZ = 2048x 0.501 0.0076 0001 GAINX = 1024x 1.732 0.0264 GAINY = 1024x 1.865 0.0285 GAINZ = 1024x 1.002 0.0153 0010 GAINX = 512x 3.463 0.0528 GAINY = 512x 3.730 0.0569 GAINZ = 512x 2.003 0.0306 0011 GAINX = 256x 6.927 0.1057 GAINY = 256x 7.460 0.1138 GAINZ = 256x 4.006 0.0611 0100 GAINX = 128x 13.854 0.2114 GAINY = 128x 14.919 0.2276 GAINZ = 128x 8.012 0.1223 0101 GAINX = 64x 27.707 0.4228 GAINY = 64x 29.838 0.4552 GAINZ = 64x 16.024 0.2445 0110 GAINX = 32x 55.414 0.8456 GAINY = 32x 59.677 0.9106 GAINZ = 32x 32.048 0.4890

Datasheet • PUBLIC DS000556 • v3-01 • 2018-Feb-07 65 │ 48 CREG1 NAME VALUE [b] CONFIGURATION 0111 GAINX = 16x 110.828 1.6911 GAINY = 16x 119.354 1.8212 GAINZ = 16x 64.097 0.9780 1000 GAINX = 8x 221.657 3.3822 GAINY = 8x 238.707 3.6424 GAINZ = 8x 128.194 1.9561 1001 GAINX = 4x 443.314 6.7644 GAINY = 4x 477.415 7.2848 GAINZ = 4x 256.387 3.9122 1010 (1) GAINX = 2x 886.628 13.5289 GAINY = 2x 954.830 14.5695 GAINZ = 2x 512.774 7.8243 1011 GAINX = 1x 1773.255 27.0577 GAINY = 1x 1909.659 29.1391 GAINZ = 1x 1025.548 15.6486 bit 3 to 0 TIME VALUE [dec] Conversion Time (fCLK = 1.024MHz) TCONV [ms] Number of clocks 0000 0 1 1024 210 0001 1 2 2048 211 0010 2 4 4096 212 0011 3 8 8192 213 0100 4 16 16384 214 0101 5 32 32768 215 0110 (1) 6 64 65536 216 0111 7 128 131072 217 1000 8 256 262144 218 1001 9 512 524288 219 1010 10 1024 1048576 220 1011 11 2048 2097152 221 1100 12 4096 4194304 222 1101 13 8192 8388608 223 1110 14 16384 16777216 224 1111 15 1 1024 210 (1) Default value after power-on reset and software reset.

Datasheet • PUBLIC DS000556 • v3-01 • 2018-Feb-07 65 │ 49 Figure 49: Configuration Register 2 (CREG2) – Address 7h CREG2 NAME VALUE [b] CONFIGURATION bit 7 Reserved (1) bit 6 EN_TM 0 In combination with SYND mode the internal measurement of the conversion time is disabled and no temperature measurement takes place. 1 (2) Internal measurement of the externally defined conversion time via SYN pulse in SYND mode is enabled (OUTCONV results are generated as well as temperature values for output register TEMP). bit 5 to 4 Reserved (1) bit 3 EN_DIV 0 (2) Digital divider of the measurement result registers is disabled

1 Digital divider of the measurement result registers is

enabled (might be needed @ CREG1:TIME > 6 dec) bit 2 to 0 DIV Value of the divider (21+DIV[dec]) 000 (2) 21 001 22 010 23 011 24 100 25 101 26 110 27 111 28 (1) The default value after power-on reset and software reset is ,0‘ as well as the recommended write value. (2) Default value after power-on reset and software reset. In SYND mode, the conversion time is externally controlled via pin SYN. In that case the bit CREG2:EN_TM enables the counting of internal clocks within the external given conversion time as well as the access to the output register OUTCONV, which contains the counting result. It is possible to count a number of clocks up to 24 bits. In case of this function is not used in SYND mode (equal to CREG2:EN_TM = ,0‘) no result for temperature measurement is generated. The values for output register TEMP are not valid. The bit CREG2:EN_DIV enables the internal prescaler, which could be interesting for conversion times more than 16 bits (CREG1:TIME ≥ 0111b) and in case of SYND mode is used. The value of CREG2:DIV is only valid with CREG2:EN_DIV = ,1‘. Then the measurement range is extended while the resolution of the 16-bit register results is reduced at the same time (see Divider). Thus it is also possible to generate complete measurement results for conversion times from 217 to 224 system clocks (CREG1:TIME). If the chosen value of the prescaler is too small, a counter overflow could occur, which is shown by the bit STATUS:MRESOF of the result register bank.

Datasheet • PUBLIC DS000556 • v3-01 • 2018-Feb-07 65 │ 50 Figure 50: Configuration Register 3 (CREG3) – Address 8h CREG3 NAME VALUE [b] CONFIGURATION bit 7 to 6 MMODE 00 CONT mode (continuous measurement) 01 (1) CMD mode (measurement per command)

10 SYNS mode (externally synchronized start of

measurement)

11 SYND mode (start and end of measurement are externally

synchronized) bit 5 Reserved (2) bit 4 SB 0 (1) Standby is switched OFF

1 Standby is switched ON

bit 3 RDYOD 0 (1) Pin READY operates as Push Pull output

1 Pin READY operates as Open Drain output

bit 2 Reserved (2) bit 1 to 0 CCLK 00 (1) Internal clock frequency fCLK = 1.024MHz 01 Internal clock frequency fCLK = 2.048MHz 10 Internal clock frequency fCLK = 4.096MHz 11 Internal clock frequency fCLK = 8.192MHz (1) Default value after power-on reset and software reset. (2) The default value after power-on reset and software reset is ,0‘ as well as the recommended write value. The bits CREG3:MMODE specify the measurement mode, which should be compatible to the given application. The bit CREG3:SB controls the operational state Standby of the AS73211. Within Standby state the power consumption of the device is reduced, but the internal circuit is ready to continue after 4 µs wake-up time by switching off Standby. With bit CREG3:RDYOD the output pin READY can be changed from push pull to open drain behavior. The open drain output allows running two or more AS73211 at the same time connected to one READY line with pull-up resistor. As long as one device still measures, the READY line is low active. The internal clock frequency fCLK is controlled by the bits of CREG3:CCLK. Higher clock rates result in shorter conversion times for the measurement. But take care of CREG1:GAIN – with higher frequencies than 1 MHz in some cases the irradiance responsivity is reduced (see Figure 35).

Datasheet • PUBLIC DS000556 • v3-01 • 2018-Feb-07 65 │ 51

8.5 Register – BREAK

The register BREAK defines the time between two consecutive measurements of CONT, SYNS and SYND mode. The default value of register BREAK is 19h. The value 0h results in a minimum time of three clocks of fCLK. Figure 51: Register BREAK – Address 9h BREAK NAME VALUE [dec]

DESCRIPTION

(25) (1) Pause time TBREAK between two measurements (except CMD mode): from 0 (2) to 2040 μs, step size 8 μs (1) Default value after power-on reset and software reset. (2) The value 0h results in a minimum time of 3 clocks of fCLK.

8.6 Register – EDGES

The register EDGES becomes operative in SYND mode. After a measurement was started in SYND mode it defines the necessary number of additional falling edges at input SYN until the conversion is terminated. The value EDGES = ‚0‘ is not allowed and results in the initial value ‚1’.

8.7 Register – OPTREG

The register bit OPTREG:INIT_IDX allows to communicate via I²C with simple masters, which do not support the I²C Repeated START condition. In this case the start address for a read operation can only be set by a complete write access with I²C STOP condition at the end. For this kind of simple I²C masters the bit INIT_IDX has to be ‚0‘. Reading of data starts then at the given index address. After each data transfer the index address is incremented. With INIT_IDX set to ‚1‘ each short read operation starts at the default address 2h in Measurement mode and 0h in Configuration mode. The setting of the internal read index address by writing to a register address followed by I²C Repeated START condition works as usual. After each data transfer the index address is incremented. Please see also chapter “I²C Read Protocol”.

Datasheet • PUBLIC DS000556 • v3-01 • 2018-Feb-07 65 │ 52 Figure 52: Register OPTREG – Address Bh OPTREG NAME VALUE [b] N bit 7 to 1 - 0111001 (1) Reserved bit 0 INIT_IDX 0 Defining the index address is only possible via write sequence and not affected by I²C STOP condition, which is necessary, if the I²C master does not support the I²C Repeated START condition. 1 (2) Each I²C STOP condition sets the internal register address to the default value. After writing an index address, it is possible to change the data direction for reading using I²C Repeated START condition. (1) Default value after power-on reset and software reset, but different, not relevant values after changing CREG1:GAIN or CREG3:CCLK. The recommended write value is 0000000b in case of OPTREG:INIT_IDX should be changed. (2) Default value after power-on reset and software reset.

8.8 Output Register Bank

All output result registers are 16-bit registers. The registers read access is only possible if state Measurement is activated. One exception offers register OSR, which is writable too. In that case one byte is assigned to address 0h (see also chapter “Operational State Register – OSR”). But the reading access of address 0h in Measurement state results in a first byte for OSR information and a second byte for STATUS information. Figure 53: Output Result Register Bank ADDRESS(1) [hex] ACCESS(2) NAME NUMBER OF BITS 0 rw OSR 8 (1) Operational State Register ro STATUS 8 (1) Status Register 1 ro TEMP 16 (2) Temperature Measurement Result (0h + 12bits for the value) 2 ro MRES1 16 (2) Measurement Result X-Channel 3 ro MRES2 16 (2) Measurement Result Y-Channel 4 ro MRES3 16 (2) Measurement Result Z-Channel 5 ro OUTCONVL 16 (2) Time reference, result of conversion time measurement (least significant byte and middle byte) 6 ro OUTCONVH 16 (2) Time reference, result of conversion time measurement (most significant byte and one empty byte with 00h) (1) Reading access of address 0h in measurement state results in a first byte for OSR information and a second byte for STATUS information. (2) Least Significant Byte comes first.

Datasheet • PUBLIC DS000556 • v3-01 • 2018-Feb-07 65 │ 53 Figure 54: Status Register (STATUS) – Address 0h BREAK NAME DESCRIPTION

7 OUTCONVOF (1)(2) Digital overflow of the internal 24 bit time reference OUTCONV

6 MRESOF(2) Overflow of at least one of the measurement result registers MRES1 …

5 ADCOF(2) Overflow of at least one of the internal conversion channels during the

measurement (e.g. caused by pulsed light) – analog evaluation is made

4 LDATA (3) Measurement results in the buffer registers were overwritten before they

were transferred to the output result registers. A transfer takes place as part of an I²C read process of at least one register of the output register bank.

3 NDATA (4) New measurement results were transferred from the temporary storage to

the output result registers.

2 NOTREADY ‚0‘: Measurement process is finished or not yet started

‚1‘: Measurement is in progress (corresponds to the inverted signal at output pin READY)

1 STANDBYSTATE ,0‘: Standby state is switched OFF

,1‘: Standby state is switched ON

0 POWERSTATE ,0‘: Power Down state is switched OFF

,1‘: Power Down state is switched ON (1) Overflow of the internal 24-bit conversion time counter – only possible in SYND mode with externally synchronized start and stop of conversion. (2) The status flag is generated while a measurement is in progress. It always matches to the actual results of the output register bank. (3) A reading process of the register STATUS always resets this status flag. (4) A reading process of the register STATUS and/or at least one result register always resets this status flag. The bit STATUS:OUTCONVOF shows an overflow of the 24 bit counter of the internal reference for the conversion time. This can only occur in SYND mode with CREG2:EN_TM = ‚1‘ and in case of accordingly long externally given conversion times. After a counter overflow the counter starts again from zero. The bit STATUS:MRESOF shows an overflow in one or more result registers of MRES1 … MRES3. This can only happen if the conversion time is longer than 216 (CREG1:TIME = 7…15 dec) in accordance with a higher input signal. The overflowed register stops at its maximum value FFFFh. With the bit STATUS:ADCOF an input signal overdriving is signalized, which could occur during the measurement cycle limited in time, so that no overflow of the result registers (MRESOF) is necessarily produced. But the measurement results are not correct in this case. To eliminate this problem the irradiance responsivity Re of the sensor has to be decreased via CREG1:GAIN. The status bits OUTCONVOF, MRESOF and ADCOF always correspond to the actual content of the measurement result registers MRES1…3. The bits STATUS:LDATA and STATUS:NDATA show the status of the measurement results. At the end of each measurement cycle, the results of the counters are stored into buffer registers. The flag

Datasheet • PUBLIC DS000556 • v3-01 • 2018-Feb-07 65 │ 54 NDATA is set to ‚1‘ to show the update (see Figure 55). With the start of each I²C read operation the content of all buffer registers is transferred to the result registers. This ensures that during the I²C readout operation the values of the result registers do not change. As long as an I²C-reading of the measurement result registers is in process (no I²C stop condition has been sent), no further update of the measurement result registers concerning to newer data of the buffer registers will happen. The status bit NDATA is reset to ‚0‘ after reading the status register or at least one measurement result register. Figure 55: Update Time of the Status Register Bits for an Accurate Measurement and Read Behavior If the buffer registers contain new values (NDATA = ‚1‘) and then a new measurement finishes before an I²C reading process occurs, the new measurement results is stored in the buffer registers. The older measurement results are overwritten. The status bit LDATA as shown in Figure 56 indicates this. The LDATA bit is only reset to ‚0‘ by reading the status register, because it allows checking for the loss of information after multiple measurement cycles. IDLEMEASUREMENT 2 RESULTS 1 MEASUREMENT 1CONFIGURATION IDLE TCONV data fetch OSR = 83h start (OSR:SS ← ‚1') MRES1 … MRES3 READY STATE I²C activity RESULTS 2 TCONV start (OSR:SS ← ‚1') LDATA = ‚0' NDATA = ‚0' data fetch LDATA = ‚0' NDATA = ‚1' LDATA = ‚0' NDATA = ‚0' LDATA = ‚0' NDATA = ‚1' LDATA = ‚0' NDATA = ‚0'

Datasheet • PUBLIC DS000556 • v3-01 • 2018-Feb-07 65 │ 55 Figure 56: Update Time of the Status Register Bits, if Some Measurement Results Were Not Picked Up The status bits STATUS:STANDBYSTATE and STATUS:POWERSTATE always show the actual status of the internal control signals for Standby and Power Down. In both cases it can differ from the actual set bits CREG3:SB and OSR:PD, because of the behavior of the control signals while a measurement is in process. The reading of the 16-bit values of the output result registers always starts with the least significant byte. The measurement value TEMP at address 1h is a 12-bit value, but its higher 4 bits until 16 are filled up with 0h. For Measurement modes programmed with CREG1:TIME < 212 there is a TEMP result with a lower resolution. If the SYND mode is used and register OUTCONV is set inactive by CREG2:EN_TM = ‚0‘, any temperature measurement is not possible. In case of CREG2:EN_TM is enabled (‚1‘) the TEMP value is only valid for conversion times with ≥ 212 internal system clocks fCLK represented by register OUTCONV. Power-on reset, software-reset or return to Configuration state resets the complete output register bank. IDLEMEASUREMENT 2 RESULTS 1 MEASUREMENT 1CONFIGURATION IDLE TCONV MRES1 … MRES3 READY STATE I²C activity RESULTS 2 TCONV data fetch LDATA = ‚0' NDATA = ‚0' LDATA = ‚0' NDATA = ‚1' LDATA = ‚1' NDATA = ‚1' LDATA = ‚0' NDATA = ‚0' OSR = 83h start (OSR:SS ← ‚1') start (OSR:SS ← ‚1')

Application Information

Datasheet • PUBLIC DS000556 • v3-01 • 2018-Feb-07 65 │ 56

9 Application Information

9.1 Schematic

Figure 57 shows a typical application circuit. Digital and analog grounds should be routed separately onto the printed circuit board and must be connected together near the device. The die attach pad (no. 17) of the QFN16 must be connected to analog ground VSSA. Without this contact it can lead to errors of the sensor. Figure 57: Typical Application Circuit Please make sure that all specified components within the application circuit work according to their operating range and to the parameters in the data sheet. For example, voltage regulators (workspace load current, separated analog and digital or decoupled power supplies based on a common regulator) need special treatment to avoid noise or deviations during operation.

9.2 External Components

The AS73211 and its external components for references and/or power supply (e.g. reference resistor REXT) should be placed on the same PCB side.

Datasheet • PUBLIC DS000556 • v3-01 • 2018-Feb-07 65 │ 57

9.3 PCB Layout

The analog supply must be placed as close as possible to the AS73211. The connection between the analog and digital grounds must be beneath (LP level) and/or near the AS73211. The die-attach pad (exposed pad) of the QFN16 package (AS73211) must be connected to analog ground VSSA.

Datasheet • PUBLIC DS000556 • v3-01 • 2018-Feb-07 65 │ 58 Figure 58: (1) All dimensions are in millimeters. Angles in degrees. (2) Dimensioning and tolerancing conform to ASME Y14.5M-1994. (3) This package contains no lead (Pb). (4) This drawing is subject to change without notice. RoHS Green

Tape & Reel Information Datasheet • PUBLIC DS000556 • v3-01 • 2018-Feb-07 65 │ 59

11 Tape & Reel Information

Standard packing is tape and reel. Usually in a moisture barrier bag (MBB sealed aluminized envelope) with desiccant (e.g. silica gel) and humidity indicator card to protect them from ambient moisture during shipping, handling, and storage before use. This package has been assigned a moisture sensitivity level of MSL 3 and the devices should be stored under the following conditions:

• Temperature range 5°C to 50°C
• Relative humidity 60% maximum
• Total time 6 months from the date code on the aluminized envelope – if unopened
• Opening time 168 hours or less Figure 59: QFN16 Tape & Reel Dimensions

Soldering & Storage Information Datasheet • PUBLIC DS000556 • v3-01 • 2018-Feb-07 65 │ 60

12 Soldering & Storage Information

The die-attach pad 17 (exposed pad) of the QFN16 package must be connected to analog ground VSSA on PCB. Realize this before soldering by a conductive adhesive and bonding this pad of the sensor backside to a ground pad on the PCB. According to the JEDEC standard, the QFN16 package has been tested and has demonstrated the ability to be reflow-soldered to a PCB substrate. The solder reflow profile describes the expected maximum heat exposure of components during the solder reflow process of product on a PCB. Temperature is measured on top of component. The component should be limited to a maximum of three passes through this solder reflow profile. Figure 60: Profile Features According to JEDEC IPC/JEDEC J-STD-020D.1 (Pb-Free) RECOMMENDED DATA Time [s] from 150°C to 200°C (preheat) 60 – 120 100 Average ramp-up rate [°C/s] (200°C to peak temperature) maximum 3.0 0.5 – 1.0 Liquidus temperature [°C] Time [s] above liquidus (217°C) 217 60 – 150 217

110 Peak package body temperature [°C] maximum 260 ≤ 260

Time [s] within 5°C of the classification temperature minimum 30 35 – 45 Average ramp-down rate [°C/s] (peak temperature to 200°C) maximum 6.0 3.0 Time [s] from 25°C to peak temperature maximum 480 350 Do not exceed the recommended values shown in the table or following figure. For further information, see the JEDEC standard J-STD-020D.1. Figure 61: Solder Reflow Profile Graph Time 25 °C To Peak tS Time → Temperature → TL TP Tsmin Tsmax tLPreheat Area Max. Ramp Up Rate = 3 °C/s Max. Ramp Down Rate = 6 °C/s tP TC –5 °C Supplier tP Supplier TP ≥ TC User tP User TP ≤ TC TC TC –5 °C

Datasheet • PUBLIC DS000556 • v3-01 • 2018-Feb-07 65 │ 61

13.1 Narrowband Luminous Sources

The spectral filters of the color sensors are specialized for applications with broadband source of lighting >10nm. Please ask our sales team before utilizing our sensor in combination with narrowband luminous sources.

13.2 Angle of Incidence

The packaging of the sensor IC has an aperture angle (beam width) of nearly 90°. Traditional interference filter work depending on angle of incidence. Using an angle of incidence < 10° allows the best results with no filter shifts. This can be ensured by using lenses or optical holes that limit the angle of incidence to the sensor device < 10°. An angle of incidence of more than 10° results in a filter shift. The filter response and accuracy is distorted the greater the angle deviation is. Please note a filter deviation resulting from this fact can differ from standard observer function and/or from the filter functions specified in this document. Please ask our sales team for support.

13.3 Effects of Temperature

The specified operation temperature range and documented parameters regarding temperature influence are described in chapter “Absolute Maximum Ratings”. The functionality of the filters do not depend on any temperature changes. The temperature coefficient of the photo sensitivity and the dark current of the photodiodes need to be considered, since these have an influence on the sensor’s response in case of changing temperature.

13.4 Notes for Manufacturing

JENCOLOR® sensors are optoelectronic components operating at high precision, resolution and smallest currents of nA in operation and pA in standby. This must be considered in the development and manufacturing. So mechanical stress, EMC, dirt and moisture must be avoided. For manufacturing purposes we recommend completely removing moisture and dirtying (dirt and residue solder as solder) on the boards with JENCOLOR® sensors. This refers to residual moisture on / below the sensor and converter. In sensor operations residual moisture or residues of solder can lead to leakage currents and result in increased offset values. Offset means a lower resolution, lower accuracy and measuring inaccuracies in sensor mode. These have particular impact on small measurement signals from the sensor. If cleaning of a PCB with water is necessary then make sure to fully dry the board later on with suitable processes and technologies (e.g. baking 120°C, over 24h). This avoids residual moisture as reason for leakage currents and noise.

Datasheet • PUBLIC DS000556 • v3-01 • 2018-Feb-07 65 │ 62

13.5 Sensor Calibration

Since the main variables of color change upon the arrangement of the observer, the object and light - it is essential to optimize and calibrate color measurement tasks to the specific application, especially for absolute color measurements according to the CIE 1931/DIN 5033.The calibration has three functions. It converts the measured values from light-to-digital converter into the color space XYZ/xyY/Luv/Lab or others. Secondly, it compensates production-related tolerances of the individual sensors. Thirdly, the accuracy of the XYZ sensor is extremely sensitive to the opto-mechanical design and variations of the system in, which it resides. These influences need to be corrected as other (e.g. external) effects like temperatures or others can influence other components in the sensor system and therefore the overall sensor response. Depending on the application and system accuracy, a sensor calibration will be possible by an individual system or by an in-series calibration. In the process of calibration there are conditions, which are required to receive reliable results in the CIE 1931 color space. Using a standardized illumination source such as A, F2 and D65 as reference, the angle of incidence as well as the arrangement of sensor and illumination are important input variables of the calibration and determine the quality of the XYZ transformation. ams Sensors Germany offers special white papers and application notes to find an optimized application-specific solution (time, costs and quality) for calibration. Please ask our sales team. For calibration the (color) target, measured by a spectrometer (n * XYZ as absolute color values and reference) and the color sensor (n * ADC measured) must be known. By a simple coefficient matrix method the relationship between the measured sensors values and absolute color coordinates in CIE 1931 color space can be made: T (1) is the matrix of the reference measurement (XYZ values of spectrometer), S (EQ1) is the sensor signal matrix (ADC values of Sensor) and K is the transformation matrix (EQ2). After the transposition of S, a transformation matrix K (linear regression) is calculated (EQ2). The result (EQ3) is the correction matrix K, which is used to transform measured sensor values (ADC result of a color target) into the color space XYZ based in CIE 1931 (EQ4). Information Matrixes are not set up as a square matrix and depend on the number of targets n. Equation 7: n n n Z Y X Z Y X Z Y X T ... n n n adcZ adcY adcX adcZ adcY adcX adcZ adcY adcX S ... Equation 8:      TT SSSTK

Datasheet • PUBLIC DS000556 • v3-01 • 2018-Feb-07 65 │ 63 Equation 9: 321 321 321 zkykzk ykykyk xkxkxk K Equation 10: adcZ adcY adcX K Z Y X SENSOR SENSOR SENSOR XSENSOR, YSENSOR, and ZSENSOR are the corrected sensor values in the CIE system, which specifies the color and brightness of particular homogenous visual stimulus. adcX, adcY, adcZ are measured values of the sensor. Xn, Yn, Zn are by a spectrometer measured color coordinates of the target for the calibration. xk…, yk…, zk… are coefficients of the correction matrix.

Datasheet • PUBLIC DS000556 • v3-01 • 2018-Feb-07 65 │ 64 Document Status Product Status Definition Product Preview Pre-Development Information in this datasheet is based on product ideas in the planning phase of development. All specifications are design goals without any warranty and are subject to change without notice Preliminary Datasheet Pre-Production Information in this datasheet is based on products in the design, validation or qualification phase of development. The performance and parameters shown in this document are preliminary without any warranty and are subject to change without notice Datasheet Production Information in this datasheet is based on products in ramp-up to full production or full production which conform to specifications in accordance with the terms of ams AG standard warranty as given in the General Terms of Trade Datasheet (discontinued) Discontinued Information in this datasheet is based on products which conform to specifications in accordance with the terms of ams AG standard warranty as given in the General Terms of Trade, but these products have been superseded and should not be used for new designs Changes from previous version to current revision v3-01 Page Datasheet was updated to latest ams design

• Page and figure numbers for the previous version may differ from page and figure numbers in the current revision.
• Correction of typographical errors is not explicitly mentioned.

Datasheet • PUBLIC DS000556 • v3-01 • 2018-Feb-07 65 │ 65

15 Legal Information

Copyrights & Disclaimer Copyright ams AG, Tobelbader Strasse 30, 8141 Premstaetten, Austria-Europe. Trademarks Registered. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. Devices sold by ams AG are covered by the warranty and patent indemnification provisions appearing in its General Terms of Trade. ams AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein. ams AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with ams AG for current information. This product is intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by ams AG for each application. This product is provided by ams AG “AS IS” and any express or implied warranties, including, but not limited to the implied warranties of merchantability and fitness for a particular purpose are disclaimed. ams AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of ams AG rendering of technical or other services. RoHS Compliant & ams Green Statement RoHS Compliant: The term RoHS compliant means that ams AG products fully comply with current RoHS directives. Our semiconductor products do not contain any chemicals for all 6 substance categories, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, RoHS compliant products are suitable for use in specified lead-free processes. ams Green (RoHS compliant and no Sb/Br): ams Green defines that in addition to RoHS compliance, our products are free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material). Important Information: The information provided in this statement represents ams AG knowledge and belief as of the date that it is provided. ams AG bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. ams AG has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ams AG and ams AG suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Headquarters ams AG Tobelbader Strasse 30

8141 Premstaetten

Austria, Europe Tel: +43 (0) 3136 500 0 Please visit our website at www.ams.com Buy our products or get free samples online at www.ams.com/ICdirect Technical Support is available at www.ams.com/Technical-Support Provide feedback about this document at www.ams.com/Document-Feedback For sales offices, distributors and representatives go to www.ams.com/contact For further information and requests, e-mail us at ams_sales@ams.com