AS7261

AS7261 AMSOSRAM | Alldatasheet

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Technical content

[v1-00] 2016-Dec-30 Document Feedback AS7261 XYZ Chromatic White Color Sensor + NIR with Electronic Shutter and Smart Interface The AS7261is a chromatic white color sensor providing direct XYZ color coordinates consistent with the CIE 1931 2° Standard Observer color coordinates. It also maps the XYZ coordinates to the x, y (Y) of the 2-dimensional color gamut and scales the coordinates to the CIE 1976 u’v’ coordinate system. The device provides accurate Correlated Color Temperature (CCT) measurements and provides color point deviation from the black body curve for white light color in the delta u’ v’ coordinate system. It also integrates a Near-IR channel for other applications. LED drivers with programmable currents are provided for electronic shutter applications. The AS7261 integrates Gaussian filters into standard CMOS silicon via Nano-optic deposited interference filter technology and is packaged in an LGA package that provides a built in aperture to control the ligh t entering the sensor array. Control and spectral data access is implemented through either the I²C register set, or with a high level AT Spectral Command set via a serial UART. Ordering Information and Content Guide appear at end of datasheet. Key Benefits & Features The benefits and features of AS7261, XYZ Chromatic White Color Sensor + NIR with Electronic Shutter and Smart Interface are listed below: Figure 1: AS7261 Benefits and Features Benefits Features

• Calibrated Chromatic white data
• XYZ
• xy data (CIE 1931)
• DUV, u’v’ , uv (CIE 1976)
• CCT, LUX
• Simple text-based command interface via UART, or direct register read and write with interrupt on sensor ready option on I²C
• UART or I²C slave digital Interface
• Lifetime-calibrated sensing with minimal drift over time or temperature • Filter set realized by silicon interference filters
• No additional signal conditioning required • 16-bit ADC with digital access General Description

Document Feedback [v1-00] 2016-Dec-30 AS7261 − General Description

Applications

The AS7261 applications include:

• Color measurement and absorbance
• Color matching and identification
• Precision color tuning/calibration Block Diagram The functional blocks of this device are shown below: Figure 2: AS7261 Chromatic White Color System
• Electronic shutter control/synchronization • Programmable LED drivers
• Low voltage operation • 2.7V to 3.6V with I²C interface
• Small, robust package, with built-in aperture • 20-pin LGA package 4.5mm x 4.7mm x 2.5mm
• -40°C to 85°C temperature range Benefits Features 100nF RX / SCL_S GND LED_DRV SCK CSN_EE MISO MOSI VDD1 VDD2 AS7261 uP 10uF 3.3V 3.3V TX / SDA_S LED_IND 3.3V Flash Memory XYZ, NIR, C & D Sensors Light Source Light in Reflective Surface INT

[v1-00] 2016-Dec-30 Document Feedback AS7261 − Pin Assignments The device pin assignments are described below. Figure 3: AS7261 Pin Diagram (Top View) Figure 4: AS7261 Pin Description Pin # Pin Name Description 1 NC Not functional. Do not connect 2R E S N R e s e t , a c t i v e L O W

3 SCK SPI serial clock

4 MOSI SPI master out slave in

5 MISO SPI master in slave out

6 CSN_EE Chip Select for external serial Flash memory, Active LOW

7 CSN_SD Chip Select for SD Card Interface, Active LOW

8 I2C_ENB Select UART (Low) or I²C (High) Operation

9 NF Not Functional. Do not connect. Pin Assignments 61 0 1620

Document Feedback [v1-00] 2016-Dec-30 AS7261 − Pin Assignments 10 NF Not Functional. Do not connect.

11 RX/SCL_S RX (UART) or SCL_S (I ²C Slave) Depending on I2C_ENB

12 TX/SDA_S TX (UART) or SDA_S (I ²C Slave) Depending on I2C_ENB

13 INT Interrupt, Active LOW

14 VDD2 Voltage Supply

15 LED_DRV LED Driver Output for Driving LED, Current Sink

16 GND Ground

17 VDD1 Voltage Supply

18 LED_IND LED Driver Output for Indicator LED, Current Sink

19 NF Not Functional. Do not connect. 20 NF Not Functional. Do not connect. Pin # Pin Name Description

[v1-00] 2016-Dec-30 Document Feedback AS7261 − Absolute Maximum Ratings Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated under Electrical Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Figure 5: Absolute Maximum Ratings Symbol Parameter Min Max Units Comments Electrical Parameters VDD1_MAX Supply voltage VDD1 -0.3 5 V Pin VDD1 to GND VDD2_MAX Supply voltage VDD2 -0.3 5 V Pin VDD2 to GND VDD_IO Input/output pin voltage -0.3 VDD + 0.3 V Input/output pin to GND I_scr Input current (latch-up immunity) ±100 mA JESD78D Electrostatic Discharge ESDHBM Electrostatic discharge HBM ±1000 V JS-001-2014 ESDCDM Electrostatic discharge CDM ±500 V JSD22-C101F Temperature Ranges and Storage Conditions Tstrg Storage temperature range -40 85 °C Tbody Package body temperature 260 °C IPC/JEDEC J-STD-020. The reflow peak soldering temperature (body temperature) is specified according IPC/JEDEC J-STD-020 “Moisture/Reflow Sensitivity Classification for Non-hermetic Solid State Surface Mount Devices” RH NC Relative humidity non-condensing 58 5 % MSL Moisture sensitivity level 3 Represents a 168 hours max. floor life time Absolute Maximum Ratings

Document Feedback [v1-00] 2016-Dec-30 AS7261 − Electrical Characteristics All limits are guaranteed with VDD = VDD1 = VDD2 = 3.3V, TAMB = 25°C. The parameters with min and max values are guaranteed with production tests or SQC (Statistical Quality Control) methods.VDD1 and VDD2 must be sourced from the same power supply. Figure 6: Symbol Parameter Conditions Min Typ Max Unit General Operating Conditions VDD1 /VDD2 Voltage operating supply UART interface 2.97 3.3 3.6 V VDD1 /VDD2 Voltage operating supply I²C interface 2.7 3.3 3.6 V TAMB Operating temperature -40 25 85 °C IVDD Operating current 5 mA Internal RC Oscillator FOSC Internal RC oscillator frequency 15.7 16 16.3 MHz tJITTER Internal clock jitter @25°C 1.2 ns Temperature Sensor DTEMP Absolute accuracy of the internal temperature measurement -8.5 8.5 °C Indicator LED I IND LED current 1 8 mA IACC Accuracy of current -30 30 % VLED Voltage range of connected LED Vds of current sink 0.3 VDD V LED_DRV ILED1 LED current 12.5 100 mA IACC Accuracy of current -10 10 % VLED Voltage range of connected LED Vds of current sink 0.3 VDD V

Electrical Characteristics

[v1-00] 2016-Dec-30 Document Feedback AS7261 − Electrical Characteristics Note(s): 1. Guaranteed, not tested in production. Digital Inputs and Outputs IIL RESN Logic input current (RESN pin) Vin=0V -1 -0.2 mA VIH CMOS logic high input 0.7* VDD VDD V VIL CMOS logic low input 00 . 3 * V D D V VOH CMOS logic high output I=1mA VDD-0.4 V VOL CMOS logic low output I=1mA 0.4 V tRISE (1) Current rise time C(Pad)=30pF 5 ns tFALL (1) Current fall time C(Pad)=30pF 5 ns Symbol Parameter Conditions Min Typ Max Unit

Document Feedback [v1-00] 2016-Dec-30 AS7261 − Electrical Characteristics Figure 11: SPI Master Read Timing Diagram tDI_V CSN_xx MOSI MISO SCK LSB tSCK_H tSCK_L Dont care MSB

Document Feedback [v1-00] 2016-Dec-30 AS7261 − Detailed Descriptions Figure 15: Internal Block Diagram XYZ Chromatic White Color Sensor The XYZ Chromatic White Color sensor is a next-generation digital color sensor device. Each channel is a designed to meet the X, Y, Z standard observer filter characteristics compliant with the CIE 1931 standard or an NIR spectrum. The sensor contains analog-to-digital converters (16-bit resolution ADC), which integrate the current from each channel’s photodiode. Upon completion of the conversion cycle, the integrated result is transferred to the corresponding data registers. The transfers are double-buffered to ensure that the integrity of the data is maintained. Standard observer interference filters realize the XYZ response, which enables minimal life-time drift and very high temperature stability. Filter accuracy will be affected by the angle of incidence wh ich itself is limited by an integrated aperture and an internal micro-lens structure. The aperture-limited field of view is ±20.5° to deliver specified accuracy. Detailed Descriptions AS7261 RC Osc VDD1 VDD2 GND 16MHz MISO SCK MOSI CSN_SD RESN Cognitive Light Engine (CLE) SPI Master TX / SDA_S RX / SCL_S UART / I2C LED_DRV XYZ Multi Spectral Se nsor D LED_IND C NIR I2C_ENB INT

[v1-00] 2016-Dec-30 Document Feedback AS7261 − Detailed Descriptions Data Conversion Description AS7261 Spectral Conversion is implemented via two photodiode banks. The First Bank, Bank1 consists of data from the X, Y, Z and NIR (near-IR) photodiodes. Bank2 provides data from the same X and Y photodiodes as well as the D (dark) and C (Clear) photodiodes. Spectral conversion requires the integration time (IT in ms) set to complete. If both photodiode banks are required to complete the conversion, the 2nd bank requires an additional IT ms. Minimum IT for a single bank conversion is 2.8 ms. If data is required from all 6 photodiodes then the device must perform 2 full conversions (2 x Integration Time). The spectral conversion process is controlled with four BANK Mode settings as follows: BANK Mode 0: Conversions will occur continuously and data will be available in I²C re gister s X, Y, Z, a nd N IR or via th e ATDATA co mmand w he n using the UART device interface. BANK Mode 1: Conversions will occur continuously and data will be available in I²C registers X, Y, D, and C or via the ATDATA command. BANK Mode 2: Conversions occur continuously and data will be available in registers X, Y, Z, NIR, D and C or via the ATDATA command after two integration periods. In this Mode 2 the calibrated, corrected values may also be obtained from the appropriate I²C registers or using the ATXYZC command. When the bank setting is Mode 0, Mode 1, or Mode 2, the spectral data conversion process operates continuously, with new data available after each IT ms period. In the continuous modes, care should be taken to assure prompt interrupt servicing so that integration values from both banks are all derived from the same spectral conversion cycle. BANK Mode 3: Data will be available in registers X, Y, Z, NIR, D and C in One-Shot mode. And in this Mode 3 the calibrated, corrected values may also be obtained from the appropriate I²C registers or using the ATXYZC command. When the bank setting is set to Mode 3 the device initiates One-Shot operation. The DATA_RDY bit is set to 1 once data is available, indicating spectral conversion is complete. One-Shot mode is intended for use when it is critical to ensure spectral conversion results are obtained contemporaneously.

[v1-00] 2016-Dec-30 Document Feedback AS7261 − Detailed Descriptions Temperature Sensor The internal temperature sensor is constantly measuring the on-chip temperature and enables temperature compensation procedures. It can be read via I²C or AT Command. Reset Pulling down the RESN pin for longer than 100ms resets the AS7261. Figure 18: Reset Circuit Indicator LED for Flash Memory Programming Progress The LED, connected to pin LED_IND, can be used to indicate Flash memory programming pr ogress of the device. While programming the AS7261 via the ex ternal SD card the indicator LED automatically starts flashing. When programming is completed the indicator LED is automatically switched off. The Flash Memory Programming is initiated by the user as needed, but once started the LED flashing is not under user control. Electronic Shutter with LED_IND or LED_DRV Driver Control Under user control there are two LED driver outputs that can be used to control LEDs on each driver pin. This allows different wavelength light sources to be used in the same system. The LED output sink currents are programmable and can drive external LED sources: LED_IND for 1mA, 2mA, 4mA or 8mA and LED_DRV for 12.5mA, 25mA, 50mA or 100mA. After programming for current the sources can be turned off and on via I²C registers or AT commands to provide the AS7261 with an electronic shutter capability. Reset AS7261 Cognitive Lighting Engine RESN Push > 100ms

Document Feedback [v1-00] 2016-Dec-30 AS7261 − Detailed Descriptions Interrupt Operation If BANK is set to Mode 0 or Mode 1 then the data is ready after the 1st integration time. If BANK is set to Mode 2 or Mode 3 then the data is ready after two integration times. If the interrupt is enabled (INT = 1) then when the data is ready, the INT line is pulled low and DATA_RDY is set to 1. The INT line is released (returns high) when the control register is read. DATA_RDY is cleared to 0 when any of the sensor registers X, Y, Z, NIR, D and C are read. For multi-byte sensor data (2 or 4 bytes), after the 1st byte is read the remaining bytes are shadow protected in case an integrati on cycle completes just after the 1st byte is read. In continuous spectral conversion mode (BANK setting of Mode 0, 1, or 2), the sensors continue to gather information at the rate of the integration time, hence if the sensor registers are not read when the interrupt line goes low, it will stay low and the next cycle’s sensor data will be available in the registers at the end of the next integration cycle. When the control register BANK bits are written with a value of Mode 3, One-Shot Spectral Conversion mode is entered. When a single set of contemporaneous sensor readings is desired, writing BANK Mode 3 to the control register immediately triggers exactly two spectral data conversion cycles. At the end of these two conversion cycles, the DATA_RDY bit is set as for the other BANK modes. To perform a new One-Shot sequence, the control register BANK bits should be written with a value of Mode 3 again. This process may continue until the user writes a different value into the BANK bits. I²C Slave Interface If selected by the I2C_ENB pin setting, interface and control can be accomplished through an I²C compatible slave interface to a set of registers that provide access to device control functions and output data. These registers on the AS7261 are, in reality, implemented as virtual registers in software. The actual I²C slave hardware registers number only three and are described in the table below. The steps necessary to access the virtual registers defined in the followin g are explained in pseudocode for external I²C master writes and reads below.

[v1-00] 2016-Dec-30 Document Feedback AS7261 − Detailed Descriptions I²C Feature List

• Fast mode (400kHz) and stan dard mode (100kHz) support
• 7+1-bit addressing mode
• Write format: Byte
• Read format: Byte Figure 19: I²C Slave Device Address and Physical Registers I²C Virtual Register Write Access I²C Virtual Resister Byte Write, detailed below, shows the pseudocode necessary to write virtual registers on the AS7261. Note that, because the actual registers of interest are realized as virtual registers, a means of indicating whether there is a pending read or write operation of a given virtual register is needed. To convey this informatio n, the most significant bit of the virtual register address is used as a marker. If it is 1, then a write is pending, otherwise the slave is expecting a virtual read operation. The pseudocode illustrates the proper technique for polling of the I²C slave status register to ensure the slave is ready for each transaction. Entity Description Note Device Slave Address 8-bit Slave Address Byte = 1001001x (device address = 49 hex) x= 1 for Master Read (byte = 93 hex) x= 0 for Master Write (byte = 92 hex) STATUS Register I²C slave interface STATUS register Read-only Register Address = 0x00 Bit 1: TX_VALID 0  New data may be written to WRITE register 1  WRITE register occupied. Do NOT write. Bit 0: RX_VALID 0  No data is ready to be read in READ register. 1  Data byte available in READ register. WRITE Register I²C slave interface WRITE register Write-only Register Address = 0x01 8-Bits of data written by the I²C Master intended for receipt by the I²C slave. Used for both virtual register addresses and write data. READ Register I²C slave interface READ register Read-only Register Address = 0x02 8-Bits of data to be read by the I²C Master.

Document Feedback [v1-00] 2016-Dec-30 AS7261 − Detailed Descriptions I²C Virtual Register Byte Write Pseudocode Poll I²C slave STATUS register; If TX_VALID bit is 0, a write ca n be performed on the interface; Send a virtual register address and set the MSB of the register address to 1 to indicate the pending write; Poll I²C slave STATUS register; If TX_VALID bit is 0, the virtual register address for th e write has been received and the data may now be written; Write the data. Sample Code: #define I2C_AS72XX_SLAVE_STATUS_REG 0x00 #define I2C_AS72XX_SLAVE_WRITE_REG 0x01 #define I2C_AS72XX_SLAVE_READ_REG 0x02 #define I2C_AS72XX_SLAVE_TX_VALID 0x02 #define I2C_AS72XX_SLAVE_RX_VALID 0x01 void i2cm_AS72xx_write(uint8_t virtualReg, uint8_t d) volatile uint8_t status; while (1) // Read slave I²C status to see if the write buffer is ready. status = i2cm_read(I2C_AS72XX_SLAVE_STATUS_REG); if ((status & I2C_AS72XX_SLAVE_TX_VALID) == 0) // No inbound TX pending at slave. Okay to write now. break, // Send the virtual register address (setti ng bit 7 to indicate a pending write). i2cm_write(I2C_AS72XX_SLAVE_WRITE_REG, (virtualReg | 0x80)) ; while (1) // Read the slave I²C status to see if the write buffer is ready. status = i2cm_read(I2C_AS72XX_SLAVE_STATUS_REG) ; if ((status & I2C_AS72XX_SLAVE_TX_VALID) == 0) // No inbound TX pending at slave. Okay to write data now. break; //Send the data to co mplete the operation. i2cm_write(I2C_AS72XX_SLAVE_WRITE_REG, d) ; I²C Virtual Register Read Access I²C Virtual Register Byte Read, detailed below, shows the pseudocode necessary to read vi rtual registers on the AS7261. Note that in this case, reading a virtual register, the register address is not modified.

[v1-00] 2016-Dec-30 Document Feedback AS7261 − Detailed Descriptions I²C Virtual Register Byte Read Pseudocode Poll I²C slave STATUS register; If TX_VALID bit is 0, the virtual regist er address for the read may be written; Send a virtual register address; Poll I²C slave STATUS register; If RX_VALID bit is 1, the read data is ready; Read the data. Sample Code: uint8_t i2cm_AS72xx_rea d(uint8_t virtualReg) volatile uint8_t status, d ; while (1) // Read slave I²C status to see if the read buffer is ready. status = i2cm_read(I2C_AS72XX_SLAVE_STATUS_REG); if ((status & I2C_AS72XX_SLAVE_TX_VALID) == 0) // No inbound TX pending at slave. Okay to write now. break; // Send the virtual register address (setti ng bit 7 to indicate a pending write). i2cm_write(I2C_AS72XX_SLAVE_WRITE_REG, virtualReg); while (1) // Read the slave I²C status to see if our read data is available. status = i2cm_read(I2C_AS72XX_SLAVE_STATUS_REG) ; if ((status & I2C_AS72XX_SLAVE_RX_VALID) != 0) // Read data is ready. break ; // Read the data to co mplete the operation. d = i2cm_read(I2C_AS72XX_SLAVE_READ_REG) ; return d ;s The details of the i2cm_read() and i2cm_write() functions in previous Figures are dependent upon the nature and implementation of the external I²C master device.

Document Feedback [v1-00] 2016-Dec-30 AS7261 − Detailed Descriptions 4-Btye Floating-Point (FP) Registers Several 4 byte registers (hex) are used by the AS7261. Here is an example of how these registers are used to represent floating point data (based on the IEEE 754 standard): Figure 20: Example of the IEEE 754 Standard The floating point (FP) value assumed by 32 bit binary32 data with a biased exponent e (the 8 bit unsigned integer) and a 23 bit fraction is (for the above example): (EQ1) FPvalue 1–() sign 1 b23 i– 2 i– i 1= 2 e 127–()×= (EQ2) FPvalue 1–() 0 1 b23 i– 2 i– i 1= 2 124 127–()×=

[v1-00] 2016-Dec-30 Document Feedback AS7261 − Detailed Descriptions I²C Virtual Register Set The figure below provides a summ ary of the AS7261 I²C register set. Figures after that provide a dditional register details. All register data is hex, and all multi-byte entities are Big Endian (most significant byte is situated at the lowest register address). Multiple byte registers (2 byte integer, or, 4 byte floating point) must be read in the order of as cending register addresses (low to high). And if capable of being written to, must also be written in the order ascending register addresses. Figure 21: I²C Virtual Register Set Overview Version Registers 0x00:0x01 HW_Version Hardware Version 0x02:0x03 FW_Version Firmware Version Control Registers 0x04 Control_Setup RST INT GAIN Bank DATA_ RDY RSVD 0x05 INT_T Integration Time 0x06 Device_Temp Device Temperature 0x07 LED_Control RSVD ICL_DRV LED_ DRV ICL_IND LED_IND Sensor Raw Data Registers 0x08 X_High Channel X High Data Byte 0x09 X_Low Channel X Low Data Byte 0x0A Y_High Channel Y High Data Byte 0x0B Y_Low Channel Y Low Data Byte 0x0C Z_High Channel Z High Data Byte 0x0D Z_Low Channel Z Low Data Byte 0x0E NIR_High Channel NIR High Data Byte 0x0F NIR_Low Channel NIR Low Data Byte 0x10 Dark_High Channel Dark High Data Byte 0x11 Dark_Low Channel Dark Low Data Byte 0x12 Clear_High Channel Clear High Data Byte 0x13 Clear_Low Channel Clear Low Data Byte

Document Feedback [v1-00] 2016-Dec-30 AS7261 − Detailed Descriptions Detailed Register Description Figure 22: HW Version Registers Sensor Calibrated Data Registers 0x14:0x17 Cal_X Cal-X data (4-byte floating-point) 0x18:0x1B Cal_Y Cal-Y data (4-byte floating-point) 0x1C:0x1F Cal_Z Cal-Z data (4-byte floating-point) 0x20:0x23 Cal_x_1931 Cal-x (CIE 1931) (4-byte floating-point) 0x24:0x27 Cal_y_1931 Cal-y (CIE 1931) (4-byte floating-point) 0x28:0x2B Cal_upri Cal_u’ (CIE 1976) (4-byte floating-point) 0x2C:0x2F Cal_vpri Cal_v’ (CIE 1976) (4-byte floating-point) 0x30:0x33 Cal_u Cal_u (CIE 1976) (4-byte floating-point) 0x34:0x37 Cal_v Cal_y (CIE 1976) (4-byte floating-point) 0x38:0x3B Cal_DUV Cal_DUV (CIE 1976) (4-byte floating-point) 0x3C:0x3F Cal_LUX Calibrated LUX (4-byte) 0x40:0x4F Cal_CCT Calibrated CCT (4-byte) Addr: 0x00 HW_Version Bit Bit Name Default Access Bit Description 7:0 Device Type 01000000 R Device type number Addr: 0x01 HW_Version Bit Bit Name Default Access Bit Description 7:0 HW Version 00111101 R Hardware version

[v1-00] 2016-Dec-30 Document Feedback AS7261 − Detailed Descriptions Figure 23: FW Version Registers Figure 24: Control Setup Register Addr: 0x02 FW_Version Bit Bit Name Default Access Bit Description 7:6 Minor version R Minor version [1:0] 5:0 Sub version R Sub version Addr: 0x03 FW_Version Bit Bit Name Default Access Bit Description 7:4 Major version R Major version 3:0 Minor version R Minor version [5:2] Addr: 0x04/0x84 Control_Setup Bit Bit Name Default Access Bit Description 7R S T0 R / W Soft Reset, Set to 1 for soft reset, goes to 0 automatically after the reset 6I N T0 R / W Enable interrupt pin output (INT), 1: Enable, 0: Disable 5:4 GAIN 10 R/W Sensor Channel Gain Setting (all channels) 3:2 BANK 10 R/W Data Conversion Type (continuous) ‘b00=Mode 0: X, Y, Z and NIR ‘b01=Mode 1: X, Y, D and C ‘b10=Mode 2: X, Y, Z, NIR, D and C ‘b11=Mode 3: One-Shot operation 1D A T A _ R D Y0 R / W 1: Data Ready to Read, sets INT active if interrupt is enabled. Can be polled if not using INT.

0 RSVD 0 R Reserved; Unused

[v1-00] 2016-Dec-30 Document Feedback AS7261 − Detailed Descriptions Figure 28: Sensor Raw Data Registers Addr: 0x08 X_High Bit Bit Name Default Access Bit Description 7:0 X_High R Channel X High Data Byte Addr: 0x09 X_Low Bit Bit Name Default Access Bit Description 7:0 X_Low R Channel X Low Data Byte Addr: 0x0A Y_High Bit Bit Name Default Access Bit Description 7:0 Y_High R Channel Y High Data Byte Addr: 0x0B Y_Low Bit Bit Name Default Access Bit Description 7:0 Y_Low R Channel Y Low Data Byte Addr: 0x0C Z_High Bit Bit Name Default Access Bit Description 7:0 Z_High R Channel Z High Data Byte Addr: 0x0D Z_Low Bit Bit Name Default Access Bit Description 7:0 Z_Low R Channel Z Low Data Byte Addr: 0x0E NIR_High Bit Bit Name Default Access Bit Description 7:0 NIR_High R Channel NIR High Data Byte Addr: 0x0F NIR_Low Bit Bit Name Default Access Bit Description 7:0 NIR_Low R Channel NIR Low Data Byte Addr: 0x10 Dark_High Bit Bit Name Default Access Bit Description 7:0 Dark_High R Channel Dark High Data Byte

Document Feedback [v1-00] 2016-Dec-30 AS7261 − Detailed Descriptions Addr: 0x11 Dark_Low Bit Bit Name Default Access Bit Description 7:0 Dark_Low R Channel Dark Low Data Byte Addr: 0x12 Clear_High Bit Bit Name Default Access Bit Description 7:0 Clear_High R Channel Clear High Data Byte Addr: 0x13 Clear_Low Bit Bit Name Default Access Bit Description 7:0 Clear_Low R Channel Clear Low Data Byte

[v1-00] 2016-Dec-30 Document Feedback AS7261 − Detailed Descriptions Figure 29: Sensor Calibrated Data Registers Addr: 0x14:0x17 Cal_X Bit Bit Name Default Access Bit Description 31:0 X_Cal R Calibrated X data (4-byte floating-point) Addr: 0x18:0x1B Cal_Y Bit Bit Name Default Access Bit Description 31:0 Y_Cal R Calibrated Y data (4-byte floating-point) Addr: 0x1C:0x1F Cal_Z Bit Bit Name Default Access Bit Description 31:0 Z_Cal R Calibrated Z data (4-byte floating-point) Addr: 0x20:0x23 Cal_x_1931 Bit Bit Name Default Access Bit Description 31:0 Cal_x_1931 R Calibrated x (CIE 1931) (4-byte floating-point) Addr: 0x24:0x27 Cal_y_1931 Bit Bit Name Default Access Bit Description 31:0 Cal_y_1931 R Calibrated y (CIE 1931) (4-byte floating-point) Addr: 0x28:0x2B Cal_upri Bit Bit Name Default Access Bit Description 31:0 Cal_upri R Calibrated u’ (CIE 1976) (4-byte floating-point) Addr: 0x14:0x17 Cal_vpri Bit Bit Name Default Access Bit Description 31:0 Cal_vpri R Calibrated v’ (CIE 1976) (4-byte floating-point) Addr: 0x18:0x1B Cal_u Bit Bit Name Default Access Bit Description 31:0 Cal_u R Calibrated u (CIE 1976) (4-byte floating-point) Addr: 0x1C:0x1F Cal_v Bit Bit Name Default Access Bit Description 31:0 Cal_v R Calibrated v (CIE 1976) (4-byte floating-point)

Document Feedback [v1-00] 2016-Dec-30 AS7261 − Detailed Descriptions UART Interface If selected by the I2C_ENB pin setting, the UART module implements the TX and RX signal s as defined in the RS-232 / V.24 standard communication protocol. It has on both, receive and transmit path, a 16 entry deep FIFO. It can generate interrupts as required. UART Feature List 1

• Full Duplex Operation (Indep endent Serial Receive and Transmit Registers) with FIFO buffer of 8 byte for each.
• At a clock rate of 16MHz it supports communication at 115200 Baud.
• Supports Serial Frames with 8 Data Bits, no Parity and 1 Stop Bit Theory of Operation TRANSMISSION If data is available in the transmit FIFO, it will be moved into the output shift register and the data will be transmitted at the configured Baud Rate, starting with a Start Bit (logic zero) and followed by a Stop Bit (logic one). RECEPTION At any time, with the receiver be ing idle, if a falling edge of a start bit is detected on the input, a byte will be received and stored in the receive FIFO. The following Stop Bit will be checked to be logic one. Addr: 0x20:0x23 Cal_DUV Bit Bit Name Default Access Bit Description 31:0 Cal_DUV R Calibrated DUV (CIE 1976) (4-byte floating-point) Addr: 0x24:0x27 Cal_LUX Bit Bit Name Default Access Bit Description 31:0 Cal_LUX R Calibrated LUX (4-byte) Addr: 0x28:0x2B Cal_CCT Bit Bit Name Default Access Bit Description 31:0 Cal_CCT R Calibrated CCT (4-byte) 1. With UART operation, min VDD of 2.97V is required as shown in Electrical Characteristics figures.

Document Feedback [v1-00] 2016-Dec-30 AS7261 − Detailed Descriptions In the figure below, numeric values may be specified with no leading prefix, in which case they will be interpreted as decimals, or with a leading “0x” to indicate that they are hexadecimal numbers, or with a leading “‘b” to indicate that they are binary numbers. The commands are loosely grouped into functional areas. Texts appearing between angle brackets (‘<‘ and ‘>‘) are commands or response arguments. A carriage return character, a linefeed character, or both may terminate commands and responses. Note that any command that encounters an error will generate the “ERROR” response shown, for example, in the NOP command at the top of the first table, but has been omitted elsewhere in the interest of readability and clarity. Figure 32: AT Commands Command Response Description/Parameters XYZ Calibrated Data with Its Derivatives ATXYZC <X_cor_value>, <Y_cor_value>, <Z_cor_value> OK Read calibrated X, Y, and Z data. Returns comma-separated floating-point values ATLUXC < LUX_value> OK Read the calibrated LUX value from the sensor. ATCC TC < CCT_value> OK Read the calibrated CCT value from the sensor. ATSMALLXYC <smallX_value>, <smallY_value> OK Read calibrated x and y for CIE 1931 color gamut. Returns comma separated floating-point values (5 decimal places). ATUVPRIMEC <Uprime_value>, <Vprime_value>, <U_value>, <V_value> OK Read calibrated u’ , v’ and u, v for CIE 1976 color gamut. Returns comma separated floating-point values (5 decimal places). ATDUVC <DUV_ value> OK Read calibrated Duv for CIE 1976-color gamut. Returns comma separated floating-point values (5 decimal places). Spectral Data per Channel <Z_value> OK Read raw X, Y, and Z data. Returns comma-separated 16-bit integers. ATDATA <Z_value>, <Spec_reg_NIR>, <Spec_reg_D>, <Spec_reg_C> OK Read raw X, Y, Z and NIR data as well as two special internal registers D, & C. Returns comma-separated 16-bit integers.

[v1-00] 2016-Dec-30 Document Feedback AS7261 − Detailed Descriptions Sensor Configuration ATINTTIME=<value>O K Set sensor integration time. Values should be in the range [1... 255], with integration time = <value> * 2.8msecs. ATINT TIME < value> OK Read sensor integration time, with integration time = <value> * 2.8msecs. ATGAIN=<value> OK Set sensor gain: 0=1X, 1=3.7X, 2=16X, 3=64X ATGAIN < value>OK Read sensor gain setting, returning 0, 1, 2, or 3 as defined immediately above. AT TEMP < value>OK Read temperature of chip in Celsius AT TCSMD=<value> OK Set Chromatic White Color Sensor Mode 0  Captures X, Y, Z, and IR (1 integration period) 1  Captures X, Y, Dk, and CLR (1 integration period) 2  Captures X, Y, Z, Dk, IR and CLR (2 integration period) 3  Sensors are OFF AT TCSMD < value> OK Read Color Sensor Mode, see above ATINTRVL=<value> OK Set the sampling interval as an integer multiple of the Integration time. The <value> is an integer between [1..255]. A sampling interval=1 implies a sampling rate of 1x the current integration time. A sampling interval=255 implies a slow sampling rate of 255 times the current integration time. ATINTRVL <value>OK Read the sampling interval as an integer multiple of the Integration time. Returns an integer in the range [1..255] as defined above ATBURST=<value>. OK <value>= # of samples (ATBURST=1 means run until ATBURST=0 is received (a special case for continuous output) LED Driver Controls ATLED0=<value> OK Sets LED_IND: 100=ON, 0=OFF ATLED0 <100|0>OK Reads LED_IND setting: 100=ON, 0=OFF ATLED1=<value> OK Sets LED_DRV: 100=ON, 0=OFF ATLED1 <100|0>OK Reads LED_DRV setting: 100=ON, 0=OFF ATLEDC=<value> OK Sets LED_IND and LED_DRV current LED_IND: bits 3:0; LED_DRV: 7:4 bits LED_IND: ‘b00=1mA; ‘b01=2mA; ‘b10=4mA; ‘b11=8mA LED_DRV: ‘b00=12.5mA; ‘b01=25mA; ‘b10=50mA; ‘b11=100mA ATLEDC <value>OK Reads LED_IND and LED_DRV current settings as shown above

Document Feedback [v1-00] 2016-Dec-30 AS7261 − Detailed Descriptions NOP , Version Access, System Reset AT OK  Success ERROR  Failure NOP ATSRST OK  Success ERROR  Failure Software Reset AT VERSW <SWversion#>OK ERROR  Failure Returns the system software version number AT VERHW <HWversion#>OK ERROR  Failure Returns the system hardware revision and product ID, with bits 7:4 containing the part ID, and bits 3:0 yielding the chip revision value. Firmware Update ATFWU=<value>O K <value>= 16-bit checksum. Initializes the firmware update process. Number of bytes that follow are always 56 KBytes ATFW=<value>O K Download new firmware Up to 7 bytes represented as hex chars with no leading or trailing 0x. Repeat command till all 56Kbytes of firmware are downloaded ATFWA OK Causes target address for FW updates to advance. Should be called after every successful “OK” returned after “ATFW=<value>” command usage. ATFWS OK Causes the active image to switch between the two possible current images and then resets the IC

[v1-00] 2016-Dec-30 Document Feedback AS7261 − Application Information Figure 33: AS7261 Typical Application Circuit

Application Information

LED_DRV LED_IND RX/SCL_S TX/SDA_S INT CSN_SD CSN_EE MISO MOSI SCK I2C_ENB NC NC NC NC NC Fla sh Memory 1/ C S DO DI CL K VCCGND/HOLD /WP 3V3 3V3 3V3 Vl ed RST RX TX INT 100nF 10uF 10K 1uF DNP

Document Feedback [v1-00] 2016-Dec-30 AS7261 − Application Information PCB Layout Figure 34: Typical Layout Reading In order to prevent interference, avoid trace routing feedthroughs with exposure directly under the AS7261. An example routing is illustrated in the diagram.

[v1-00] 2016-Dec-30 Document Feedback AS7261 − Package Drawings & Markings Figure 35: Note(s): 1. XXXXX = tracecode Package Drawings & Markings AS7261 Green RoHS

Document Feedback [v1-00] 2016-Dec-30 AS7261 − PCB Pad Layout Suggested PCB pad layout guidelines for the LGA device are shown. Figure 36: Recommended PCB Pad Layout Note(s): 1. Unless otherwise specified, all dimensions are in millimeters. 2. Dimensional tolerances are ±0.05mm unless otherwise noted. 3. This drawing is subject to change without notice. PCB Pad Layout 4.40 0.30 0.65 1.10 4.60 Unit: mm

[v1-00] 2016-Dec-30 Document Feedback AS7261 − Mechanical Data Figure 37: Tape & Reel Information Note(s): 1. All dimensions in millimeter s unless of otherwise stated. 2. Measured from centreline of spro cket hole to centreline of pocket. 3. Cumulative tolerance of 10 sprocket holes is ±0.20. 4. Measured from centreline of spro cket hole to centreline of pocket. 5. Other material available. Mechanical Data

[v1-00] 2016-Dec-30 Document Feedback AS7261 − Soldering & Storage Information Manufacturing Process Considerations The AS7261 package is compatible with standard reflow no-clean and cleaning processes including aqueous, solvent or ultrasonic techniques. However, as an open-aperture device, precautions must be taken to avoid particulate or solvent con-tamination as a result of any manufacturing processes, including pick and place, reflow , cleaning, integration assembly and/or testing. Temporary covering of the ap-erture is allowed. To avoid degradation of accuracy or performance in the end prod-uct, care should be taken that any temporary covering and associated seal-ants/debris are thoroughly removed prior to any optical testing or final packaging. Storage Information Moisture Sensitivity Optical characteristics of the device can be adversely affected during the soldering process by the release and vaporization of moisture that has been previous ly absorbed into the package. To ensure the package contains the smallest amount of absorbed moisture possible, each device is baked prior to being dry packed for shipping. Devices are dry packed in a sealed aluminized envelope called a moisture-barrier bag with silica gel to protect them from am- bient moisture during shipping, handling, and storage before use. Shelf Life The calculated shelf life of the device in an unopened moisture barrier bag is 12 months from the date code on the bag when stored under the following conditions:

• Shelf Life: 12 months
• Ambient Temperature: < 40°C
• Relative Humidity: < 90% Rebaking of the devices will be required if the devices exceed the 12 month shelf life or the Humidity Indicator Card shows that the devices were exposed to conditions beyond the allow- able moisture region.

Document Feedback [v1-00] 2016-Dec-30 AS7261 − Soldering & Storage Information Floor Life The CS package has been assigned a moisture sensitivity level of MSL 2. As a result, the floor life of devices removed from the moisture barrier bag is 1 year from the time the bag was opened, provided that the devices are stored under the following conditions:

• Floor Life: 1 year
• Ambient Temperature: <30°C
• Relative Humidity:<60% If the floor life or the temperature/humidity conditions have been exceeded, the devices must be rebaked prior to solder reflow or dry packing. Rebaking Instructions When the shelf life or floor life limits have been exceeded, rebake at 50°C for 12 hours.

[v1-00] 2016-Dec-30 Document Feedback AS7261 − Ordering & Contact Information Figure 40:

Ordering Information

Note(s): 1. Required companion serial flash memory (must be ams verified) is ordered from the flash memory supplier (e.g. AT25SF041-SSHD-B from Adesto Technologies) 2. AS7261 flash memory software is available from ams Buy our products or get free samples online at: www.ams.com/ICdirect Technical Support is available at: www.ams.com/Technical-Support Provide feedback about this document at: www.ams.com/Document-Feedback For further information and requests, e-mail us at: ams_sales@ams.com For sales offices, distributors and representatives, please visit: www.ams.com/contact Headquarters ams AG Tobelbader Strasse 30

8141 Premstaetten

Austria, Europe Tel: +43 (0) 3136 500 0 Website: www.ams.com Ordering Code Package Marking Description Delivery Form Delivery Quantity AS7261-BLGT 20-pin LGA AS7261 XYZ Chromatic White Color Sensor + NIR with Electronic Shutter and Smart Interface Tape & Reel 2000 pcs/reel Ordering & Contact Information

Document Feedback [v1-00] 2016-Dec-30 AS7261 − RoHS Compliant & ams Green Statement RoHS: The term RoHS compliant means that ams AG products fully comply with current RoHS directives. Our semiconductor products do not contain any chemicals for all 6 substance categories, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, RoHS compliant products are suitable for use in specif ied lead-free processes. ams Green (RoHS compliant and no Sb/Br): ams Green defines that in addition to RoHS compliance, our products are free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material). Important Information: The information provided in this statement represents ams AG knowledge and belief as of the date that it is provided. ams AG bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are unde rway to better integrate information from third parties. ams AG has taken and continues to take reasonable steps to prov ide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ams AG and ams AG suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. RoHS Compliant & ams Green Statement

[v1-00] 2016-Dec-30 Document Feedback AS7261 − Copyrights & Disclaimer Copyright ams AG, Tobelbader St rasse 30, 8141 Premstaetten, Austria-Europe. Trademarks Registered. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used with out the prior written consent of the copyright owner. Devices sold by ams AG are covered by the warranty and patent indemnification provisions appe aring in its General Terms of Trade. ams AG makes no warranty, express, statutory, implied, or by description regarding th e information set forth herein. ams AG reserves the right to ch ange specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with ams AG for current information. This product is intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications , such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by ams AG for each application. This product is provided by ams AG “AS IS” and any express or implied wa rranties, including, but not limited to the implied warranties of merchantability and fitness for a particular purpose are disclaimed. ams AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any th ird party shall arise or flow out of ams AG rendering of technical or other services. Copyrights & Disclaimer

Document Feedback [v1-00] 2016-Dec-30 AS7261 − Document Status Document Status Product Status Definition Product Preview Pre-Development Information in this datasheet is based on product ideas in the planning phase of development. All specifications are design goals without any warranty and are subject to change without notice Preliminary Datasheet Pre-Production Information in this datasheet is based on products in the design, validation or qualification phase of development. The performance and parameters shown in this document are preliminary without any warranty and are subject to change without notice Datasheet Production Information in this datasheet is based on products in ramp-up to full production or full production which conform to specifications in accordance with the terms of ams AG standard warranty as given in the General Terms of Trade Datasheet (discontinued) Discontinued Information in this datasheet is based on products which conform to specifications in accordance with the terms of ams AG standard warranty as given in the General Terms of Trade, but these products have been superseded and should not be used for new designs Document Status

[v1-00] 2016-Dec-30 Document Feedback AS7261 − Revision Information Initial production version 1-00 for releaseRevision Information

Document Feedback [v1-00] 2016-Dec-30 AS7261 − Content Guide

1 General Description

1 Key Benefits & Features

2 Applications

2 Block Diagram

3 Pin Assignments

3 Pin Description

5A b s o l u t e M a x i m u m R a t i n g s

6 Electrical Characteristics

7 Timing Characteristics

10 Typical Optical Characteristics

11 Detailed Descriptions

11 XYZ Chromatic White Color Sensor

12 Data Conversion Description

13 RC Oscillator

14 Temperature Sensor

14 Reset

14 Indicator LED for Flash Me mory Programming Progress

14 Electronic Shutter with LED_IND or LED_DRV Driver

15 Interrupt Operation

15 I²C Slave Interface

16 I²C Feature List

16 I²C Virtual Register Write Access

17 I²C Virtual Register Byte Write

17 I²C Virtual Register Read Access

18 I²C Virtual Register Byte Read

19 4-Btye Floating-Point (FP) Registers

20 I²C Virtual Register Set

22 Detailed Register Description

27 UART Interface

27 UART Feature List

27 Theory of Operation

28 AT Command Interface

34 PCB Pad Layout

35 Mechanical Data

36 Soldering & Storage Information

36 Soldering Information

37 Manufacturing Process Considerations

37 Storage Information

37 Moisture Sensitivity

37 Shelf Life

37 Floor Life

38 Rebaking Instructions

[v1-00] 2016-Dec-30 Document Feedback AS7261 − Content Guide

40 RoHS Compliant & ams Green Statement

41 Copyrights & Disclaimer

42 Document Status