AS7038RB-COLM

AS7038RB AMSOSRAM | Alldatasheet

Document overview

• Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
• PDF pages: 127

Technical content

Biosensor Solution with Embedded ECG Channel v2-00 • 2021-Jun-02

Document Feedback AS7038RB Content Guide Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 2 Content Guide 9 Package Drawings & Markings . 122

11 Soldering & Storage

Document Feedback AS7038RB General Description Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 3

1 General Description

The operation of the AS7038RB is based on photoplethysmography (PPG) and electrocardiogram (ECG). PPG is the most used HRM method, which measures the pulse rate by sampling light modulated by the blood vessels, which expand and contract as blood pulses through them. PPG is also used to measure the blood oxygen saturation (SpO2). ECG is the reference for any measurement of the bio potential generated by the heart. Embedded ECG analog front end satisfies IEC 60601-2-47 requirements. The solution includes LED drivers, photo-sensor, analog front-end (AFE) and sequencer as well as application software. In addition, the device also enables skin temperature and skin resistivity measurements by providing interfaces to external sensors. Compare to ams previous generation AS7038RB has 250% larger photodiode with lower LEDs driving current to achieve the high PPG performances. The AS7038RB’s low-power design and small form factor is particularly well suited to application in earbuds, fitness bands, smart watches, sports watches and smart patches, in which board space is limited and in which users look for extended, multi-day intervals between battery recharges. Thin package dimension makes the AS7038RB suitable for height constrained solution likes earbuds or smart patches. Photodiode filter centered on red and infra-red wavelengths and embedded ADC make the AS7038RB suitable for disposable Pulse Oximeter solution.

1.1 Key Benefits & Features

The benefits and features of AS7038RB, Biosensor Solution with Embedded ECG Channel, are listed below: Figure 1: Added Value of Using AS7038RB Benefits Features Address all skin types Improved optical path Higher optical SNR 250% larger embedded photodiode Allows smallest application size e.g. narrow HRM measurement band Compact device integrated PD and analog front end Electrocardiogram ECG with dry electrodes Embedded low noise analog front end for ECG signals acquisition fulfill IEC 60601-2-47 Enabling SpO2 measurements RED and IR dedicated embedded PD filter

Document Feedback AS7038RB General Description Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 4 Benefits Features Additional information for end user Analog electrical front end (e.g. for temperature sensing using a NTC or galvanic skin resistivity (GSR)) Integrated interference filter Reduce negative effect of strong sunlight Long operating time Hardware sequencer to offload processor Adjustable LED driver with current control Works reliably with ambient light Synchronous demodulator

1.2 Applications

• Optical sensor platform
• Disposable oximeter
• Smart patch
• Earbuds
• Fitness band
• Smart watch
• Oximeter
• ECG monitoring

Document Feedback AS7038RB General Description Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 5

1.3 Block Diagram

The functional blocks of this device are shown below: Figure 2 : Functional Blocks of AS7038RB AS7038RB SCL SDA ECG_REF ECG_INN ECG_INP ENABLE GPIO3 GPIO2 GPIO1 LDO Reference Block AGND SIGREF VDD V_LDO GND VD1 VD3 VBAT 2.7V-5.5V GPIO0 INT VD4 VD2 CS1 CS4 ECG Amplifier Analog Electrical Frontend (AFE) Photodiodes Optical Frontend (OFE) ADC I2C & digital control Sequencer CS3 CS4 SIGREF_ECG

Document Feedback AS7038RB

Ordering Information

Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 6

2 Ordering Information

Ordering Code Package Marking Delivery Form Delivery Quantity AS7038RB-COLT OLGA-22 n.a Tape & Reel 5000 pcs/reel AS7038RB-COLM OLGA-22 n.a. Tape & Reel 500 pcs/reel

Document Feedback AS7038RB Pin Assignment Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 7

3 Pin Assignment

3.1 Pin Diagram

Figure 3: Pinout - Top View

3.2 Pin Description

Figure 4: Pin Description of AS7038RB Pin Number Pin Name Pin Type(1) Description

1 VD1 AI Connection to current sink 1

2 GND G Power supply ground. All voltages are referenced to GND.

13 GPIO0

14 GPIO1

15 GPIO2

16 GPIO3

17 V_LDO

18 AGND

19 VD4

20 VD2

SIGREF_ECG 4 SIGREF 3 ECG_INN 6 ECG_REF 7 ENABLE 8 INT 9 SCL 10 SDA 11 Sensor GND 2 21 NC

22 VD3

ECG_INP 5

12 VDD

Document Feedback AS7038RB Pin Assignment Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 8 Pin Number Pin Name Pin Type(1) Description

3 SIGREF AO

Analog reference output. Connect 2.2 µF capacitor to GND (e.g. 0402 sized capacitor GRM153R60J225ME95 or 0201 sized GRM033R60J225ME47 from Murata – needs to have >1 µF specified for 1.0 V voltage bias); do not load externally The typical operating voltage on this pin is

0.6 V (sigref_en=1)

4 SIGREF_ECG AO

Analog reference output. Connect 2.2 µF capacitor to GND (e.g. 0402 sized capacitor GRM153R60J225ME95 or 0201 sized GRM033R60J225ME47 from Murata – needs to have >1 µF specified for 1.0 V voltage bias); do not load externally The typical operating voltage on this pin is

5 ECG_INP AI ECG amplifier positive input

6 ECG_INN AI ECG amplifier negative input

7 ECG_REF AO ECG amplifier reference output

8 ENABLE DI

Enable input for AS7038RB. Active high. Setting this input to low resets all internal registers and the AS7038RB enters power down mode. Setting it high allows operation of the AS7038RB. If ENABLE is not used (AS7038RB always enabled), connect to VDD. 9 INT DO Open drain interrupt output pin. Active low.

10 SCL DI

I²C serial clock input terminal – the device does not use clock stretching therefore SCL is only an input terminal. 11 SDA DI I²C serial data I/O terminal – open drain. 12 VDD P Supply voltage. Connect a 2.2 µF capacitor to GND.

13 GPIO0 GPIO General purpose input/output

14 GPIO1 GPIO General purpose input/output

15 GPIO2 GPIO General purpose input/output

16 GPIO3 GPIO General purpose input/output

17 V_LDO AO 1.9 V output voltage. Connect 2.2 µF capacitor to GND

Document Feedback AS7038RB Pin Assignment Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 9 Pin Number Pin Name Pin Type(1) Description (e.g. 0402 sized capacitor GRM153R60J225ME95 or 0201 sized GRM033R60J225ME47 from Murata – needs to have >1 µF with 1.0 V voltage bias); do not load externally 18 AGND GND Analog ground. Connect to low noise GND

19 VD4 AI Connection to current sink 4

20 VD2 AI Connection to current sink 2

21 NC Not connect

22 VD3 AI Connection to current sink 3

(1) Explanation of abbreviations: DI Digital Input DO Digital Output AI Analog Input AO Analog Output G Ground P Power Supply GPIO General Purpose NC Not Connected

Document Feedback AS7038RB Absolute Maximum Ratings Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 10

4 Absolute Maximum Ratings

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated under “Operating Conditions” is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Figure 5 Symbol Parameter Min Max Unit Comments Electrical Parameters VSUP / VGND Supply Voltage to Ground 6 V VIN Input Pin Voltage to Ground pins GPIO0/1/2/3 -0.3 VDD+0.3 (max. 6V) V Diode to VDD VIN-OTHER Input Pin Voltage to Ground pins SCL/SDA/INT/ENABLE and VD1/VD2/VD3/VD4 -0.3 5.5 V No internal diode to VDD or V_LDO VVD1/2/3/4_INTERNAL Voltage between internal pin of VD1- VD4 to VDD VDD+0.3 V Internal diode between current source (internal node at anode of the LED if the pin has a LED otherwise VD1/2/3/4 pin) and VDD VIN-LDO Input Pin Voltage to Ground for pin V_LDO -0.3 2.0 V Diode to VDD VIN-LDO_DIODE Input Pin Voltage to Ground pins for ECG_INP/ECG_INN/ECG_REF/SIGREF -0.3 2.0 V Diode to V_LDO VGND-AGND Analog to power ground voltage difference -0.3 +0.3 V ISCR Input Current (latch-up immunity) ±100 mA JEDEC JESD78 Electrostatic Discharge ESDHBM Electrostatic Discharge HBM ±2 kV ANSI/ESDA/JEDEC JS-001-2012 Temperature Ranges and Storage Conditions TSTRG Storage Temperature Range -40 85 °C 020 (1) RHNC Relative Humidity (non-condensing) 5 85 % MSL Moisture Sensitivity Level 3 Maximum floor life time of 168h (1) The reflow peak soldering temperature (body temperature) is specified according to IPC/JEDEC J-STD-020 “Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices.” The lead finish for Pb-free leaded packages is “Matte Tin” (100 % Sn)

Document Feedback AS7038RB

Electrical Characteristics

Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 11

5 Electrical Characteristics

All limits are guaranteed. The parameters with Min and Max values are guaranteed with production tests or SQC (Statistical Quality Control) methods. Figure 6: Symbol Parameter Conditions Min Typ Max Unit VDD Supply voltage 2.7 3.8 5.5 V TAMB Operating free-air temperature −30 70 °C IDD Supply current ENABLE=VDD, ldo_en=0; osc_en=0; internal LDO operating in low power mode – only I²C communication possible, no blocks shall be enabled (1) 22 μA ENABLE=VDD, ldo_en=1; osc_en=0; internal LDO operating and bandgap running – I²C communication possible, analog blocks can be enabled(1) 32 μA ENABLE=VDD, ldo_en=1, osc_en=1; internal LDO operating and bandgap and oscillator running – I²C communication possible, analog blocks can be enabled 86 μA SIGREF buffer (sigref_en=1) 52 μA transimpedance amplifier (pd_amp_en=1) 110 μA Optical front end operating (one channel) 200 μA Gain stage (ofe1_gain_en=1 or ofe2_gain_en=1) 75 μA

Document Feedback AS7038RB Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 12 Symbol Parameter Conditions Min Typ Max Unit ADC sampling at 20 Hz with 64 μs settling time 4.5 μA ECG amplifier and frontend (need SIGREF enabled) 190 μA ECG leakage compensation (ecg_low_leakage_en=1), low pass filter, high pass filter and gain stage 151 μA Power down, no I²C communication possible ENABLE=GND(2) 0.5 μA VOL GPIO0-3, INT, SDA output low voltage With 3 mA load With 6 mA load 0 0.4 0.8 V VOH GPIO0-3 output high voltage With 3 mA load 2.3 VDD V VIH GPIO0-3, SCL, SDA, ENABLE input high voltage 1.25 V VIL GPIO0-3, SCL, SDA, ENABLE input low voltage 0.54 V ILEAK1 GPIO0-3, SCL, SDA, ENABLE, INT -1 1 μA ILEAK2 VD1, VD2 VD3, VD4 -3 3 μA E_f2M Tolerance of internal

2 MHz

0 ºC to 70 ºC, VDD<5.0 V -2 2 % -30 ºC to 70 ºC -4 2 % ECG Amplifier and Filter ILEAK_ECG ECG pins leakage current Lab evaluation shows <±20 nA maximum leakage current. Not production tested. ±1 nA

Document Feedback AS7038RB Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 13 Symbol Parameter Conditions Min Typ Max Unit VNOISE_ECG Input referred noise Gain=192 V/V, short circuited inputs, sample rate = 1000sps, BW 0.33 Hz÷100 Hz. Filtered 1.64 μVrms LED Driver ILED1/2/3/4 V_Dmin LED output current range tolerance LED current is adjustable with 10 bits – registers curr1/2/3/4 csx_boost = 0 0 100 mA LED current is adjustable with 10 bits – registers curr1/2/3/4 csx_boost = 1 200 mA At 35 mA output current (currX[9:0]=166 h, X=1…4), VDD<5.0 V -7 7 % V_Dmin Min output voltage compliance csx_boost = 0 0.3 V csx_boost = 1 0.7 V_Dmax Max output voltage compliance 5.5 V Photodiode Area Photodiode area 2.5 mm2 RePD1-4 Irradiance responsivity photodiode PD1…PD4 Wavelength = 550 nm; 4 photodiodes (PD1 - PD4) connected together; TIA resistor (pd_ampres) = 3 MΩ 212 Counts/ (µW/cm2) Irradiance responsivity photodiode B Wavelength = 940 nm; TIA resistor (pd_ampres) = 3 MΩ Id Dark current Ee=0, TAMB =25 °C 0 1 nA Ios Extrapolated offset current TAMB =25 °C -1 1 nA ADC Vref ADC reference voltage 1.6 V Nbit Resolution 14 Bit INL Relative accuracy TAMB =25 °C -8 8 LSB DNL(3) Differential nonlinearity TAMB =25 °C 1.5 LSB Offset error TAMB =25 °C -8 8 LSB

Document Feedback AS7038RB Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 14 Symbol Parameter Conditions Min Typ Max Unit Gain error TAMB =25 °C -8 8 LSB SNR Signal-to- noise ratio Fsample = 1 kHz, Fsignal=100 Hz 80 dB THD Total harmonic distortion Fsample = 1 kHz, Fsignal=100 Hz -70 dB Tconv Conversion rate 14-bit resolution 50 ksps Vin Input voltage range 0 Vref V I²C Mode Timings fSCLK SCL clock frequency 0 400 kHz tBUF Bus free time between a STOP and START condition 1.3 µs tHD:STA Hold time (Repeated) START condition(4) 0.6 µs tLOW LOW period of SCL clock 1.3 µs tHIGH HIGH period of SCL clock 0.6 µs tSU:STA Setup time for a repeated START condition 0.6 µs tHD:DAT Data hold time(5) 0 0.9 µs tSU:DAT Data setup time(6) 100 ns tR Rise time of both SDA and SCL signals 20 300 ns tF Fall time of both SDA and SCL signals 20 300 ns tSU:STO Setup time for STOP condition 0.6 µs

Document Feedback AS7038RB Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 15 Symbol Parameter Conditions Min Typ Max Unit CB Capacitive load for each bus line CB — total capacitance of one bus line in pF 500 pF CI/O I/O pin capacitance (SDA, SCL) 10 pF (1) GPIO0-3 configured to draw minimum current (software dependent). (2) AS7038RB I2C interface active also in power down mode (3) Specified only typical value for DNL to reduce production test time. (4) After this period, the first clock pulse is generated. (5) A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHMIN of the SCL signal) to bridge the undefined region of the falling edge of SCL. (6) Fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT = 250 ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tR max + tSU:DAT = 1000 + 250 = 1250 ns before the SCL line is released. Figure 7: I²C Mode Timing Diagram

Document Feedback AS7038RB Register Description Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 16

6 Register Description

6.1 Register Overview

Figure 8: Register Overview Register Type 1 0x0F GPIO_SYNC Not used Not used Not used Not used Not used gpio_edg e goio_select[1:0] 0x10 LED_CFG sigref_en sigref__e cg_volta ge sigref_ofe_voltage[1: 0] led4_en led3_en led2_en led1_en 0X11 LED_WAIT_L OW led_wait_low[7:0] 0X12 LED1_CURRL Curr1[1:0] Not used Not used Not used Not used Not used cs1_boo st 0X13 LED1_CURR H Curr1[9:2] 0X14 LED2_CURRL Curr2[1:0] Not used Not used Not used Not used Not used cs2_boo st 0X15 LED2_CURR H Curr2[9:0] 0X16 LED3_CURRL Curr3[1:0] Not used Not used Not used Not used Not used cs3_boo st 0X17 LED3_CURR H Curr3[9:2] 0X18 LED4_CURRL Curr4[1:0] Not used Not used Not used Not used Not used cs4_boo st 0X19 LED4_CURR H Curr4[9:2] 0X2C LED12_MOD E Man- sw_led2 Led2_mode[2:0] Man_sw _led1 Led1_mode[2:0] 0X2D LED34_MOD E Man- sw_led4 Led4_mode[2:0] Man- sw_led3 Led3_mode[2:0] 0X2E MAN_SEQ_C FG man_mo de man_sw _sdmult man_sw _sdpol man_sw _itg diode_ctrl[2:0] seq_en 0X1A PD_CFG Not used pd_boost pd4 pd3 pd2 pd1 pd_i1 pd_i0 0X1B PDOFFX_LE DOFF pdoffx_ledoff[7:0] 0X1C PDOFFX_LE DON pdoffx_ledon[7:0] 0X1D PD_AMPRCC FG pd_ampres[2:0] pd_ampcap[4:0] 0X1E PD_AMPCFG pd_amp_ en pd_amp_ auto pd_ampvo[3:0] pd_ampcomp[1:0]

Document Feedback AS7038RB Register Description Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 17 0X1F OFE1_PD_T HCFG ofe1_pd_clipdetect_h_thresh[3:0] ofe1_pd_clipdetect_l_thresh[3:0] 0X30 SEQ_CNT seq_count[7:0] 0X31 SEQ_DIV seq_div[7:0] 0X32 SEQ_START Not used Not used Not used Not used Not used seq_start _gpio seq_start _sync seq_start 0X33 SEQ_PER seq_period[7:0] 0X34 SEQ_LED_S TA seq_led_ start[7:0] 0X35 SEQ_LED_S TO seq_led_stop[7:0] 0X36 SEQ_SECLE D_STA seq_secled_start[7:0] 0X37 SEQ_SECLE D_STO seq_secled_stop[7:0] 0X38 SEQ_ITG_ST A seq_itg_start[7:0] 0X39 SEQ_ITG_ST O seq_itg_stop[7:0] 0X3A SEQ_SDP1_ STA seq_sdp1_start[7:0] 0X3B SEQ_SDP1_ STO seq_sdp1_stop[7:0] 0X3C SEQ_SDP2_S TA seq_sdp2_start[7:0] 0X3D SEQ_SDP2_ STO seq_sdp2_stop[7:0] 0X3E SEQ_SDM1_ STA seq_sdm1_start[7:0] 0X3F SEQ_SDM1_ STO seq_sdm1_stop[7:0] 0X40 SEQ_SDM2_ STA seq_sdm2_start[7:0] 0X41 SEQ_SDM2_ STO seq_sdm2_stop[7:0] 0X42 SEQ_ADC seq_adc[7:0] 0X43 SEQ_ADC2TI A seq_adc2tia[7:0] 0X44 SEQ_ADC3TI A seq_adc3tia[7:0] 0X45 SD_SUBS sd_subs[7:0] 0X46 SEQ_CFG Not used Not used Not used Not used Not used Not used Not used sd_subs _always 0X47 SEQ_ERR irq_adc_t iming_err or Not used Not used Not used Not used Not used Not used Not used 0X48 SEQ_OVS_S EL ovs_sel2 ovs_sel1 0X49 SEQ_OVS_V AL Not used ovs_val2 Not used ovs_val1

Document Feedback AS7038RB Register Description Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 18 0X4A SEQ_DIS_SE L dis_sel2[3:0] dis_sel1[3:0] 0X4B SEQ_DIS_VA L1 seq_dis_val1[7:0] 0X4C SEQ_DIS_VA L2 Seq_dis_val2[7:0] 0X60 CYC_COUNT ER cycle_counter[7:0] 0X61 SEQ_COUNT ER sequence_counter[7:0] 0X62 SUBS_COUN TER subs_counter[7:0] 0X50 OFE_CFGA ofe2_en ofe1_en en_bias_ ofe aa_freq[1:0] gain_sd[2:0] 0X51 OFE1_SD_TH CFG ofe1_sd_clipd_h_thresh [3:0] ofe1_sd_clipd_l_thresh [3:0] 0X52 OFE_CFGC Not used prefilter_ aa_byp prefilter_ hp_byp prefilter_ gain_byp prefilter_ bypass_ en prefilter_ aa_en prefilter_ hp_en prefilter_ gain_en 0X53 OFE_CFGD Not used notch_bw[1:0] ofe_sd_hp[2:0] ofe_gs_aa[1:0] 0X54 OFE1_CFGA ofe1_sd_ pol_init ofe1_sd_ en ofe1_hp_ en ofe1_gai n_en ofe1_sd _byp ofe1_hp_ byp ofe1_gai n_byp ofe1_sd_ hld 0X55 OFE1_CFGB ofe1_gain_g[2:0] ofe1_sd_bw[2:0] ofe1_hp_freq[1:0] 0X56 OFE2_PD_T HCFG ofe2_pd_clipd_h_thresh[3:0] ofe2_pd_clipd_l_thresh[3:0] 0X57 OFE2_SD_T HCFG ofe2_sd_clipd_h_thresh[3:0] ofe2_sd_clipd_l_thresh[3:0] 0X58 OFE2_CFGA ofe2_sd_ pol_init ofe2_sd_ en ofe2_hp_ en ofe2_gai n_en ofe2_sd _byp ofe2_hp_ byp ofe2_gai n_byp ofe2_sd_ hld 0X59 OFE2_CFGB ofe2_gain_g[2:0] ofe2_sd_bw[1:0] ofe2_hp_freq[1:0] 0X20 LTFDATA0_L ltfdata0[7:0] 0X21 LTFDATA0_H ltfdata0[15:8] 0X22 LTFDATA1_L ltfdata0[7:0] 0X23 LTFDATA1_H ltfdata1[15:8] 0X24 ITIME Itime[7:0] 0X25 LTF_CONFIG infinite_iti me az_disab le_auto az_mode[1:0] Not used ltf_prox_ mode ltf_fifo_m ode ltf_enabl e 0X26 LTF_SEL Do not use ltf1_sel[2:0] Not used ltf0_sel[2:0] 0X27 LTF_GAIN Do not use Do not use itime_unit[1:0] ltf_gain[3:0] 0X28 LTF_CONTR OL Do not use Do not use Do not use Do not use Do not use Do not use Do not use ltf_start 0X29 AZ_CONTRO L Do not use Do not use Do not use Do not use Do not use Do not use az_enabl e_1 az_enabl e_0 0X2A OFFSET0 offset0[7:0] 0X2B OFFSET1 offset0[7:0]

Document Feedback AS7038RB Register Description Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 19 0X6C LTF_THRESH OLD_LOW0 ltf_threshold_low[7:0] 0X6D LTF_THRESH OLD_LOW1 ltf_threshold_low[15:8] 0X6E LTF_THRESH OLD_HIGH0 ltf_threshold_High[7:0] 0X6F LTF_THRESH OLD_HIGH1 ltf_threshold_lhigh15:8] 0X70 EAF_CFG Do not use Do not use Do not use Do not use afe_ena b afe_enab _dac afe_enab _dac_buf afe_ena b_gainst age 0X80 EAF_GST gpio_gst_in[2:0] gst_ref[1:0] gst_gain[2:0] 0X81 EAF_BIAS gpio_r_bias[2:0] Not used Not used Not used Not used Not used 0X82 EAF_DAC Do not use Do not use Do not use sigref_on _dac_buf measure _dac gpio_dac[2:0] 0X83 EAF_DAC1_L dac1_value[] Not used Not used Not used Not used Not used Not used 0X84 EAF_DAC1_H dac1_value[9:2] 0X85 EAF_DAC2_L dac2_value[1:0] Not used Not used Not used Not used Not used Not used 0X86 EAF_DAC2_H dac2_value[9:2] 0X87 EAF_DAC_CF G Not used Not used Not used Not used Not used Not used dac_mode[1:0] 0X5A OFE_NOTCH Not used ofe2_not ch_sel60 ofe2_not ch_byp ofe2_not ch_en Not used ofe1_not ch_sel60 ofe1_not ch_byp ofe1_not ch_en 0X5B ECG_MODE ecg_notc h_sel60 ecg_hp_mode[2:0] ecg_gain_g2[1:0] ecg_gain_g1[1:0] 0X5C ECG_CFGA ecg_en ecg_clk_ off ecg_gain _byp ecg_lp_b yp ecg_notc h_byp ecg_diff_ byp ecg_hp_byp[1:0] 0X5D ECG_CFGB ecg_fast _startup ecg_lp_freq[1:0] ecg_hp_freq[1:0] ecg_gain_g[2:0] 0X6A ECG_THRES HOLD_LOW ecg_threshold_low[7:0] 0X6B ECG_THRES HOLD_HIGH ecg_threshold_high[7:0] 0X5E ECG_CFGC Not used Not used Not used Not used Not used Not used ecg_low _leakage _en ecg_ref_ en 0X5F ECG_CFGD Not used Not used Not used ecg_lead sdet_syn c_adc ecg_lead sdet_pol ecg_leadsdet_curr[1: ecg_lead sdet_en 0X68 ADC_THRES HOLD adc_threshold[7:0] 0X69 ADC_THRES HOLD_CFG Not used Not used Not used Not used Not used Not used adc_thre sh_differ ential adc_thre sh_tiaonl y 0X88 ADC_CFGA Not used Not used Not used Not used adc_multi_n[2:0] adc_mult imode 0X89 ADC_CFGB Not used Not used adc_clock[2:0] adc_calib ration ulp adc_en 0X8A ADC_CFGC Not used Not used Not used adc_self pd adc_disc harge adc_settling_time[2:0]

Document Feedback AS7038RB Register Description Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 20 0X8B ADC_CHANN EL_MASK_L adc_cha nnel_ma sk_prega in adc_cha nnel_ma sk_afe adc_cha nnel_ma sk_temp adc_cha nnel_ma sk_sd2 adc_cha nnel_ma sk_ofe2 adc_cha nnel_ma sk_sd1 adc_cha nnel_ma sk_ofe1 adc_cha nnel_ma sk_tia 0X8C ADC_CHANN EL_MASK_H Not used Not used Not used Not used adc_cha nnel_ma sk_gpio2 adc_cha nnel_ma sk_gpio3 adc_cha nnel_ma sk_ecgi adc_cha nnel_ma sk_ecgo 0X8E ADC_DATA_ L adc_data[7:0] 0X8F ADC_DATA_ H Not used Not used adc_data[13:8] 0X78 FIFO_CFG Not used fifo_threshold[6:0] 0X79 FIFO_CNTRL Not used Not used Not used Not used Not used Not used Not used fifo_clear 0XFE FIFOL Fifol[7:0] 0XFF FIFOH Fifoh[7:0] 0x00 CONTROL Not used Not used Not used hs_en Not used clk_def osc_en ldo_en 0X08 GPIO_A Not used Not used Not used Not used gpio3_a gpio2_a gpio1_a gpio0_a 0X09 GPIO_E Not used Not used Not used Not used gpio3_e gpio2_e gpio1_e gpio0_e 0X0A GPIO_O Not used Not used Not used Not used gpio3_o gpio2_0 gpio1_0 gpio0_0 0X0B GPIO_I Not used Not used Not used Not used gpio3_i gpio2_i gpio1_i gpio0_i 0X0C GPIO_P gpio3_pd gpio3_pu gpio2_pd gpio2_pu gpio1_p d gpio1_pu gpio0_pd gpio0_pu 0X0D GPIO_SR Not used Not used Not used Not used gpio3_sr gpio2_sr gpio1_sr gpio0_sr 0X91 SUBID subid[4:0] Revision[2:0] 0X92 ID id[5:0] id_reserved[1:0] 0XA0 STATUS irq_led_s upply_lo w irq_clipd etect irq_fifoov erflow irq_fifothr eshold irq_adc_t hreshold irq_ltf irq_sequ encer irq_adc 0XA1 STATUS2 Not used Not used Not used Not used Not used irq_ltf_thr eshold_h igh irq_ltf_thr eshold_l ow irq_ecg_t hreshold 0XA2 CLIPSTATUS Not used Not used Not used Not used pd_clipd etect_l pd_clipd etect_h sd_clipd etect_l sd_clipd etect_h 0XA3 LEDSTATUS Not used Not used Not used Not used led4_sup ply_low led3_sup ply_low led2_sup ply_low led1_sup ply_low 0XA4 FIFOSTATUS Not used Not used Not used Not used Not used Not used Not used fifooverfl ow 0XA5 LTFSTATUS Not used Not used ltf1_thres hold_hig h ltf1_thres hold_low ltf0_thres hold_hig h ltf0_thres hold_low ltf_sat ltf_done 0XA6 FIFOLEVEL fifolevel[7:0] 0XA8 INTENAB irq_led_s upply_lo w_enab irq_clipd etect_en ab irq_fifoov erflow_e na irq_fifothr eshold_e nab irq_adc_t hreshold _enab irq_ltf_en ab irq_sequ encer_en ab irq_adc_ enab 0XA9 INTENAB2 Not used Not used Not used Not used Not used irq_ltf1_t hreshold _enab irq_ltf0_t hreshold _enab irq_ecg_t hreshold _enab 0XAA INTR irq_led_s upply_lo w_intr irq_clipd etect_intr irq_fifoov erflow_in tr irq_fifothr eshold_i ntr irq_adc_t hreshold _intr irq_ltf_int r irq_sequ encer_int r irq_adc_i ntr

Document Feedback AS7038RB Register Description Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 21 0XAB INTR2 Not used Not used Not used Not used Not used irq_ltf_thr eshold_h igh_intr irq_ltf_thr eshold_l ow_intr irq_ecg_t hreshold _intr

Document Feedback AS7038RB Functional Description Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 22

7 Functional Description

7.1 Optical Analog Front End

Figure 9: Optical Analog Front End The optical front end is used for PPG measurements. The OFE consist of:

• 4 LEDs drivers individually configurable, operated manually or controlled by the built -in Sequencer. GPIO0 pd1 pd2 pd3 pd4 pd_i0 pd_ampcap pd_ampres pdoffx pd_amp_en ADC ofe1/2_sd_byp Synchronous Demodulator1,2 + BP Filter + Gain Stages TIA ofe1/2_hp_byp ofe1/2_sd_bw aa_freq 12.5-200Hz ofe1/2_en ofe1/2_hp_freq ofe1/2_hp_en ofe1/2 _gain_g Sequencer VD2 -1/0/float/+1 sample reset VD3 Clip Det Clip Det select select gain_sd h/l vth h/l vth -1/0/float/+1 FiFo Prefilter pdoffx_ledon any LED on? fifol, fifoh pregain ofe1 ofe2 sd1 sd2 tia pd_i1 Photodiode B VD4 VD1 ofe_notch _sel60 ecg_notch_byp

Document Feedback AS7038RB Functional Description Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 23

• 6 Photodiodes
• 4 with RED/IR filters (PD1, PD2 PD3 and PD4)
• 1 with IR filter (PD B)
• 1 clear (PD A) only connected to Light-to-Frequency block
• TIA
• Trans-Impedance Amplifier
• PREFILTER
• LP & HP Filter and variable Gain Stage
• Synchronous Demodulators
• SD_OFE1, SD_OEF2 with LP 6 HP filter and gain stage The first Block in signals path is the TIA. The TIA converts the current from Photodiodes into a voltage. The trans-impedance of TIA can be adjusted in 7 steps. After the TIA follow the PREFILTER. PREFILTER includes a low pass filter with adjustable cut-off frequency, a high pass filter and a variable gain stage. This block can be bypassed. The output signal of PREFILTER is used as input for the blocks SD_OFE1 and SD_OFE2. These Block are identically built and can work in parallel. Both consists of synchronous demodulator, a low-pass filter, a high pass filter and variable gain stage. The sequencer does the control of the whole signal path, which is part of digital part. In addition to these main blocks, there are two smaller blocks for detection of clipping signals inside the blocks. The TIA Clip detection observes the output of TIA and SD Clip detection observe the output of PREFILTER Block. The limits for clip detection can adjusted by digital part.

7.1.1 LED-Driver

The AS7038RB contain 4 identical LED driver circuits. The LED-driver outputs can be controlled manually or by the built in sequencer. See section 7.1.8 Optical Front End Operating Modes Information The integration time t INT is defined either by the sequencer (man_mode=0) of manually through the bit sw_itg if man_mode=1. For the synchronous demodulator only use the resistive feedback.

Document Feedback AS7038RB Functional Description Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 24 Figure 10: LED Drivers

7.1.2 LED Driver Configuration

LED_CFG Register (Address 0x10) Figure 11: LED_CFG Register Addr: 0x10 LED_CFG Bit Bit Name Default Access Bit Description 7 sigref_en 0 RW Signal reference: Is required for all analog blocks (except PD_Amp or light-to-frequency operation) 0: Disable signal reference 1: Enable signal reference X=4 Sequencer VD1 VD2 max. compliance Q Q SET CLR S R write 1 to register irq_led_supply_low ledX_supply _low and irq_led_ supply_low currX ledX_en man_mode man_sw_ledX ledX_mode VD3 X=1 X=2 X=3 D1 D2 D3 D4 VD4

Document Feedback AS7038RB Functional Description Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 25 Addr: 0x10 LED_CFG Bit Bit Name Default Access Bit Description 6 sigref_ecg_voltage 0 RW Voltage setting of SIGREF_ECG – datasheet parameters are guaranteed only for default value of 0.9 V Setting Voltage 0 0.9 V (default) 1 0.8 V 5:4 sigref_ofe_voltage 0 RW Voltage setting of SIGREF – datasheet parameters are guaranteed only for default value of 0.6 V. Setting IMAX 00 0.6 V (default) 01 0.7 V 10 0.8 V 11 0.9 V 3 led4_en 0 RW 0: Disables LED4 output source. 1: Enables LED4 output source. 2 led3_en 0 RW 0: Disables LED3 output source. 1: Enables LED3 output source. 1 led2_en 0 RW 0: Disables LED2 output source. 1: Enables LED2 output source. 0 led1_en 0 RW 0: Disables LED1 output source. 1: Enables LED1 output source. The LED_CURR defines the LED output current. LED_WAIT_LOW Register (Address 0x11) Figure 12: LED_WAIT_LOW Register Addr: 0x11 LED_WAIT_LOW Bit Bit Name Default Access Bit Description 7:0 Led_wait_low 0 RW Time = led_wait_low *1 μs LED_WAIT_LOW defines the time between the switching on of an LED and the beginning of voltage monitoring. All LEDs use the same time.

Document Feedback AS7038RB Functional Description Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 27 LED2_CURRL Register (Address 0x14) Figure 15: LED2_CURRL Register Addr: 0x14 LED2_CURRL Bit Bit Name Default Access Bit Description 7:6 Curr2[1:0] 0 RW LED2 output current lower 2 bits 5:1 Not used 0 RW Not used

0 Cs2_boost 0 RW

0: Imax = 100 mA, 1 LSB=97 µA 1: Imax = 200 mA, 1 LSB=194 µA LED2_CURRH Register (Address 0x15) Figure 16: LED2_CURRH Register Addr: 0x15 LED2_CURRH Bit Bit Name Default Access Bit Description 7:0 Curr2[9:2] 0 RW LED2 output current upper 8 bits Coding for curr1[9:0]: 000h: 786 µA 001h: 883 µA (1 LSB=97 µA with cs1_boost = 0) 002h: 980 µA 166h: 35 mA 3FFh: 100 mA LED3_CURRL Register (Address 0x16) Figure 17: LED3_CURRL Register Addr: 0x16 LED3_CURRL Bit Bit Name Default Access Bit Description 7:6 Curr3[1:0] 0 RW LED3 output current lower 2 bits 5:1 Not used 0 RW Not used

0 Cs3_boost 0 RW

0: Imax = 100 mA, 1 LSB=97 µA 1: Imax = 200 mA, 1 LSB=194 µA

Document Feedback AS7038RB Functional Description Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 28 LED3_CURRH Register (Address 0x17) Figure 18: LED3_CURRH Register Addr: 0x17 LED3_CURRH Bit Bit Name Default Access Bit Description 7:0 Curr3[9:2] 0 RW LED3 output current upper 8 bits Coding for curr1[9:0]: 000h: 786 µA 001h: 883 µA (1 LSB=97 µA with cs1_boost = 0) 002h: 980 µA 166h: 35 mA 3FFh: 100 mA LED4_CURRL Register (Address 0x18) Figure 19: LED4_CURRL Register Addr: 0x18 LED4_CURRL Bit Bit Name Default Access Bit Description 7:6 Curr4[1:0] 0 RW LED4 output current lower 2 bits 5:1 Not used 0 RW Not used

0 Cs4_boost 0 RW

0: Imax = 100 mA, 1 LSB=97 µA 1: Imax = 200 mA, 1 LSB=194 µA LED4_CURRH Register (Address 0x19) Figure 20: LED4_CURRH Register Addr: 0x19 LED4_CURRH Bit Bit Name Default Access Bit Description 7:0 Curr4[9:2] 0 RW LED4 output current upper 8 bits Coding for curr1[9:0]: 000h: 786 µA 001h: 883 µA (1 LSB=97 µA with cs1_boost = 0) 002h: 980 µA

Document Feedback AS7038RB Functional Description Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 29 Addr: 0x19 LED4_CURRH Bit Bit Name Default Access Bit Description 166h: 35 mA 3FFh: 100 mA LED12_MODE Register (Address 0x2c) Figure 21: LED12_MODE Register Addr: 0x2c LED12_MODE Bit Bit Name Default Access Bit Description 7 man-sw_led2 0 RW Function enabled only in manual mode 0: LED output D2 disabled. (High impedance) 1: LED output D2 enabled 6:4 led2_mode 0 RW LED2 mode Settings Behavior

000 Always OFF

001 Always ON when sequencer is active

010 Controlled by sequencer

011 Controlled by sequencer, only ON in

even iterations: 0, 2, 4 etc.

100 Controlled by sequencer, only ON in

odd iterations: 1, 3, 5 etc. 101 Controlled by sequencer, only ON in every fourth iteration, starting at 1:1, 5, 9 etc.

110 Controlled by sequencer: secondary

111 Do not use

3 man_sw_led1 0 RW Function enabled only in manual mode 0: LED output D1 disabled. (High impedance) 1: LED output D1 enable 2:0 led1_mode 0 RW LED1 mode Settings Behavior

Document Feedback AS7038RB Functional Description Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 30 Addr: 0x2c LED12_MODE Bit Bit Name Default Access Bit Description even iterations: 0, 2, 4 etc. odd iterations: 1, 3, 5 etc. 101 Controlled by sequencer, only ON in every fourth iteration, starting at 1: 1, 5, 9 etc. LED34_MODE Register (Address 0x2d) Figure 22: LED34_MODE Register Addr: 0x2d LED34_MODE Bit Bit Name Default Access Bit Description 7 man-sw_led4 0 RW Function enabled only in manual mode 0: LED output D4 disabled. (High impedance) 1: LED output D4 enabled 6:4 led4_mode 0 RW LED4 mode Settings Behavior even iterations: 0, 2, 4 etc. odd iterations: 1, 3, 5 etc. 101 Controlled by sequencer, only ON in every fourth iteration, starting at 1: 1, 5, 9 etc.

Document Feedback AS7038RB Functional Description Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 31 Addr: 0x2d LED34_MODE Bit Bit Name Default Access Bit Description 3 man_sw_led3 0 RW Function enabled only in manual mode 0: LED output D3 disabled. (High impedance) 1: LED output D3 enable 2:0 led3_mode 0 RW LED3 mode Settings Behavior even iterations: 0, 2, 4 etc. odd iterations: 1, 3, 5 etc. 101 Controlled by sequencer, only ON in every fourth iteration, starting at 1: 1, 5, 9 etc. The MAN_SEQ_CFG register is used to configure the operation of the optical front end MAN_SEQ_CFG Register (Address 0x2e) Figure 23: MAN_SEQ_CFG Register Addr: 0x2e MAN_SEQ_CFG Bit Bit Name Default Access Bit Description 7 man_mode 0 RW 0: Enables sequencer 1: Enables manual control of optical front end 6 man_sw_sd mult 0 RW If man_mode=1 0: Disables synchronous demodulator multiplication 1: Enables synchronous demodulator multiplication 5 man_sw_sd pol 0 RW If man_mode=1 0: Negative polarity in synchronous demodulator multiplication 1: Positive polarity in synchronous demodulator multiplication

Document Feedback AS7038RB Functional Description Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 32 Addr: 0x2e MAN_SEQ_CFG Bit Bit Name Default Access Bit Description 4 man_sw_itg 0 RW If man_mode=1 0: All integrator capacitors are shorted. Integrator is reset 1: Integrator capacitors are charging up. Integrator is running 3:1 diode_ctrl 0 RW Connection of Photodiodes PD1, PD2, PD3, PD4 to the photodiode amplifier. 0: PD1-PD4 are connected 1: PD1 synchronous to LED1, PD2 sync/to LED2 PD3 sync/to LED3, PD4 sync/to LED4 2:PD1 synchronous to LED1, PD2 sync/to LED1 PD3 sync/to LED2, PD4 sync/to LED2 3: PD1 synchronous to LED1, PD2 sync/to LED1 PD3 sync/to LED4, PD4 sync/to LED4 4: SPO2 mode *(obsolete): (negedge(sdm1) or negedge(sdp1)) - PD1=0 PD2=0 PD3=1 PD4=1; (negedge(sdm2) or negedge(sdp2)) - PD1=1 PD2=1 PD3=0 PD4=0 Note that PD_CFG.pdX takes precedence - to turn OFF one photo diode, the respective bit has to be de- asserted in the PD_CFG register. PD_CFG . pdX diode_ ctrl Photo Diode Photo Diode Photo Diode Photo Diode 0 xx OFF OFF OFF OFF 1 0 ON ON ON ON 1 1 LED1 LED2 LED3 LED4 1 2 LED1 LED1 LED2 LED2 1 3 LED1 LED1 LED4 LED4 1 4 SPO2 mode (obsolete) 1 5..7 Do not use 0 seq_en 0 RW 0: Disables sequencer 1: Enables sequencer

Document Feedback AS7038RB Functional Description Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 33 LEDSTATUS Register (Address 0xa3) Figure 24: LEDSTATUS Register Addr: 0xa3 LEDSTATUS Bit Bit Name Default Access Bit Description 7:4 NA 0 RO Not used 3 led4_supply_low 0 RO If this bit is asserted, LED4 voltage has been too low. 2 led3_supply_low 0 RO If this bit is asserted, LED3 voltage has been too low. 1 led2_supply_low 0 RO If this bit is asserted, LED2 voltage has been too low. 0 led1_supply_low 0 RO If this bit is asserted, LED1 voltage has been too low. An asserted bit can be cleared by either writing a '1' to the STATUS.clipdetect bit (in normal mode) or by reading the CLIPSTATUS register (clear on read mode)

7.1.3 Photodiode Selection

In order to have flexible arrangement of the use photodiodes, PD1-PD4 can be individually connected to the photodiode amplifier input. The optional offset current allows cancellation of constant light sources like sunlight. In case of an external photodiode or any other sensor with (low) current output, the pins GPIO0 and GPIO1 can be used as input. Additionally the sequencer can control the diodes – see diode_ctrl described in register MAN_SEQ_CFG.

Document Feedback AS7038RB Functional Description Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 34 Figure 25: Photodiode Selection PD_CFG Register (Address 0x1a) Figure 26: PD_CFG Register Addr: 0x1a PD_CFG Bit Bit Name Default Access Bit Description

7 NA 0 RW Not used

pd_boost RW pd_boost = 0 pdoffx_ledoff lsb = 10 nA pdoffx_ledon lsb = 10 nA pd_boost = 1 pdoffx_ledoff lsb = 20 nA pdoffx_ledoonlsb = 20 nA 5 pd4 0 RW 0: Photodiode PD4 is disconnected from photo amplifier 1: Photodiode PD4 is connected to photo amplifier (as defined in diode_ctrl) 4 pd3 0 RW 0: Photodiode PD3 is disconnected from photo amplifier 1: Photodiode PD3 is connected to photo amplifier (as defined in diode_ctrl) GPIO0 pd1 pd2 pd3 pd4 pd_i0 to TIA (Trans-Impedance-Amplifier) pdoffx pdoffx_ledon any LED on? pd_i1 Photodiode B

Document Feedback AS7038RB Functional Description Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 35 Addr: 0x1a PD_CFG Bit Bit Name Default Access Bit Description 3 pd2 0 RW 0: Photodiode PD2 is disconnected from photo amplifier 1: Photodiode PD2 is connected to photo amplifier (as defined in diode_ctrl) 2 pd1 0 RW 0: Photodiode PD1 is disconnected from photo amplifier 1: Photodiode PD1 is connected to photo amplifier (as defined in diode_ctrl) 1 pd_i1 0 RW 0: Photodiode B (see Photodiode Characteristics) disconnected from TIA input 1: Photodiode B (see Photodiode Characteristics) connected to TIA input; set ltf1_sel=0 and ltf2_sel=0. 0 pd_i0 0 RW 0: GPIO0-input is disconnected from photo amplifier 1: GPIO0-input is connected to photo amplifier; set gpio_a[0]=1. The PD_CFG register is used to configure the input to the photo amplifier. PDOFFX_LEDOFF Register (Address 0x1b) Figure 27: PDOFFX_LEDOFF Register Addr: 0x1b PDOFFX_LEDOFF Bit Bit Name Default Access Bit Description 7:0 pdoffx_ledoff 0 RW Input offset current if all LEDs are OFF (all sw_led* sequencer outputs are zero) Ioffset = pdoffx_ledoff*10 nA if PD_CFG[6] = 0 Ioffset = pdoffx_ledoff*20 nA if PD_CFG[6] = 1 0: Offset source is turned OFF

Document Feedback AS7038RB Functional Description Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 36 PDOFFX_LEDON Register (Address 0x1c) Figure 28: PDOFFX_LEDON Register Addr: 0x1c PDOFFX_LEDON Bit Bit Name Default Access Bit Description 7:0 pdoffx_ledon 0 RW Input offset current if at least one LED is ON (one or more sw_led* sequencer outputs are non-zero) Ioffset = pdoffx_ledon*10 nA if PD_CFG[6] = 0 Ioffset = pdoffx_ledon*20 nA if PD_CFG[6] = 1 0: Offset source is turned OFF

7.1.4 Photodiode Characteristics

Figure 29: Photodiode Arrangement –Orientation as in Figure 2 Sensor PD1 PD2 PD3 PD4 P D A P D B 1.67 mm 1.5 mm

Document Feedback AS7038RB Functional Description Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 37 Figure 30: Photodiode Filter Implementation For operation and characteristics of photodiode ‘PDA’ and photodiode ‘PDB’ see section 7.1.13 Light- to-Frequency Mode PDB IR PDA Clear PD1 PD2 PD3 PD4

Document Feedback AS7038RB Functional Description Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 38 Figure 31: Photodiode Sensitivity (solid black) and LED Emission Spectrum (dotted red and dotted black) Information All 4 photodiodes used pd1/2/3/4=1; perpendicular light source and no diffusor used on AS7038RB.

7.1.5 Photodiode Trans-Impedance Amplifier (TIA)

The Trans-Impedance Amplifier is used to convert the photocurrent to the voltage. The photodiode amplifier can be configured in two different modes:

• Photocurrent to voltage converter
• Photocurrent integrator TIA block also includes a clip detection block.

Document Feedback AS7038RB Functional Description Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 40 pd_ampres pd1234(1) pd_ampcap pd_ampcomp pd_ampvo gain Low Bandwidth Mode 5 1…4 31 3 15 7 V/µA Integrating Mode (pd_ampres=0) 0 1…4 10 3 15 1 V/pQ 0 1…4 20 3 15 1/2V/pQ 0 1…4 30 3 15 1/3V/pQ (1) pd1234 … number of active photodiodes (for example, pd1=1, pd2=0, pd3=1, pd4=0 -> pd1234=2)

7.1.6 Photodiode TIA Registers

PD_AMPRCCFG Register (Address 0x1d) Figure 34: PD_AMPRCCFG Register Addr: 0x1d PD_AMPRCCFG Bit Bit Name Default Access Bit Description 7:5 pd_ampres 0 RW Feedback resistor Setting Resistance No resistor in feedback of amplifier – photocurrent integrator 1 1 MΩ 2 2 MΩ 3 3 MΩ 4 5 MΩ 5 7 MΩ 6 10 MΩ 7 15 MΩ 4:0 pd_ampcap Feedback capacitor =pd_ampcap * 0.1 pF The PD_AMPCFG register is used to configure the operating mode of the photoamplifier.

Document Feedback AS7038RB Functional Description Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 42 Addr: 0x1f OFE1_PD_THCF Bit Bit Name Default Access Bit Description 8: 1216 mV 9: 1140 mV 10: 1064 mV 11: 988 mV 12: 912 mV 13: 836 mV 14: 760 mV 15: 684 mV 3:0 ofe1_pd_clipdetect_l_thresh 0 RW If the voltage on the output of the OFE2 falls below this threshold the irq_clipdetect interrupt is asserted. The threshold is defined as 0: 76.2 mV 1: 152 mV 2: 228 mV 3: 304 mV 4: 380 mV 5: 456 mV 6: 532 mV 7: 608 mV 8: 684 mV 9: 760 mV 10: 836 mV 11: 912 mV 12: 988 mV 13: 1064 mV 14: 1140 mV 15: 1216 mV

Document Feedback AS7038RB Functional Description Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 43 OFE2_PD_THCFG (Address 0x56) Figure 37: OFE2_PD_THCFG Register Addr: 0x56 OFE2_PD_THCFG Bit Bit Name Default Access Bit Description 7:4 ofe2_pd_clipd_h_thresh 0 RW If the voltage on the output of the TIA exceed this threshold, the irq_clipdetect interrupt is asserted. The threshold is defined as 0: 1824 mV 1: 1748 mV 2: 1672 mV 3: 1596 mV 4: 1520 mV 5: 1444 mV 6: 1368 mV 7: 1292 mV 8: 1216 mV 9: 1140 mV 10: 1064 mV 11: 988 mV 12: 912 mV 13: 836 mV 14: 760 mV 15: 684 mV 3:0 ofe2_pd_clipd_l_thresh 0 RW If the voltage on the output of the OFE2 falls below this threshold, the irq_clipdetect interrupt is asserted. The threshold is defined as 0: 76.2 mV 1: 152 mV 2: 228 mV 3: 304 mV 4: 380 mV 5: 456 mV 6: 532 mV 7: 608 mV 8: 684 mV

Document Feedback AS7038RB Functional Description Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 44 Addr: 0x56 OFE2_PD_THCFG Bit Bit Name Default Access Bit Description 9: 760 mV 10: 836 mV 11: 912 mV 12: 988 mV 13: 1064 mV 14: 1140 mV 15: 1216 mV

7.1.7 Voltage Mode of the Photodiode Amplifier

The output voltage of the photodiode amplifier is depending on the feedback component. Equation 1: 𝑈𝑜𝑢𝑡 = 𝐼𝑝ℎ𝑜𝑡𝑜 ∙ 𝑅𝑓𝑏 Feedback resistor Equation 2: 𝑈𝑜𝑢𝑡 = 𝐼𝑝ℎ𝑜𝑡𝑜 ∙ 𝑡𝐼𝑁𝑇 𝐶𝑓𝑏 Feedback capacitor Figure 38: Difference Between Resistive and Capacitive Feedback (1) Green: Capacitive Integration Green Dotted: Effective Value from Capacitive Mode Blue: Resistive Feedback Red: Light Intensity

Document Feedback AS7038RB Functional Description Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 45 Information The integration time t INT is defined either by the sequencer (man_mode=0) of manually through the bit sw_itg if man_mod e=1. For the synchronous demodulator only use the resistive feedback.

7.1.8 Optical Front End Operating Modes

Once the photodiode amplifier is configured the measurement can be done in two different ways. Either the LED-outputs, the photodiode amplifier and the ADC are controlled manually by means of register bits, or they are controlled by a built in sequencer. Manual Operation of the Optical Frontend: The optical front end can be manually controlled via the register man_mode=1 Figure 39: Optical Frontend (1) Applies only if man_mode=1 For manual operation of the LEDs and its current sinks see 7.1.1 LED-Driver

7.1.9 Sequencer

In order to synchronize the LED-currents, the integration time and the ADC-sampling time, a built in sampling sequencers can be used. The sequencer generates the 8-bit-timings based on a 1 µs clock pd_ampcap pd_ampres pd_amp_en man_sw_itg pd1 pd2 pd3 pd4 pdi_1 pdi_0 ADC adc_channel_mask_tia is set? Start conversion: seq_en=1 End of conversion: seq_en returns to 0 pdoffx pdoffx_ledon any LED on? GPIO0

Document Feedback AS7038RB Functional Description Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 46 which can be pre-scaled with seq_div. The results of the analog to digital conversion are automatically stored in a pipeline buffer or in register adc_data and the ADC FIFO. The timings can be programmed with following registers (apply for man_mode=0): Figure 40: Timing Registers Register Description seq_div Divider of the 1 µs input clock for all sequencer timings seq_count Number of measurements in one sequence seq_start Writing 1 starts the sequencer, 0 stops the sequencer seq_period Time of one measurement cycle seq_led_start Start time of the LED drivers within one cycle seq_led_stop Stop time of the LED drivers within one cycle seq_secled_start Start time of the secondary LED drivers within one cycle (used for SpO2) seq_secled_stop Stop time of the secondary LED drivers within one cycle (used for SpO2) seq_itg_start Start time of the integrator seq_itg_stop Stop time of the integrator seq_sdp1_start Start time of the synchronous demodulator’s 1 positive multiplication seq_sdp1_stop Stop time of the synchronous demodulator’s 1 positive multiplication seq_sdm1_start Start time of the synchronous demodulator’s 1 negative multiplication seq_sdm1_stop Stop time of the synchronous demodulator’s 1 negative multiplication seq_sdp2_start Start time of the synchronous demodulator’s 2 positive multiplication seq_sdp2_stop Stop time of the synchronous demodulator’s 2 positive multiplication seq_sdm2_start Start time of the synchronous demodulator’s 2 negative multiplication seq_sdm2_stop Stop time of the synchronous demodulator’s 2 negative multiplication seq_adc Sampling position of the ADC seq_adc2tia, seq_adc3tia If the TIA channel is selected allow a second (and third) conversion within this cycle. sd_s ubs, sd_subs_always Synchronous demodulator subsampling ratio between sequencer frequency and ADC sampling frequency. ulp Ultra low power bit for the sequencer. If this bit is set and sd_subs>0, it disables the LED pulses and powers off the TIA in all sequences but the one where the TIA is sampled. This bit can be used to optimize the power consumption of the LEDs and the AS7038RB (This bit is located in ADC_CFGB Register bit 1) irq_adc_timing_error The sequencer setup caused a timing error on ADC conversion.

Document Feedback AS7038RB Functional Description Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 47 Figure 41: Block Diagram of Sequencer Sequencer X=2 Synchronous Demodulator control X=1 VD3 Q Q SET CLR S R seq_led_start seq_led_stop led_x_mode x=1...4 Q Q SET CLR S R seq_itg_start seq_itg_stop clk clk Q Q SET CLR S R seq_sdpX_start seq_sdpX_stop clk Q Q SET CLR S R seq_sdmX_start seq_sdmX_stop clk ADC logic sd_subs div seq_div 1µs clkCounter 0...seq_period-1 Run / Stop Logic seq_count cycles seq_start Run/Reset read status register diode_ctrl +1 -1 ADC control GPIO0 pd1 pd2 pd3 pd4 pdi_1 pdi_0 pd_ampcap pd_ampres pd_amp_en ADC Sync. Demodulator 1+2 + BP Filter + Gain Stages TIA -1/0/float/+1 sample reset Clip Det select h/l vth -1/0/float/+1 FiFo Prefilter VD12 seq_adc seq_adc2tia clk seq_adc3tia Q Q SET CLR S R seq_secled_ start seq_secled_ stop clk pregain pregain Photodiode B

Document Feedback AS7038RB Functional Description Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 48

7.1.10 Sequencer Registers

SEQ_CNT Register (Address 0x30) Figure 42: SEQ_CNT Register Addr: 0x30 SEQ_CNT Bit Bit Name Default Access Bit Description 7:0 seq_count 0 RW Number of measurements in one sequence. If seq_count = 0x0 the sequencer is running continuously if started by seq_start=1 or seq_start_sync=1. This register is reset by disabling/enabling of seq_start=0 (but not by osc_off=1) SEQ_DIV Register (Address 0x31) Figure 43: SEQ_DIV Register Addr: 0x31 SEQ_DIV Bit Bit Name Default Access Bit Description 7:0 seq_div 0 RW Divider value Sequencer time increment tclk = ( seq_div + 1 ) * 1 µs The SEQ_DIV register sets the input divider for the main clock. SEQ_START (Address 0x32) Figure 44: SEQ_START Register Addr: 0x32 SEQ_START Bit Bit Name Default Access Bit Description 7:3 Not used 0 R_PUSH Not used

Document Feedback AS7038RB Functional Description Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 49 Addr: 0x32 SEQ_START Bit Bit Name Default Access Bit Description 2 seq_start_gpio 0 R_PUSH After programming, the sequencer waits for a synchronization pulse via GPIO (see register GPIO_SYNC). For all released ADC channels a value is recorded per synchronization pulse (see register ADC_CHANNEL). 1 seq_start_sync 0 R_PUSH Similar to seq_start, but the sequencer will wait for overflow of the frequency divider that feeds all the switched-cap filters. This means 1) That it could take anything between 0 and 8 ms before the sequencer actually starts. 2) That the generated frequencies are in phase with the sequencer. For this to have any effect, the sequencer period should be selected with the selected frequencies (sd_bw, hp_freq) in mind. 0 seq_start 0 R_PUSH Writing 1 starts the sequencer(s) in the according to the configuration and upon rising edge of seq_start ADC selects first channel. Writing 0 stops the sequencer(s). In manual mode, writing 1 starts one ADC conversion but does not initialize the ADC channel selection. Reading returns 1 if the sequencer is running (sequencer mode), respectively if the ADC is converting (manual mode) With the SEQ_START register sets the configured sequencer can be started SEQ_PER (Address 0x33) Figure 45: SEQ_PER Register Addr: 0x33 SEQ_PER Bit Bit Name Default Access Bit Description 7:0 seq_period 0 RW t_period Sequencer period T = t_period * (seq_div+1) * 1 µs The SEQ_PER register sets one measurement cycle of the sequencer.

Document Feedback AS7038RB Functional Description Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 58 SUBS_COUNTER (Address 0x62) Figure 68: SUBS_COUNTER Register Addr: 0x62 SUBS_COUNTER Bit Bit Name Default Access Bit Description 7:0 subs_counter 0 RO Current subsampling counter value OVERSAMPLING/AVERAGE Noise improvement. Generate the programmable average of multiple sample for two input channels (e.g., PPG and ECG). The mean value is programmed as a 2^n function. SEQ_OVS_SEL (Address 0x48) Figure 69: SEQ_OVS_SEL Register Addr: 0x48 SEQ_OVS_SEL Bit Bit Name Default Access Bit Description 7:4 ovs_sel2 0 RW Selecting the ADC channel for oversampling 2 3:0 ovs_sel1 0 RW Selecting the ADC channel for oversampling 1 SEQ_OVS_VAL (Address 0x49) Figure 70: SEQ_OVS_VAL Register Addr: 0x49 SEQ_OVS_VAL Bit Bit Name Default Access Bit Description

7 Not used 0 RW Not used

6:4 ovs_val2 0 RW Set value for oversampling 2, 2^ovs_val2

3 Not used 0 RW Not used

2:0 ovs_val1 0 RW Set value for oversampling 1, 2^ovs_val1

Document Feedback AS7038RB Functional Description Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 60

7.1.11 Optical Signal Conditioning

Figure 74: Optical Signal Conditioning Synchronous Demodulator Two optional synchronous demodulators can be used to detect small optical signals in the presence of large unwanted noise (ambient light). Since the detector synchronizes to the LED frequency, the demodulator can only be used of the measurement sequencer is running. It includes input filer (adjustable high pass and low pass, notch filter) and 2nd order adjustable output low pass. The demodulator itself multiplies the signal by +1 / 0 / -1 with a timing which is controlled by the sequencer. Information The optical signal conditioning stage need sigref_en=1 for operation. ADC ofe1/2_sd_byp Synchronous Demodulator1,2 + BP Filter + Gain Stages From TIA ofe1/2_hp_byp ofe1/2_sd_bw aa_freq 12.5-200Hz ofe1/2_en ofe1/2_hp_freq ofe1/2_hp_en ofe1/2 _gain_g Clip Det Clip Det gain_sd h/l vth FiFo Prefilter pregain ofe1 ofe2 sd1 sd2 tia ofe_notch _sel60 ecg_notch_byp

Document Feedback AS7038RB Functional Description Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 61 High Pass Filter Two optional high pass filter can be used to remove unwanted DC-components from the signal and allows further amplification. In order to guarantee fast settling times of the filter, four cutoff frequencies can be chosen. Gain Stage Two optional gain stage can be used to amplify the signal after the DC-component has been removed. Figure 75: Optical Signal Conditioning Signal Path (25 Hz LED sampling rate example) The LED that is periodically turned ON and OFF, samples the cardio-vascular pulse wave. The photodiode measures the reflected light that is modulated by the LED sampling frequency (25Hz in the examples Figure 75). Unwanted ambient light or glass reflected LED light is not modulated. The signal can be sent to the Pre-filter Block where an anti-aliasing filter removes the high frequency noise, followed by a high pass filter that removes the low frequency noise and unwanted dc light. After the Synchronous demodulator demodulates the signal it is filtered and amplified.

Document Feedback AS7038RB Functional Description Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 62

7.1.12 Optical Signal Conditioning Registers

OFE_CFGA (Address 0x50) Figure 76: OFE_CFGA Register Addr: 0x50 OFE_CFGA Bit Bit Name Default Access Bit Description 7 ofe2_en 0 RW Enable OFE2 6 ofe1_en 0 RW Enable OFE1 5 en_bias_ofe 0 RW Enable bias for OFE and TIA 4:3 aa_freq 0 RW Anti-aliasing filter cut-off frequency Settings Signal 0 10 kHz 1 20 kHz 2 40 kHz 3 60 kHz 2:0 gain_sd 0 RW SD gain Settings Normal Gain 0 1 1 2 2 4 3 8 4 16 5 32 6 64

7 Reserved

Document Feedback AS7038RB Functional Description Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 63 OFE1_SD_THCFG (Address 0x51) Figure 77: OFE1_SD_THCFG Register Addr: 0x51 OFE1_SD_THCFG Bit Bit Name Default Access Bit Description 7:4 ofe1_sd_clipd_h_thresh 0 RW If the voltage on the output of the gain_sd stage of OFE1 (input of synchronous demodulator) exceed this threshold the irq_clipdetect interrupt is asserted. The threshold is defined as: 0: 1824 mV 1: 1748 mV 2: 1672 mV 3: 1596 mV 4: 1520 mV 5: 1444 mV 6: 1368 mV 7: 1292 mV 8: 1216 mV 9: 1140 mV 10: 1064 mV 11: 988 mV 12: 912 mV 13: 836 mV 14: 760 mV 15: 684 mV 3:0 ofe1_sd_clipd_l_thresh 0 RW If the voltage on the output of the gain_sd stage OFE 1 (input of synchronous demodulator) falls below this threshold the irq_clipdetect interrupt is asserted. The threshold is defined as: 0: 67 mV 1: 143 mV 2: 219 mV 3: 295 mV 4: 371 mV 5: 447 mV 6: 523 mV 7: 599 mV 8: 675 mV 9: 751 mV 10: 827 mV

Document Feedback AS7038RB Functional Description Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 64 Addr: 0x51 OFE1_SD_THCFG Bit Bit Name Default Access Bit Description 11: 903 mV 12: 979 mV 13: 1055 mV 14: 1131 mV 15: 1207 mV OFE_CFGC (Address 0x52) Figure 78: OFE_CFGC Register Addr: 0x52 OFE_CFGC Bit Bit Name Default Access Bit Description 6 prefilter_aa_byp 0 RW 0: Anti-aliasing filter (aa_filter) is used 1: Bypass anti-aliasing filter 5 prefilter_hp_byp 0 RW 0: Use 200 Hz high pass filter 1: Bypass 200 Hz high pass filter 4 prefilter_gain_byp 0 RW 0: Use gain_sd stage 1: Bypass gain_sd stage 3 prefilter_bypass_en 0 RW 0: Use prefilter unless any of the above register is set 1: Bypass complete prefilter 2 prefilter_aa_en 0 RW 0: Anti-aliasing filter (aa_filter) is OFF 1: Anti-aliasing filter is ON 1 prefilter_hp_en 0 RW 0: 200 Hz high pass filter is OFF 1: 200 Hz high pass filter is ON 0 prefilter_gain_en 0 RW 0: gain_sd stage is OFF 1: gain_sd stage is ON

Document Feedback AS7038RB Functional Description Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 65 OFE_CFGD (Address 0x53) Figure 79: OFE_CFGD Register Addr: 0x53 OFE_CFGD Bit Bit Name Default Access Bit Description 6:5 notch_bw 3 RW Bandwidth of notch filter. Settings Value

0 Max BW

3 Min BW (default)

4:2 ofe_sd_hp 0 RW High pass filter pulse rate for both synchronous demodulators. Pulse width = 1 µs Settings Pulse Frequency Cutoff Frequency 0 125 kHz 200 Hz 1 62.5 kHz 100 Hz 2 31.25 kHz 50 Hz 3 15.625 kHz 25 Hz 4 7.8125 kHz 12.5 Hz 1:0 ofe_gs_aa 0 RW OFE anti-aliasing Setting Nominal Gain

0 Bypass

1 fc=100 kHz 2 fc=10 kHz 3 fc=826 Hz

Document Feedback AS7038RB Functional Description Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 67 Addr: 0x55 OFE1_CFGB Bit Bit Name Default Access Bit Description 4 16 5 32 6 64 7 128 4:2 ofe1_sd_bw 0 RW Low pass clock for synchronous demodulator 1 and cutoff frequency Settings Cutoff Frequency 0 10 Hz 1 20 Hz 2 40 Hz 3 80 Hz 4 5 Hz 5 2.5 Hz 1:0 of1e_hp_freq 0 RW High pass filter pulse rate for synchronous demodulator 1. Pulse width = 1 µs Settings Cutoff Frequency 0 0.33 Hz 1 1.32 Hz 2 5.28 Hz 3 10.56 Hz OFE2_SD_THCFG (Address 0x57) Figure 82: OFE2_SD_THCFG Register Addr: 0x57 OFE2_SD_THCFG Bit Bit Name Default Access Bit Description 7:4 ofe2_sd_clipd_h_thresh 0 RW If the voltage on the output of the gain_sd stage of OFE2 (input of synchronous demodulator) exceed this threshold the irq_clipdetect interrupt is asserted. The threshold is defined as: 0: 1824 mV 1: 1748 mV

Document Feedback AS7038RB Functional Description Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 68 Addr: 0x57 OFE2_SD_THCFG Bit Bit Name Default Access Bit Description 2: 1672 mV 3: 1596 mV 4: 1520 mV 5: 1444 mV 6: 1368 mV 7: 1292 mV 8: 1216 mV 9: 1140 mV 10: 1064 mV 11: 988 mV 12: 912 mV 13: 836 mV 14: 760 mV 15: 684 mV 3:0 ofe1_sd_clipd_l_thresh 0 RW If the voltage on the output of the gain_sd stage OFE 2 (input of synchronous demodulator) falls below this threshold the irq_clipdetect interrupt is asserted. The threshold is defined as: 0: 67 mV 1: 143 mV 2: 219 mV 3: 295 mV 4: 371 mV 5: 447 mV 6: 523 mV 7: 599 mV 8: 675 mV 9: 751 mV 10: 827 mV 11: 903 mV 12: 979 mV 13: 1055 mV 14: 1131 mV 15: 1207 mV

Document Feedback AS7038RB Functional Description Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 70 Addr: 0x59 OFE2_CFGB Bit Bit Name Default Access Bit Description 4 16 5 32 6 64 7 128 4:2 ofe2_sd_bw 0 RW Low pass clock for synchronous demodulator 2 and cutoff frequency Settings Cutoff Frequency 0 10 Hz 1 20 Hz 2 40 Hz 3 80 Hz 4 5 Hz 5 2.5 Hz 1:0 of2e_hp_freq 0 RW High pass filter pulse rate for synchronous demodulator 2. Pulse width = 1 µs Settings Cutoff Frequency 0 0.33 Hz 1 1.32 Hz 2 5.28 Hz 3 10.56 Hz OFE_NOTCH (Address 0x5a) Figure 85: OFE_NOTCH Register Addr: 0x5a OFE_NOTCH Bit Bit Name Default Access Bit Description 6 ofe2_notch_sel60 0 RW 0: Fc=50 Hz 1: Fc=60 Hz 5 ofe2_notch_byp 1 RW 0: OFE2 Notch filter Not bypassed 1: OFE2 Notch bypassed 4 ofe2_notch_en 0 RW 0: Power down of the OFE2 high pass filter 1: Enable OFE2 Notch filter

Document Feedback AS7038RB Functional Description Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 71 Addr: 0x5a OFE_NOTCH Bit Bit Name Default Access Bit Description 2 ofe1_notch_sel60 0 RW 0: Fc= 50 Hz 1: Fc= 60 Hz 1 ofe1_notch_byp 1 RW 0: OFE1 Notch filter Not bypassed 1: OFE1 Notch bypassed 0 ofe1_notch_en 0 RW 1. 0: Power down of the OFE1 high pass filter 1: Enable OFE1 Notch filter

7.1.13 Light-to-Frequency Mode

The LTF (light-to-frequency, or FM, frequency mode) mode. Figure 86: Light-to-Frequency Mode Internal Circuit (1) Do not use diodes which are connected to the TIA (register pd_a, pd_b, pd1...4) at the same time when Itf_en is enabled on the same diode. LTF 1 LTF 0 Counter I -> f conversion A B Timer & Capture itime ltf_data0 16 bits ltf_data1 16 bits ltf_enable ltf0_sel, lft1_sel ltf_gain

Document Feedback AS7038RB Functional Description Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 74 LTF_CONFIG (Address 0x25) Figure 92: LTF_CONFIG Register Addr: 0x25 LTF_CONFIG Bit Bit Name Default Access Bit Description 7 infinite_itime 0 RW If this is asserted, then integration does not stop. The ITIME setting is ignored. Use with watch the ltfdata counters. (Warning: must be filtered in software to prevent inconsistent upper/lower byte). It's implemented as a count disable on the integration counter, so when resetting bit to 0 again, the itime counter will continue and results can be read afterwards through the regular mechanisms (ltfdata or FIFO) This is intended for very long integration times - as the timing is controlled by software/I²C, accuracy fully depends on the system and I²C master. 6 az_disable_auto 0 RW 0: Run autozero on both channels every time FM mode is activated for the first time after ENAB is being asserted. 1: Do not run autozero automatically. Autozero can only be activated manually (AZ_CONTROL) 5:4 az_mode 0 RW Autozero mechanism. It is a simple and robust follower circuit that requires as many cycles as offsetvalue minus startvalue. Mode 0 is the safe default mode. Mode 1 is used in production test to be sure that the DAC can generate all values. Mode 2 can be used if AZ time is an issue, if one is certain that the AZvalue has not changed much: typically if full AZ has been run, one can assume that offset only changes a little bit from temperature. Settings Mode Always start at zero when searching the best offset value,128+16 cycles Always start at the previous offset with the auto-zero mechanism, 256+16 cycles Always start at the previous offset with the auto-zero mechanism, 16+16 cycles

3 Not used

2 ltf_prox_mode 0 RW LTF proximity mode

Document Feedback AS7038RB Functional Description Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 75 Addr: 0x25 LTF_CONFIG Bit Bit Name Default Access Bit Description 1 ltf_fifo_mode 0 RW Run LTF integrations back to back, the LTF modulator is running continuously (the modulators are not reset between integrations cycles). After each integration, the result gets written to the FIFO. The FIFO is being filled automatically, FIFO threshold interrupt is flagged as configured. The first item read from the FIFO is from channel 0, the next one from channel 1, etc. Note that there is no ltf_done interrupt triggered after each integration. A FIFO threshold of 1 can be used to generate an interrupt for each result. irq_ltf_enab should be kept asserted to avoid missing an ltf_sat interrupt. Do not enable ADC/sequencer FIFO mode and ltf_fifo_mode at the same time, corrupted data would be the result. Make sure to empty the FIFO in time, if the FIFO is full, new data is not being stored in the FIFO. Source of data read from the FIFO after an overflow condition is undefined (can be from channel 0 or channel 1) Stop the procedure by clearing this bit. 0 ltf_enable 0 RW This bit must be asserted for any LTF function (powers up the LTF clock tree) LTF_SEL (Address 0x26) Figure 93: LTF_SEL Register Addr: 0x26 LTF_SEL Bit Bit Name Default Access Bit Description

7 Do not use 0 RW Do not use

6:4 ltf1_sel 2 RW Select the sensor diode for LTF1 Setting Source

0 Clear

1 Not used

Document Feedback AS7038RB Functional Description Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 76 Addr: 0x26 LTF_SEL Bit Bit Name Default Access Bit Description

4 PD1

5 PD2

6 PD3

7 PD4

2:0 ltf0_sel 0 RW Select the sensor diode for LTF0 Setting Source

1 Clear

Document Feedback AS7038RB Functional Description Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 80 LTF_THRESHOLD_ HIGH0 (Address 0x6e) Figure 101: LTF_THRESHOLD_ HIGH0 Register Addr: 0x6e LTF_THRESHOLD_ HIGH0 Bit Bit Name Default Access Bit Description 7:0 ltf_threshold_high[7:0] FF RW If LTF returns a value below ltf_threshold_high (not equal), then the ltf_threshold_high interrupt can be triggered. LTF_THRESHOLD_ HIGH1 (Address 0x6f) Figure 102: LTF_THRESHOLD_ HIGH1 Register Addr: 0x6f LTF_THRESHOLD_ HIGH1 Bit Bit Name Default Access Bit Description 7:0 ltf_threshold_high[15:8] FF RW If LTF returns a value below ltf_threshold_high (not equal), then the ltf_threshold_high interrupt can be triggered.

7.1.14 Electrical Analog Front End

The electrical analog front end consists of three identical signal paths with independent settings of bias condition, gain and offset. Four general purpose pins and ECG_REF can be used either as configurable GPIO pin or as analog input pins for the electrical analog front end. The analog inputs can be configured to setup different amplifier topologies.

Document Feedback AS7038RB Functional Description Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 81 Figure 103: AFE Schematic GPIO0 GPIO1 GPIO2 GPIO3 ECG_REF gpio_dac gpio_r_bias 160k gpio_gst_in measure_dac T-gates: 50k T-gates: 50k T-gates: 10k gst_gain 0 1x 1 2x 2 4x 3 8x 4 16x 5 32x 6 64x 7 don t use 0AGND gst_ref SIGREF don t use 128k Note: Resistor / T-gates resistance values are given as indication - don t rely on absolute values on ADC Vref=1.6V AGND dac1_value sigref_on_dac_buf SIGREF afe_enab_dac_buf 1.9V DACdac2_value afe_enab_dac afe_enab_gainstage

Document Feedback AS7038RB Functional Description Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 82 DAC Switching Figure 104: Electrical Analog Front End DAC Level Switching If bit dac_mode is not zero, the DAC switches its codes between dac1_value and dac2_value on the beginning of every/every 2nd/every 4th sequencer cycle where the ADC is converting the electrical frontend channel. ADC conversions of any other channel do not switch the DAC. Input Pins Four general purpose pins and ECG_REF can be used either as configurable GPIO pin or as analog input pins for the electrical analog front end. The analog inputs can be configured to setup different amplifier topologies.

7.1.15 EAF (Electrical Analog Frontend) Registers

EAF_CFG (Address 0x70) Figure 105: EAF_CFG Register Addr: 0x70 EAF_CFG Bit Bit Name Default Access Bit Description 7:4 Do not use 0 RW Do not use 3 eaf_enab 0 RW 0: EAF bias deactivated 1: EAF bias activated (need to be set for any functions of the EAF are used). 2 eaf_enab_dac 0 RW 0: DAC inside the EAF OFF Example with dac_mode=1 VDAC sequencer start period ADC convert start ADC convert start ADC convert seq_adc seq_adc seq_adc dac1_value dac2_value dac1_value t [not to scale]

Document Feedback AS7038RB Functional Description Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 83 Addr: 0x70 EAF_CFG Bit Bit Name Default Access Bit Description 1: DAC inside the EAF ON 1 eaf_enab_dac_buf 0 RW 0: DAC buffer OFF 1: DAC buffer ON 0 eaf_enab_gainstage 0 RW 0: Gain stage in EAF OFF 1: Gain stage in EAF ON The EAF_CFG register is used to configure the analog frontend. EAF_GST (Address 0x80) Figure 106: EAF_GST Register Addr: 0x80 EAF_GST Bit Bit Name Default Access Bit Description 7:5 gpio_gst_in 0 RW Gain stage input selection Setting Meaning

0 Not connected

1 GPIO0

2 GPIO1

3 GPIO2

4 GPIO3

5 ECG_REF

4:3 gst_ref 0 RW Gain stage reference voltage Setting Meaning

0 AGND

1 DAC buffer

2 SIGREF

3 Reserved

2:0 gst_gain 0 RW Gain stage gain Setting Meaning 0 1 1 2 2 4

Document Feedback AS7038RB Functional Description Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 84 Addr: 0x80 EAF_GST Bit Bit Name Default Access Bit Description 3 8 4 16 5 32 6 64 The EAF register is used to configure the electrical frontend EAF_BIAS (Address 0x81) Figure 107: EAF_BIAS Register Addr: 0x81 EAF_BIAS Bit Bit Name Default Access Bit Description 7:5 gpio_r_bias 0 RW Resistive biasing Setting Meaning

0 No resistive biasing

1 Resistive biasing on GPIO0

2 Resistive biasing on GPIO1

3 Resistive biasing on GPIO2

4 Resistive biasing on GPIO3

5 Resistive biasing on ECG_REF

4:0 Not used 0 RW Do not use EAF_DAC (Address 0x82) Figure 108: EAF_DAC Register Addr: 0x82 EAF_DAC Bit Bit Name Default Access Bit Description 7:5 Do not use 0 RW Do not use 4 sigref_on_dac_buf 0 RW If asserted, connect SIGREF to DAC buffer.

Document Feedback AS7038RB Functional Description Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 85 Addr: 0x82 EAF_DAC Bit Bit Name Default Access Bit Description 3 measure_dac 0 RW If this bit is asserted, the DAC output is connected to the gain stage input (independent of gpio_gst_in selection, therefore the DAC output is measurable on the GPIO pin) 2:0 gpio_dac 0 RW DAC on GPIO Setting Meaning

0 No DAC biasing

1 DAC on GPIO0

2 DAC on GPIO1

3 DAC on GPIO2

4 DAC on GPIO3

5 DAC on ECG_REF

EAF_DAC1_L (Address 0x83) Figure 109: EAF_DAC1_L Register Addr: 0x83 EAF_DAC1_L Bit Bit Name Default Access Bit Description 7:6 dac1_value[1:0] 0 RW DAC value 1 (2LSB) 5:0 Not used 0 RW Not used The EAF_DAC1/2_L/H registers is used to configure the dac value. See bit dac_mode for selection of dac register 1 or 2 EAF_DAC1_H (Address 0x84) Figure 110: EAF_DAC1_H Register Addr: 0x84 EAF_DAC1_H Bit Bit Name Default Access Bit Description 7:0 dac1_value[9:2] 0 RW DAC value 1 (upper 8 bits) 10-bit value:

Document Feedback AS7038RB Functional Description Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 87 Addr: 0x87 EAF_DAC_CFG Bit Bit Name Default Access Bit Description 1:0 dac_mode 0 RW DAC mode The EAF has a DAC that can be switched out on GPIOs. dac_mode 0 uses statically dac1_value, the other modes switch dynamically between the two values. The system switches from one value to the next always at the beginning of a sequence in which the ADC will sample the AFE channel. Setting Meaning Possible Configurations of Every Amplifier Stage Figure 114: Non Inverting Amplifier with Offset and Input Voltage Divider (Temperature Sensor) DAC Gain

Document Feedback AS7038RB Functional Description Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 89 Figure 118: Non Inverting Amplifier with DC -Blocking, Referenced to V_ADCRef/2 Figure 119: Non Inverting Amplifier with DC -Blocking and Fast Settling Time, Referenced to ADCRef /2

7.1.16 ECG Amplifier

The ECG (electro cardiogram) amplifier is a high impedance, low noise instrumentation amplifier with analog circuitry to band pass filter the signal. Gain is distributed between 3 gain stages. The gain in the first stage determines the tradeoff between achievable noise level and achievable input offset voltage. An optional 50/60 Hz notch filter can be enabled to attenuate unwanted noise from mains coupling. DAC Gain DAC Gain

Document Feedback AS7038RB Functional Description Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 90 Figure 120: ECG Amplifier Circuitry ECG_INP ECG_INN ECG_REF to electrical frontend Leads off detect ecg_ref_en 1µF ECG Electrodes 2x10M SIGREF SIGREF ecg_low_leakage_en for diode leakage reduction on ECG_INP and ECG_INN 1 G=1..128 SIGREF ADC 800Hz G_ina=18 (programmable 1 .. 48) Gain StageStage 1 Differential AmplifierStage 2High Pass Filter Filter Gain 1 .. 4 1 .. 12 G2G1 0.33Hz

50 Hz 40-200 Hz

Document Feedback AS7038RB Functional Description Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 91 ECG Lead OFF Detection Figure 121: ECG Lead-OFF Detection The ECG lead OFF detection can be used for detection if the user actually touches the leads. It is a circuitry to measure the capacitor and/or resistance between the two lead inputs ECG_INP and ECG_INN. ECG_INP ECG_INN ECG_REF ECG Electrodes 2x10M GND ecg_leadsdet_curr 20nA/100nA/500nA/1µA to ADC channel ecgi ecg_leadsdet_en ecg_leadsdet_en ecg_leadsdet_sync_adc If ecg_leaddet_sync_adc is set, the leads detect current is reversed by toggling ecg_leadset_pol on every start of a sequencer period, where an ADC conversion of ECG_INP is performed. This concept allows the measurement of the connected resistor and capacitor between the electrodes. on ecg_leadsdet_pol updates ecg_leadsdet_sync_adc=1 IECG_INP VECG_INP sequencer start period ADC convert start ADC convert start ADC convert seq_adc seq_adc seq_adc ecg_low_leakage_en

Document Feedback AS7038RB Functional Description Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 92

7.1.17 ECG Registers

ECG_MODE (Address 0x5b) Figure 122: ECG_MODE Register Addr: 0x5b ECG_MODE Bit Bit Name Default Access Bit Description 7 ecg_notch_sel60 0 RW 0: Fc=50 Hz 1: Fc=60 Hz 6:4 ecg_hp_mode 0 RW 0: Differential A-B 3:2 ecg_gain_g2 2 RW Gain INA2 Setting Gain Factor 0 1 1 4 2 6 3 12 1:0 ecg_gain_g1 2 RW Gain INA1 Setting Gain Factor 0 1 1 2 2 3 3 4 ECG_CFGA (Address 0x5c) Figure 123: ECG_CFGA Register Addr: 0x5c ECG_CFGA Bit Bit Name Default Access Bit Description 7 ecg_en 0 RW Enable ECG instrumentation amplifier 6 ecg_clk_off 0 RW 0: All ECG clocks enable 1: All ECG clocks disable 5 ecg_gain_byp 0 RW 0: Gain stage is used

Document Feedback AS7038RB Functional Description Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 93 Addr: 0x5c ECG_CFGA Bit Bit Name Default Access Bit Description 1: Gain stage is ECGREF 4 ecg_lp_byp 0 RW 0: LP stage is used 1: LP stage is bypassed 3 ecg_notch_byp 1 RW 0: Notch stage is used 1: Notch stage is bypassed 2 ecg_diff_byp 0 RW 0: Diffamp stage is used 1: Diffamp stage is bypassed 1:0 ecg_hp_byp 0 RW 00: HP filter is used 01: Not used 10: Not used 11: HP filter is bypassed ECG_CFGB (Address 0x5d) Figure 124: ECG_CFGB Register Addr: 0x5d ECG_CFGB Bit Bit Name Default Access Bit Description 7 ecg_fast_startup 0 RW ECG fast startup 6:5 ecg_lp_freq 0 RW ECG low pass cut of Frequency Setting Pulse Frequency Cutoff Frequency 0 31.25 kHz 40 Hz 1 62.5 kHz 80 Hz 2 125 kHz 160 Hz 3 250 kHz 320 Hz 4:3 ecg_hp_freq 0 RW ECG High pass filter cutoff frequency Setting Filter Frequency Cutoff Frequency 0 122 Hz 0.33 Hz 1 488 Hz 1.32 Hz 2 1935 Hz 5.28 Hz 3 3906 Hz 10.56 Hz

Document Feedback AS7038RB Functional Description Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 95 Addr: 0x5f ECG_CFGD Bit Bit Name Default Access Bit Description 4 ecg_leadsdet_sync_adc 0 RW ECG Leads Detection Automatic Update. If this is asserted, then ecg_leadsdet_pol is inverted automatically at the start of a sequence (at count=2) if in this sequence the ADC will convert the ECGi channel. 3 ecg_leadsdet_pol 0 RW ECG Leads Detection Polarity. Can be written to manually if ecg_leadsdet_sync_adc is clear, otherwise it is automatically toggled. 2:1 ecg_leadsdet_curr 0 RW ECG Leads Detection Current Setting Current 0 20 nA 1 100 nA 2 500 nA 3 1 µA 0 ecg_leadsdet_en 0 RW ECG Leads Detection Enable ECG_THRESHOLD_LOW (Address 0x6a) Figure 127: ECG_THRESHOLD_LOW Register Addr: 0x6a ECG_THRESHOLD_LOW Bit Bit Name Default Access Bit Description 7:0 ecg_threshold_low 0 RW If the ADC returns an ECG value below agc_threshold_low (not equal) at ecg_leadsdet_pol=0, then the lead_off interrupt can be triggered.

Document Feedback AS7038RB Functional Description Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 96 ECG_THRESHOLD_HIGH (Address 0x6b) Figure 128: ECG_THRESHOLD_HIGH Register Addr: 0x6b ECG_THRESHOLD_HIGH Bit Bit Name Default Access Bit Description 7:0 ecg_threshold_high FF RW If the ADC returns an ECG value above agc_threshold_high (not equal) at ecg_leadsdet_pol=1, then the lead_off interrupt can be triggered

7.1.18 ADC and FIFO

The ADC is a 14-bit successive-approximation register (SAR) type. It supports 14-bit with conversion time up to 50 ksps. The ADC is started by the sequencer and its timing or in manual mode (man_m ode=1) by setting seq_start=1 (seq_start stays ‘1’ as long as the conversion runs). The AS7038RB can be configured to trigger an interrupt upon end of conversion.

Document Feedback AS7038RB Functional Description Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 97 Figure 129: ADC Internal Circuit and Multiplexer For best accuracy, the ADC can be optionally calibrated. Information If GPIO2 or GPIO3 is used as ADC input, there is no anti-aliasing filter in front of the ADC (needs to be added externally).

7.1.19 ADC Threshold

At the output of the ADC converter a digital threshold can be enabled. If the output of the ADC exceeds the threshold adc_threshold, it triggers an interrupt. This mechanism can be used to identify if an object is in proximity of the sensor and then to interrupt the host. In cases where no object is detected, the host can be sleeping therefore reducing power consumption of the system. ADC Vref=1.6V AGND V_LDO Electrical Frontend TIA GPIOs vtemp adc_channel_mask_temp ADC_DATAH/L FiFo 64x16 bit entries OFE adc_channel_mask_tia adc_channel_mask_ofe1/ sd1/ofe2/sd2 adc_channel_mask_afe adc_channel_mask_ecgo adc_channel_mask_ecgifrom ECG Start from top and cycle through channels where adc_channel_mask_...=1 (first channel selected seq_start 0->1) ECG_ REF Pre- Filter adc_channel_mask_pregain adc_channel_mask_gpio3 adc_channel_mask_gpio2 GPIO3 GPIO2

Document Feedback AS7038RB Functional Description Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 98

7.1.20 ADC Registers

ADC_THRESHOLD (Address 0x68) Figure 130: ADC_THRESHOLD Register Addr: 0x68 ADC_THRESHOLD Bit Bit Name Default Access Bit Description 7:0 adc_threshold 0xff RW If the ADC returns a value above adc_threshold (not equal), then the adc_threshold interrupt can be triggered. Note that when only the upper 8 bits are compared, the lower 6 bits are ignored. A value of 0xff can therefore never trigger the interrupt ADC_THRESHOLD_CFG (Address 0x69) Figure 131: ADC_THRESHOLD_CFG Register Addr: 0x69 ADC_THRESHOLD_CFG Bit Bit Name Default Access Bit Description 7:2 Not used 0 RW Not used 1 adc_thresh_differential 0 RW If adc_thresh_tia only is asserted and any of seq_adc[23]tia is non-zero, meaning that there are two or three ADC TIA measurements in one sequencer period, then the second is subtracted from the first, and the difference is being compared to the adc_threshold. 0 adc_thresh_tiaonly 0 RW Normally, the adc_threshold works regardless of the adc channel. If this bit is set, then the threshold is only checked if the adc channel is TIA

Document Feedback AS7038RB Functional Description Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 99 ADC_CFGA (Address 0x88) Figure 132: ADC_CFGA Register Addr: 0x88 ADC_CFGA Bit Bit Name Default Access Bit Description 7:4 Not used 0 RW Not used 3:1 adc_multi_n

0 RW Defines number of samples that are taken in

multimode (adc_multimode =1) Setting Number of Samples per ADC Conversion Command 0 2 1 4 2 8 3 16 4 32 5 48 6 64 7 96 0 adc_multimode 0 RW 0: If ADC is started one sample is measured 1: If ADC is started multiple samples are stored in sequence in the FIFO. The number of samples is defined with "adc_multi_n". Information If the ADC is triggered with the sequencer, the very first ADC conversion after seq_en=1 stores the number of samples according to above table. All subsequent samples use one sample less (e.g. 7 instead of 8).

Document Feedback AS7038RB Functional Description Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 101 Addr: 0x8a ADC_CFGC Bit Bit Name Default Access Bit Description 4 adc_selfpd 0 RW 1: Power down the ADC when not converting; use this to conserve power, but set adc_settling_time to minimum 64 μs to permit settling of the ADC reference buffer. 0: Always enable ADC 3 adc_discharge 0 RW 0: Suppress ADC capacitor discharging – use with caution 1: Discharge ADC capacitor before tracking If asserted, the capacitor is discharged before the tracking phase. If zero, the discharge phase is suppressed and the tracking phase is started one cycle earlier 2:0 adc_settling_time 0 RW ADC settling time: Use with synchronous demodulator. It defines the number of ADC clock cycles the sampling window is kept open additionally. If the gain stage in the optical frontend is used (gain_byp=0), set this to minimum 8 µs. If adc_selfpd=1, set this to minimum 64 µs. Setting Periods µs (@500 kHz) µs (@250 kHz) 0 0 0 0 1 4 8 16 2 8 16 32 3 16 32 64 4 32 64 128 5 64 128 256 6 128 256 512 7 256 512 1 ms ADC_CHANNEL_MASK_L (Address 0x8b) Figure 135: ADC_CHANNEL_MASK_L Register Addr: 0x8b ADC_CHANNEL_MASK_L Bit Bit Name Default Access Bit Description 7 adc_channel_mask_pregain 0 RW Pregain channel selection 6 adc_channel_mask_afe 0 RW Electrical front end

Document Feedback AS7038RB Functional Description Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 102 Addr: 0x8b ADC_CHANNEL_MASK_L Bit Bit Name Default Access Bit Description 5 adc_channel_mask_temp 0 RW Temperature measurement 4 adc_channel_mask_sd2 0 RW Synchronous modulator 2 output just before the gain stage 3 adc_channel_mask_ofe2 0 RW Synchronous modulator 2 output after the gain stage 2 adc_channel_mask_sd1 0 RW Synchronous modulator 1 output just before the gain stage 1 adc_channel_mask_ofe1 0 RW Synchronous modulator 1 output after the gain stage 0 adc_channel_mask_tia 0 RW Trans-Impedance amplifier output The adc channel is chosen automatically from the bits within the adc_channel_mask_* set. It starts from right and finishes left (LSB->MSB) and wraps back from the most significant asserted bit to the least significant of the asserted bits. After every ADC conversion it switches to the next enabled channel, (except around the adc2tia/adc3tia cases). See register description FIFOH and FIFOL for encoding of the first channel in the data stream. This applies to both, manual mode and sequencer mode. In sequencer mode, it starts with the smallest channel when the sequencer is being started. In manual mode, the adc_sel is reset with every write to either ADC_CHANNEL_MASK_L or ADC_CHANNEL_MASK_H. ADC_CHANNEL_MASK_H (Address 0x8c) Figure 136: ADC_CHANNEL_MASK_H Register Addr: 0x8c ADC_CHANNEL_MASK_H Bit Bit Name Default Access Bit Description 7:4 Not used 0 RW Not used 3 adc_channel_mask_gpio2 0 RW GPIO2 input – set gpio2_a=1 and Write 0x47 to register 0xC6 Write 0x0C to register 0xC2 Write 0x0C to register 0xC3 2 adc_channel_mask_gpio3 0 RW GPIO3 input – set gpio3_a=1 and Write 0x47 to register 0xC6 Write 0x0C to register 0xC2 Write 0x0C to register 0xC3 1 adc_channel_mask_ecgi 0 RW ECG amplifier input – use for leads off detection

Document Feedback AS7038RB Functional Description Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 104

7.1.21 FIFO Register

FIFO_CFG (Address 0x78) Figure 139: FIFO_CFG Register Addr: 0x78 FIFO_CFG Bit Bit Name Default Access Bit Description 6:0 fifo_threshold 0 RW FIFO threshold. The fifo_threshold interrupt is flagged if there are more than this many entries in the FIFO. 0: Interrupt with 1 (16-bit) entry in FIFO 127: Interrupt when FIFO is full but one FIFO_CNTRL (Address 0x79) Figure 140: FIFO_CNTRL Register Addr: 0x79 FIFO_CNTRL Bit Bit Name Default Access Bit Description 7:1 Not used 0 RW Not used 0 fifo_clear 0 PUSH1 Write a 1 here to clear the FIFO. Can be useful when switching from one sequencer mode to another to make sure that there are no old FIFO entries left

Document Feedback AS7038RB Functional Description Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 105 FIFOSTATUS (Address 0xa4) Figure 141: FIFOSTATUS Register Addr: 0xa4 FIFOSTATUS Bit Bit Name Default Access Bit Description 7:1 Not used 0 RO Not used

0 Fifo overflow 0 RO FIFO overflow indicator

FIFOLEVEL (Address 0xa6) Figure 142: FIFOLEVEL Register Addr: 0xa6 FIFOLEVEL Bit Bit Name Default Access Bit Description 7:0 FifoLevel 0 RO FIFO fill level (0..128) FIFOL (Address 0xfe) Figure 143: FIFOL Register Addr: 0xfe FIFOL Bit Bit Name Default Access Bit Description 7:0 fifol 0 PUSHPOP Low byte of FIFO FIFOL can be read out with single reads (2 consecutive I²C addresses have to be read to get one FIFO entry) or with block-read (up to 2 x fifo_depth values can be read in a single block-read) Upon reading of FIFOH, it automatically advances the internal read pointer and decreases FIFO level. If reading beyond end of FIFO, data will return 00h. There is no underrun flag, this is not an error condition. Use ams SDK functions to read from the FIFO register to keep the reading in synchronization with the ADC channel selection. If synchronization is no concern use [fifoh[7:0] : fifol[7:2]] as ADC result as the ADC data is multiplied by x4 before it is pushed in to the FIFO. FIFOl[0] is used as an ADC first channel indication. The first channel indication bit toggles upon every new entry unless the first ADC

Document Feedback AS7038RB Functional Description Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 106 channel is transmitted. Then toggling can be stopped for up to 5 FIFO entries and the very first stopping indicates the first ADC channel. To allow encoding of any number of ADC channels, the first ADC channel encoding is dropped from time to time. FIFOH (Address 0xff) Figure 144: FIFOH Register Addr: 0xff FIFOH Bit Bit Name Default Access Bit Description 7:0 fifoh 0 PUSHPOP High byte of FIFO See Interrupts for the actual FIFO interrupt.

7.1.22 Digital Interface

After setting the pin ENABLE=1 the AS7038RB registers can be accessed by the I²C interface. Before enabling any additional function (current source, TIA, ADC…) set the bit ldo_en=1 to set the internal LDO to normal mode. For operating the ADC or the sequencer enable the oscillator by setting osc_en =1 GPIO Pins Figure 145: GPIO Pin Diagram VDD GND GPIO0...3 to analog pullup/pulldown controlled by gpio_p enabled if gpio_a=0 gpio_i enabled if gpio_e=1 gpio_o

Document Feedback AS7038RB Functional Description Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 107 Interrupts An interrupt output pin INT can be used to interrupt the host. Following interrupt sources are possible: irq_adc: End of ADC conversion irq_sequencer: End of sequencer sequence reached. irq_ltf: A light-to-frequency conversion is finished. irq_adc_threshold: ADC threshold triggered – see ADC Threshold. irq_fifothreshold: FIFO almost full (as defined in bit fifo_threshold) irq_fifooverflow: FIFO overflow (error condition, data is lost) irq_clipdetect: TIA output and/or SD output exceeded threshold– see details in CLIPSTATUS irq_led_supply_low: led supply low comparator triggered – see details in LEDSTATUS Depending on the setting in register INTENAB each of the above interrupt source can assert INT output pin (active low).

7.2 I2C

The AS7038RB includes an I²C slave using an I²C address of 0x30 (7-bit format; R/W bit has to be added) respectively 60 h (8-bit format for writing) and 61 h (8-bit format for reading). It expects external pull-up resistors.

7.2.1 I2C Serial Interface

• Fast mode (400 kHz) and standard mode (100 kHz) support
• 7+1-bit addressing mode
• Write formats: Single-Byte-Write, Page-Write
• Read formats: Current-Address-Read, Random-Read, Sequential-Read
• SDA input delay and SCL spike filtering by integrated RC-components

Document Feedback AS7038RB Functional Description Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 110 I²C Sequential Read: Shows the format of an I²C sequential read access Sequential Read is the extended form of Random Read, as more than one register -data bytes are transferred subsequently. In difference to the Random Read, for a sequential read the transferred register-data bytes are responded by an acknowledge from the master. The number of data bytes transferred in one sequence is unlimited (consider the behavior of the word-address counter). To terminate the transmission the master has to send a not-acknowledge following the last data byte and generate the STOP condition subsequently. Figure 151: I²C Current Address Read I²C Current Address Read: Shows the format of an I²C current address read access. To keep the access time as small as possible, this format allows a read access without the word address transfer in advance to the data transfer. The bus is idle and the master issues a START condition followed by the Device-Read address. Analogous to Random Read, a single byte transfer is terminated with a not-acknowledge after the 1st register byte. Analogous to Sequential Read an unlimited number of data bytes can be transferred, where the data bytes has to be responded with an acknowledge from the master. For termination of the transmission the master sends a not- acknowledge following the last data byte and a subsequent STOP condition. CONTROL (Address 0x00) Figure 152: CONTROL Register Addr: 0x00 CONTROL Bit Bit Name Default Access Bit Description 7:5 Not used 0 RW Not used 4 hs_en 0 RW Enable I2C high speed 2 clk_def 0 RW Set the internal system frequency Programming is only possible if oscillator is be disable 0:2 MHz. 1:1 MHz S DW A WA A NA read register WA++ dataSr DR P WA++

Document Feedback AS7038RB Functional Description Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 111 Addr: 0x00 CONTROL Bit Bit Name Default Access Bit Description 1 osc_en 0 RW Enable the oscillator. The oscillator must be enabled for any analog block (ADC, sequencer, optical frontend, sequencer); not mandatory for current sinks or ECG amplifier 0 ldo_en 0 RW If the EN input is not asserted, the chip is in reset If asserted, I²C transactions are possible. Upon assertion of ldo_en, the reference and the LDO are enabled The LDO must be enabled for anything but plain I²C register read/write GPIO_A (Address 0x08) Figure 153: GPIO_A Register Addr: 0x08 GPIO_A Bit Bit Name Default Access Bit Description 7:4 Not used 0 RW Not used 3 gpio3_a 0 RW 1=Put GPIO3 in analog mode; set this bit when used for an analog function e.g. the electrical frontend. If set execute following I²C commands (otherwise an internal pulldown will be enabled) in this sequence: Write 0x47 to register 0xC6 Write 0x0C to register 0xC2 Write 0x0C to register 0xC3 2 gpio2_a 0 RW 1=Put GPIO2 in analog mode If set execute following I²C commands (otherwise an internal pulldown will be enabled) in this sequence: Write 0x47 to register 0xC6 Write 0x0C to register 0xC2 Write 0x0C to register 0xC3 1 gpio1_a 0 RW 1=Put GPIO1 in analog mode 0 gpio0_a 0 RW 1=Put GPIO0 in analog mode

Document Feedback AS7038RB Functional Description Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 114 Addr: 0x0d GPIO_SR Bit Bit Name Default Access Bit Description 3 gpio3_sr 0 RW GPIO3 slew rate configuration 0: Default slew rate 1: Increased slew rate 2 gpio2_sr 0 RW GPIO2 slew rate configuration 1 gpio1_sr 0 RW GPIO1 slew rate configuration 0 gpio0_sr 0 RW GPIO0 slew rate configuration GPIO_SYNC (Address 0x0f) Figure 159: GPIO_SYNC Register Addr: 0x0f GPIO_SYNC Bit Bit Name Default Access Bit Description 7:3 Not used 0 RW Not used 2 gpio_edge 0 RW Used edge on selected GPIO for synchronization. 0=posedge 1=negedge 1:0 gpio_select 0 RW 0: GPIO0 1: GPIO1 2: GPIO2 3: GPIO3 An external synchronization signal can be used to start the sequencer for an ADC cycle The synchronization signal is available via a GPIO. The used GPIO and Edge (positive, negative or both) can be programmed.

Document Feedback AS7038RB Functional Description Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 115 SUBID (Address 0x91) Figure 160: SUBID Register Addr: 0x91 SUBID Bit Bit Name Default Access Bit Description 7:3 subid NA RO Defines product version. Do not rely on bits defined as ‘X’. 1XXXXb 2:0 Revision NA RO Reserved. Do no use and do not rely that the content stays the same for each device. ID (Address 0x92) Figure 161: ID Register Addr: 0x92 ID Bit Bit Name Default Access Bit Description 7:2 id 15 RO Part number identification Value Meaning

010101 AS703x

1:0 Revision NA RO Reserved. Do no use and do not rely that the content stays the same for each device. STATUS (Address 0xa0) Figure 162: STATUS Register Addr: 0xa0 STATUS Bit Bit Name Default Access Bit Description 7 irq_led_supply_low 0 R_PUSH1 Check LEDSTATUS 6 irq_clipdetect 0 R_PUSH1 Check CLIPSTATUS 5 irq_fifooverflow 0 R_PUSH1 FIFO overflow (error condition, new data is lost)

Document Feedback AS7038RB Functional Description Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 116 Addr: 0xa0 STATUS Bit Bit Name Default Access Bit Description 4 irq_fifothreshold 0 R_PUSH1 FIFO is almost full (as defined in fifo_threshold, usually 3/4) 3 irq_adc_threshold 0 R_PUSH1 The ADC value was above the programmed adc_threshold register setting 2 irq_ltf 0 R_PUSH1 LTF measurement is done. check LTFSTATUS (or ignore it) 1 irq_sequencer 0 R_PUSH1 All configured sequencer iterations have finished 0 irq_adc 0 R_PUSH1 ADC has finished The STATUS register shows the current state of the interface. Some bits in here can trigger an interrupt. An asserted bit can be cleared by writing a '1' to it - in case of irq_led_supply_low and irq_clipdetect, this also clears the underlying condition in the CLIPSTATUS and LEDSTATUS registers. The FIFO threshold interrupt cannot be cleared directly, but only by lowering the FIFO level. The FIFO overflow interrupt is sticky and must be cleared explicitly. STATUS2 (Address 0xa1) Figure 163: STATUS2 Register Addr: 0xa1 STATUS2 Bit Bit Name Default Access Bit Description 7:3 Not used 0 R_PUSH1 Not used 2 irq_ltf_threshold_high 0 R_PUSH1 The LTF value was above the programmed ltf_threshold_high register setting 1 irq_ltf_threshold_low 0 R_PUSH1 The LTF value was below the programmed ltf_threshold_low register setting

Document Feedback AS7038RB Functional Description Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 117 Addr: 0xa1 STATUS2 Bit Bit Name Default Access Bit Description 0 irq_ecg_threshold 0 R_PUSH1 If programmed ecg_leadsdet_pol=0, the ecg ADC value was below the programmed ecg_threshold_low setting If programmed ecg_leadsdet_pol=1, the ecg ADC value was above the programmed ecg_threshold_high setting The STATUS2 register shows the current state of the interface. Some bits in here can trigger an interrupt. In normal mode, an asserted bit can be cleared by writing a '1' to it (in normal mode). In clear-on-read mode, reading the STATUS2 register clears all bits. CLIPSTATUS (Address 0xa2) Figure 164: CLIPSTATUS Register Addr: 0xa2 CLIPSTATUS Bit Bit Name Default Access Bit Description 7:4 Not used 0 RO Not used 3 pd_clipdetect_l 0 RO If this bit is asserted, photo diode amplifier has been below the lower threshold 2 pd_clipdetect_h 0 RO If this bit is asserted, photo diode amplifier has been above the upper threshold 1 sd_clipdetect_l 0 RO If this bit is asserted, photo diode amplifier has been below the lower threshold 0 sd_clipdetect_h 0 RO If this bit is asserted, photo diode amplifier has been above the upper threshold

Document Feedback AS7038RB Functional Description Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 120 Addr: 0xaa INTR Bit Bit Name Default Access Bit Description 3 irq_adc_threshold_intr 0 RO 2 irq_ltf_intr 0 RO 1 irq_sequencer_intr 0 RO 0 irq_adc_intr 0 RO The INTR registers shows the bit or bits that are responsible for an asserted interrupt. Effectively, these bits are OR-ed together to drive the interrupt pin INT low (open drain output). INTR2 (Address 0xab) Figure 169: INTR2 Register Addr: 0xab INTR2 Bit Bit Name Default Access Bit Description 7:3 Not used 0 RO Not used 2 irq_ltf_threshold_high_intr 0 RO ltf_treshold_high in ltf0or/and ltf1 1 irq_ltf_threshold_low_intr 0 RO ltf_treshold_low in ltf0or/and ltf1 0 irq_ecg_threshold_intr 0 RO ecg_treshold_high or ecg_treshold_low

Document Feedback AS7038RB

Application Information

Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 121

8 Application Information

8.1 Application Examples

The following figure shows the complete integration of the AS7038RB in a mobile optical measurement system for HRM, SpO2, GSR (galvanic skin resistivity) and skin temperature using an NTC. The device can be powered directly by a Li-ion battery as it has its own power management. Nevertheless the I2C interface can be powered by 1.8 V circuitry. Information AS7038RB can be used in the same configuration for e.g. a fitness band or a smart watch. Figure 170: AS7038RB Optical SpO2 and HRM Measurement System for Wrist Based Application AS7038RB I2C, Optical & Electrical Frontend, ECG Amp.SCL SDA ENABLE GPIO3 GPIO2 GPIO1 LDO Ref AGND SIGREFVDD V_LDO GND VD1 VD2 VD4 VD3 LED Supply Host Processor ON=0,OFF=1 VDD PMIC +Charger LED Supply VBAT VBAT NTCGSR Electrodes to ENABLE for on/off Accelerometer GPIO0 VBAT INT connect unused current sinks to GND ECG_REF ECG_INN ECG_INP SIGREF_ECG LED Supply LED Supply

Document Feedback AS7038RB Package Drawings & Markings Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 122

9 Package Drawings & Markings

Figure 171: Ref. Min Nom Max A 0.55 0.65 0.75 A1 0.3 REF A2 0.35 REF D 3.82 BSC E 2.92 BSC W 0.25 0.3 0.35 L 0.3 0.35 0.4 e 0.45 BSC N 22 D1 2.7 BSC E1 1.35 BSC SD --- BSC SE 0.226 BSC aaa 0.1 bbb 0.1 ddd 0.08 (1) All dimensions are in millimeters. Angles in degrees. (2) Dimensioning and tolerancing conform to ASME Y14.5M-1994. (3) N is the total number of terminals. (4) This package contains no lead (Pb). (5) This drawing is subject to change without notice. RoHS Green

Document Feedback AS7038RB Tape & Reel Information Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 123

10 Tape & Reel Information

Figure 172: AS7038RB Tape Dimensions

Document Feedback AS7038RB Soldering & Storage Information Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 124

11 Soldering & Storage Information

Figure 173: Solder Reflow Profile Graph Figure 174: Solder Reflow Profile Parameter Reference Device Average temperature gradient in preheating 2.5 °C/s Soak time tsoak 2 to 3 minutes Time above 217 °C (T1) t1 Max 60 s Time above 230 °C (T2) t2 Max 50 s Time above Tpeak – 10 °C (T3) t3 Max 10 s Peak temperature in reflow Tpeak 260 °C Temperature gradient in cooling Max −5 °C/s

Document Feedback AS7038RB Revision Information Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 125 Changes from previous version to current revision v2-00 Page Update Figure 29 36

• Page and figure numbers for the previous version may differ from page and figure numbers in the current revision.
• Correction of typographical errors is not explicitly mentioned.

Document Feedback AS7038RB Legal Information Datasheet • PUBLIC DS000726 • v2-00 • 2021-Jun-02 126 │ 126

13 Legal Information

Copyrights & Disclaimer Copyright ams AG, Tobelbader Strasse 30, 8141 Premstaetten, Austria-Europe. Trademarks Registered. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. Devices sold by ams AG are covered by the warranty and patent indemnification provisions appearing in its General Terms of Trade. ams AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein. ams AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with ams AG for current information. This product is intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by ams AG for each application. This product is provided by ams AG “AS IS” and any express or implied warranties, including, but not limited to the implied warranties of merchantability and fitness for a particular purpose are disclaimed. ams AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of ams AG rendering of technical or other services. RoHS Compliant & ams Green Statement RoHS Compliant: The term RoHS compliant means that ams AG products fully comply with current RoHS directives. Our semiconductor products do not contain any chemicals for all 6 substance categories plus additional 4 substance categories (per amendment EU 2015/863), including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, RoHS compliant products are suitable for use in specified lead-free processes. ams Green (RoHS compliant and no Sb/Br/Cl): ams Green defines that in addition to RoHS compliance, our products are free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) and do not contain Chlorine (Cl not exceed 0.1% by weight in homogeneous material). Important Information: The information provided in this statement represents ams AG knowledge and belief as of the date that it is provided. ams AG bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. ams AG has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ams AG and ams AG suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Headquarters ams AG Tobelbader Strasse 30

8141 Premstaetten

Austria, Europe Tel: +43 (0) 3136 500 0 Please visit our website at www.ams.com Buy our products or get free samples online at www.ams.com/Products Technical Support is available at www.ams.com/Technical-Support Provide feedback about this document at www.ams.com/Document-Feedback For sales offices, distributors and representatives go to www.ams.com/Contact For further information and requests, e-mail us at ams_sales@ams.com