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Rev. 4.4 10/13 Micross Components reserves the right to change products or specifi cations without notice. For more products and information please visit our web site at www.micross.com 256K x 36 SSRAM Flow-Through, Synchronous Burst SRAM
FEATURES
Organized 256K x 36 Fast Clock and OE\\ access times Single +3.3V +0.3V/-0.165V power supply (VDD) SNOOZE MODE for reduced-power standby Common data inputs and data outputs Individual BYTE WRITE control and GLOBAL WRITE Three chip enables for simple depth expansion and address pipelining Clock-controlled and registered addresses, data I/Os and control signals Internally self-timed WRITE cycle Burst control (interleaved or linear burst) Automatic power-down for portable applications Low capacitive bus loading 100-lead TQFP package for high density, high speed RoHs compliant options available OPTIONS MARKING Timing 7.5ns/8.5ns/117MHz -7.5 8.5ns/10ns/100MHz -8.5 10ns/15ns/66MHz -10 Packages TQFP DQ No. 1001 Operating Temperature Ranges Military (-55oC to +125oC) /XT Enhanced (-40oC to +105oC) /ET Industrial (-40oC to +85oC) /IT PIN ASSIGNMENT (Top View) 100-pin TQFP (DQ) GENERAL DESCRIPTION The AS5SS256K36 employs high-speed, low-power CMOS designs that are fabricated using an advanced CMOS process. This 8Mb Synchronous Burst SRAM integrates a 256K x 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. All synchronous inputs pass through registers controlled by a positive-edge-triggered single-clock input (CLK). The synchronous inputs include all addresses, all data inputs, active LOW chip enable (CE\\), two additional chip enables for easy depth expansion (CE2\\, CE2), burst control inputs (ADSC\\, ADSP\\, ADV\\), byte write enables (BWx\\) and global write (GW\\). DQPc DQc DQc V DDQ Vss DQc DQc DQc DQc Vss V DDQ DQc DQc Vss V DD NC Vss DQd DQd V DDQ Vss DQd DQd DQd DQd Vss V DDQ DQd DQd DQPd DQPb DQb DQb V DDQ Vss DQb DQb DQb DQb Vss V DDQ DQb DQb Vss NC V DD ZZ DQa DQa V DDQ Vss DQa DQa DQa DQa Vss V DDQ DQa DQa DQPa SA SA SA SA SA SA SA SA NF V DD Vss DNU DNU SA0 SA1 SA SA SA SA MODE 100 SA SA ADV\\ ADSP\\ ADSC\\ OE\\ BWE\\ GW\\ CLK Vss V DD CE2\\ BWa\\ BWb\\ BWc\\ BWd\\ CE2 CE\\ SA SA
Rev. 4.4 10/13 Micross Components reserves the right to change products or specifi cations without notice. GENERAL DESCRIPTION (continued) Asynchronous inputs include the output enable (OE\\), clock (CLK) and snooze enable (ZZ). There is also a burst mode input (MODE) that selects between interleaved and linear burst modes. The data-out (Q), enabled by OE\\, is also asynchronous. WRITE cycles can be from one to four bytes wide as controlled by the write control inputs. Burst operation can be initiated with either address status processor (ADSP\\) or address status controller (ADSC\\) inputs. Subsequent burst addresses can be internally generated as controlled by the burst advance input (ADV\\). Address and write control are registered on-chip to simplify WRITE cycles. This allows self-timed WRITE cycles. Individual byte enables allow individual bytes to be written. During WRITE cycles on the x18 device, BWa\\ controls DQa’s and DQPa; BWb\\ controls DQb’s and DQPb; BWc\\ controls DQc’s and DQPc; BWd\\ controls DQd’s and DQPd. GW\\ LOW causes all bytes to be written. Parity bits are also featured on this device. This 8Mb Synchronous Burst SRAM operates from a +3.3V V DD power supply, and all inputs and outputs are TTL- compatible. The device is ideally suited for 486, Pentium ©, 680x0 and PowerPCTM systems and those systems that benefi t from a wide synchronous data bus. 18 18 16 18 SA0, SA1, SAs SA0-SA1 MODE ADV\\ CLK SA1' SA0' BWd\\ BWc\\ DQs DQPa DQPb DQPc BWb\\ DQPd BWa\\ BWE\\ GW\\ OE\\ ADDRESS REGISTER BINARY COUNTER AND LOGIC Q0CL ADSC\\ ADSP\\ BYTE "d" WRITE REGISTER BYTE "c" WRITE REGISTER BYTE "b" WRITE REGISTER BYTE "a" WRITE REGISTER ENABLE REGISTERCE\\ CE2 CE2\\ BYTE "d" WRITE DRIVER BYTE "c" WRITE DRIVER BYTE "b" WRITE DRIVER BYTE "a" WRITE DRIVER 256K x 9 x 4 (x36) MEMORY ARRAY SENSE AMPS OUTPUT BUFFERS INPUT REGISTERS FUNCTIONAL BLOCK DIAGRAM NOTE: Functional Block Diagrams illustrate simplifi ed device operation. See Truth Table, Pin Descriptions and time diagrams for detailed information.
Rev. 4.4 10/13 Micross Components reserves the right to change products or specifi cations without notice. PIN DESCRIPTION Pin Number SYMBOL TYPE DESCRIPTION 32-35, 44-50, 81, 82, 99, 100 SA0 SA1 SA Input Synchronous Address Inputs: These inputs are registered and must meet the setup and hold times around the rising edge of CLK. Two different pinouts are available for the TQFP packages. BWa\\ BWb\\ BWc\\ BWd\\ Input Synchronous Byte Write Enables: These active LOW inputs allow individual bytes to be written and must meet the setup and hold times around the rising edge of CLK. A byte write enable is LOW for a WRITE cycle and HIGH for a READ cycle. Bwa\\ controls DQa pins and DQPa; Bwb\\ controls DQb pins and DQPb; Bwc\\ controls DQc pins and DQPc; Bwd\\ controls DQd pins and DQPd. Parity bits are featured on this device.
87 BWE\\ Input
Byte Write Enable: This active LOW input permits BYTE WRITE operations and must meet the setup and hold items around the rising edge of CLK.
88 GW\\ Input
Global Write: This active LOW input allows a full 36-bit WRITE to occur independent of the BWE\\ and BWx\\ lines and must meet the setup and hold times around the rising edge of CLK.
89 CLK Input
Clock: CLK registers address, data, chip enable, byte write enables and burst control inputs on its rising edge. All synchronous inputs must meet setup and hold times around the clock's rising edge.
98 CE\\ Input
Synchronous Chip Enable: This active LOW input is used to enable the device and conditions the internal use of ADSP\\. CE\\ is sampled only when a new external address is loaded.
92 CE2\\ Input Synchronous Chip Enable: This active LOW input is used to enable the
device and is sampled only when a new external address is loaded.
97 CE2 Input Synchronous Chip Enable: This active HIGH input is used to enable the
device and is sampled only when a new external address is loaded.
86 OE\\ Input Output Enable: This active LOW, asynchronous input enables the data
I/O output drivers.
83 ADV\\ Input
Synchronous Address Advance: This active LOW input is used to advance the internal burst counter, controlling burst access after the external address is loaded. A HIGH on this pin effectively causes wait states to be generated (no address advance). To ensure use of correct address during a WRITE cycle, ADV\\ must be HIGH at the rising edge of the first clock after an ADSP\\ cycle is initiated.
85 ADSC\\ Input
Synchronous Address Status Controller: This active LOW input interrupts any ongoing burst, causing a new external address to be registered. A READ or WRITE is performed using the new address if CE\\ is LOW. ADSC\\ is also used to place the chip into power-down state when CE\\ is HIGH.
Rev. 4.4 10/13 Micross Components reserves the right to change products or specifi cations without notice. PIN DESCRIPTION (continued) Pin Number SYMBOL TYPE DESCRIPTION
84 ASDP\\ Input
Synchronous Address Status Processor: This active LOW inputs interrupts any ongoing burst, causing a new external address to be registered. A READ is performed using the new address, independent of the byte write enables and ADSC\\, but dependent upon CE\\, CE2 and CE2\\. ADSP\\ is ignored if CE\\ is HIGH. Power-down state is entered if CE2 is LOW or CE2\\ is HIGH.
31 MODE Input
MODE: This inputs selects the burst sequence. A LOW on this pin select "linear burst." NC or HIGH on this pin selects "interleaved burst." Do not alter input state while device is operating.
64 ZZ Input
Snooze Enable: This active HIGH, asynchronous input causes the device to enter a low-power standby mode in which all data in the memory array is retained. When ZZ is active, all other inputs are ignored. (a) 52, 53, 56-59, 62, 63 (b) 68, 69, 72-75, 78, 79 (c) 2, 3, 6-9, 12, (d) 18, 19, 22-25, 28, 29 DQa DQb DQc DQd Input/ Output SRAM Data I/O's: Byte "a" is DQa pins; Byte "b" is DQb pins; Byte "c" is DQc pins; Byte "d" is DQd pins. Input data must meet setup and hold times around the rising edge of CLK. NC/DQPa NC/DQPb NC/DQPc NC/DQPd NC/ I/O Parity Data I/Os: Byte "a" parity is DQPa; Byte "b" parity is DQPb; Byte "c" parity is DQPc; Byte "d" parity is DQPd. 15, 41, 65, 91 V DD Supply Power Supply: See DC Electrical Characteristics and Operating Conditions for range. 4, 11, 20, 27, 54, 61, 70, 77 VDDQ Supply Isolated Output Buffer Supply: See DC Electrical Characteristics and Operating Conditions for range. 5, 10, 14, 17, 21, 71, 76, 90 Vss Supply Ground: GND 38, 39 DNU --- Do Not Use: These signals may either be unconnected or wired to GND to improve package heat dissipation. 16, 66 NC --- No Connect: These signals are not internally connected and may be connected to GND to improve package heat dissipation.
42 NF ---
No Function: These pins are internally connected to the die and have the capacitance of an input pin. It is allowable to leave these pins unconnected or driven by signals. Pin 42 is reserved as an address upgrade pin for the 16Mb Synchronous Burst.
Rev. 4.4 10/13 Micross Components reserves the right to change products or specifi cations without notice. INTERLEAVED BURST ADDRESS TABLE (MODE = NC OR HIGH) FIRST ADDRESS (EXTERNAL) SECOND ADDRESS (INTERNAL) THIRD ADDRESS (INTERNAL) FOURTH ADDRESS (INTERNAL) X…X00 X…X01 X…X10 X…X11 X…X01 X…X00 X…X11 X…X10 X…X10 X…X11 X…X00 X…X01 X…X11 X…X10 X…X01 X…X00 LINEAR BURST ADDRESS TABLE (MODE = LOW) FIRST ADDRESS (EXTERNAL) SECOND ADDRESS (INTERNAL) THIRD ADDRESS (INTERNAL) FOURTH ADDRESS (INTERNAL) X…X00 X…X01 X…X10 X…X11 X…X01 X…X10 X…X11 X…X00 X…X10 X…X11 X…X00 X…X01 X…X11 X…X00 X…X01 X…X10 PARTIAL TRUTH TABLE FOR WRITE COMMANDS FUNCTION GW\\ BWE\\ BWa\\ BWb\\ BWc\\ BWd\\ R E A D HHXXXX R E A D HLHHHH WRITE Byte "a" H L L H H H WRITE All Bytes H L L L L L WRITE All Bytes L X X X X X
Rev. 4.4 10/13 Micross Components reserves the right to change products or specifi cations without notice. TRUTH TABLE OPERATION ADDRESS USED CE\\ CE2\\ CE2 ZZ ADSP\\ ADSC\\ ADV\\ WRITE\\ OE\\ CLK DQ Deselected Cycle, Power-Down None H X X L X L X X X L-H High-Z Deselected Cycle, Power-Down None L X L L L X X X X L-H High-Z Deselected Cycle, Power-Down None L H X L L X X X X L-H High-Z Deselected Cycle, Power-Down None L X L L H L X X X L-H High-Z Deselected Cycle, Power-Down None L H X L H L X X X L-H High-Z SNOOZE MODE, Power-Down None X X X H X X X X X X High-Z READ Cycle, Begin Burst External L L H L L X X X L L-H Q READ Cycle, Begin Burst External L L H L L X X X H L-H High-Z WRITE Cycle, Begin Burst External L L H L H L X L X L-H D READ Cycle, Begin Burst External L L H L H L X H L L-H Q READ Cycle, Begin Burst External L L H L H L X H H L-H High-Z READ Cycle, Continue Burst Next X X X L H H L H L L-H Q READ Cycle, Continue Burst Next X X X L H H L H H L-H High-Z READ Cycle, Continue Burst Next H X X L X H L H L L-H Q READ Cycle, Continue Burst Next H X X L X H L H H L-H High-Z WRITE Cycle, Continue Burst Next X X X L H H L L X L-H D WRITE Cycle, Continue Burst Next H X X L X H L L X L-H D READ Cycle, Suspend Burst Current X X X L H H H H L L-H Q READ Cycle, Suspend Burst Current X X X L H H H H H L-H High-Z READ Cycle, Suspend Burst Current H X X L X H H H L L-H Q READ Cycle, Suspend Burst Current H X X L X H H H H L-H High-Z WRITE Cycle, Suspend Burst Current X X X L H H H L X L-H D WRITE Cycle, Suspend Burst Current H X X L X H H L X L-H D NOTE: 2. For WRITE\\, L means any one or more byte write enable signals (BWa\\, BWb\\, BWc\\, or BWd\\) and BWE\\ are LOW or GW\\ is LOW. WRITE\\ = H for all BWx\\, BWE\\, GW\\ HIGH. 3. BWa\\ enables WRITEs to DQa pins, DQPa. BWb\\ enables WRITEs to DQb pins, DQPb. BWc\\ enables WRITEs to DQc pins, DQPc. BWd\\ enables WRITEs to DQd pins, DQPd. 4. All inputs except OE\\ and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK. 5. Wait states are inserted by suspending burst. 6. For a WRITE operation following a READ operation, OE\\ must be HIGH before the input data setup time and held HIGH throughout the input data hold time. 7. This device contains circuitry that will ensure the outputs will be High-Z during power-up. 8. ADSP\\ LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte write enable signals and BWE\\ LOW or GW\\ LOW for the subsequent L-H edge of CLK. Refer to WRITE timing diagram for clarifi cation.
Rev. 4.4 10/13 Micross Components reserves the right to change products or specifi cations without notice. ABSOLUTE MAXIMUM RATINGS* V *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condi- tions above those indicated in the operation section of this specifi cation is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. ** Junction temperature depends upon package type, cycle time, loading, ambient temperature and air fl ow, and humidity. 3.3V I/O DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (-55oC to +125oC, -40oC to +105oC or -40oC to +85oC; VDD, VDDQ = +3.3V +0.3V/-0.165V un- less otherwise noted) PARAMETER CONDITION SYMBOL MIN MA X UNITS NOTES Input High (Logic 1) Voltage VIH 2.2 VCC +0.3 V1 , 2 Input Low (Logic 0) Voltage VIL -0.3 0.8 V 1, 2 Input Leakage Current OV < VIN < Vcc IL I -5 5 P$ 3 Output Leakage Current Output(s) disabled, OV < VOUT < Vcc ILO -5 5 P$ Output High Voltage IOH = -4.0 mA VOH 2.4 -- V 1, 4 Output Low Voltage IOL = 8.0 mA VOL --- 0.4 V 1, 4 Supply Voltage VDD 3.135 3.6 V 1 Isolated Output Buffer Supply VDDQ 3.135 3.6 V 1, 5 NOTES: 1. All voltages referenced to Vss (GND). 2. Overshoot: VIH < +4.6V for t<tKC/2 for I < 20mA Undershoot: VIL > -0.7V for t<tKC/2 for I < 20mA Power-up: VIH < +3.6V and VDD < 3.135V for t < 200ms 3. MODE and ZZ pins have internal pull-up resistors, and input leakage = +10A 4. The load used for VOH, VOL testing is shown in Figure 2 for 3.3V I/O. AC load current is higher than the stated DC values. AC I/O curves are available upon request. 5. V DDQ should never exceed VDD. VDD and VDDQ can be connected together. 6. This parameter is sampled. THERMAL RESISTANCE Parameter Description Test Conditions DQ Package DQC Package Unit Ĭ JA Thermal Resistance (Junction to Ambient) 29.41 30.2 oC/W Ĭ JC Thermal Resistance (Junction to Case) 6.31 6.5 oC/W Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51
Rev. 4.4 10/13 Micross Components reserves the right to change products or specifi cations without notice. DESCRIPTION CONDITIONS SYM -7.5 -8.5 -10 UNITS NOTES Power Supply Current: Operating Device selected; all inputs < VIL or > VIH; Cycle time > tKC MIN; VDD = MAX; Outputs open IDD 250 225 200 mA 1, 2, 3 Power Supply Current: Idle Device selected; VDD = MAX; ADSC\\, ADSP\\, ADV\\, GW\\, BWx\\ >VIH; All inputs < Vss+ 0.2 or > VDD -0.2; Cycle time < tKC MIN; Outputs open IDD1 160 150 140 mA 1, 2, 3 CMOS Standby Device deselected; VDD = MAX; All inputs < Vss +0.2 or > VDD -0.2; All inputs static; CLK frequency = 0 ISB2 90 90 90 mA 2, 3 TTL Standby Device deselected; VDD = MAX; All inputs < VIL or > VIH; All inputs static; CLK frequency = 0 ISB3 130 130 130 mA 2, 3 MAX IDD OPERATING CONDITIONS AND MAXIMUM LIMITS (-55oC to +125oC or -40oC to +85oC) CAPACITANCE DESCRIPTION CONDITIONS SYM MA X UNITS NOTES Input Capacitance CI 6p F4 Input/Output Capacitance CO 8p F4 TA = 25oC; f = 1MHz; VDD = 3.3V NOTES: 1. IDD is specifi ed with no output current and increases with faster cycle times. IDDQ increases with faster cycle times and greater output loading. 2. “Device deselected” means device is in power-down mode as defi ned in the truth table. “Device selected” means device is active (not in power-down mode). 3. A typical value is measured at 3.3V , 25 oC and 15ns cycle time. 4. This parameter is sampled.
Rev. 4.4 10/13 Micross Components reserves the right to change products or specifi cations without notice. ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Note 1) (-55oC to +125oC or -40oC to +85oC) MIN MA X MIN MA X MIN MA X CLOCK Clock cycle time tKC 8.5 10.0 15.0 ns Clock frequency tKF 117 100 66 MHz Clock HIGH time tKH 2.5 3.0 4.0 ns 2 Clock LOW time tKL 2.5 3.0 4.0 ns 2 OUTPUT TIMES Clock to output valid tKQ 7.5 8.5 10.0 ns Clock to output invalid tKQX 2.5 2.5 2.5 ns 3 Clock to output in Low-Z tKQLZ 2.5 2.5 2.5 ns 3, 4, 5, 6, Clock to output in High-Z tKQHZ 4.0 5.0 5.0 ns 3, 4, 5, 6, OE\\ to output valid tOEQ 3.4 4.4 5.0 ns 7 OE\\ to output in Low-Z tOELZ 0 0 0 ns 3, 4, 5, 6, OE\\ to output in High-Z tOEHZ 3.5 4.4 5.0 ns 3, 4, 5, 6, SETUP TIMES Address tAS 1.5 1.8 2.0 ns 8, 9 Address status (ADSC\\, ADSP\\) tADSS 1.5 1.8 2.0 ns 8, 9 Address advance (ADV\\) tAAS 1.5 1.8 2.0 ns 8, 9 Byte write enables (BWa\\ - BWd\\, GW\\, BWE\\) tWS 1.5 1.8 2.0 ns 8, 9 Data-in tDS 1.5 1.8 2.0 ns 8, 9 Chip enable (CE\\) tCES 1.5 1.8 2.0 ns 8, 9 HOLD TIMES Address tAH 0.5 0.5 0.5 ns 8, 9 Address status (ADSC\\, ADSP\\) tADSH 0.5 0.5 0.5 ns 8, 9 Address advance (ADV\\) tAAH 0.5 0.5 0.5 ns 8, 9 Byte write enables (BWa\\ - BWd\\, GW\\, BWE\\) tWH 0.5 0.5 0.5 ns 8, 9 Data-in tDH 0.5 0.5 0.5 ns 8, 9 Chip enable (CE\\) tCEH 0.5 0.5 0.5 ns 8, 9 UNITS NOTESSYMBOLDESCRIPTION -10-8.5-75 NOTE: 1. Test conditions as specifi ed with the output loading shown in Figure 1 unless otherwise noted. 2. Measured as HIGH above VIH and LOW below VIL. 3. This parameter is measured with the output loading shown in Figure 2 for 3.3V I/O. 4. This parameter is sampled. 5. Transition is measured +500mV from steady state voltage. 6. Refer to Technical Note TN-58-09, “Synchronous SRAM Bus Contention Design Considerations,” for a more thorough discussion on these parameters. 7. OE\\ is a “Don’t Care” when a byte write enable is sampled LOW. 8. A READ cycle is defi ned by byte write enables all HIGH or ADSP\\ LOW for the required setup and hold times. A WRITE cycle is defi ned by at least one byte write enable LOW and ADSP\\ HIGH for the required setup and hold times. 9. This is a synchronous device. All addresses must meet the specifi ed setup and hold times for all rising edges of CLK when either ADSP\\ or ADSC\\ is LOW and chip enabled. All other synchronous inputs must meet the setup and hold times with stable logic levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be valid at each rising edge of CLK when either ADSP\\ or ADSC\\ is LOW to remain enabled.
Rev. 4.4 10/13 Micross Components reserves the right to change products or specifi cations without notice. OUTPUT LOADS +3.3v DQ Fig. 2 3.3V I/O OUTPUT LOAD EQUIV ALENT 351 5 pF 317 Fig. 1 3.3V I/O OUTPUT LOAD EQUIV ALENT DQ 50 Z0=50 Vt = 1.5V AC TEST CONDITIONS NOTE: SRAM timing is dependent upon the capacitive loading on the outputs.
Rev. 4.4 10/13 Micross Components reserves the right to change products or specifi cations without notice. DESCRIPTION CONDITIONS SYM MIN MAX UNITS NOTES Current during SNOOZE MODE ZZ > VIH ISB2Z 80 mA ZZ active to input ignored tZZ 2tcyc ns 1 ZZ inactive to input sampled tRZZ 2tcyc ns 1 ZZ active to snooze current tZZI 2tcyc ns 1 ZZ inactive to exit snooze current tRZZI 0n s 1 SNOOZE MODE SNOOZE MODE is a low-current, “power-down” mode in which the device is deselected and current is reduced to ISB2Z. The duration of SNOOZE MODE is dictated by the length of time ZZ is in a HIGH state. After the device enters SNOOZE MODE, all inputs except ZZ become gated inputs and are ignored. ZZ is an asynchronous, active HIGH input that causes the device to enter SNOOZE MODE. When ZZ becomes a logic HIGH, I SB2Z is guaranteed after the setup time tZZ is met. Any READ or WRITE operation pending when the device enters SNOOZE MODE is not guaranteed to complete successfully. Therefore, SNOOZE MODE must not be initiated until valid pending operations are completed. SNOOZE MODE ELECTRICAL CHARACTERISTICS NOTE: 1. This parameter is sampled. SNOOZE MODE WAVEFORM CLK ZZ ISUPPLY ALL INPUTS* *Except ZZ Don’t Care tZZ tZZI tRZZ tRZZI tSB2
Rev. 4.4 10/13 Micross Components reserves the right to change products or specifi cations without notice. READ TIMING3 NOTE: 1. Q(A2) refers to output from address A2. Q(A2+1) refers to output from the next internal burst address following A2. 2. CE2\\ and CE2 have timing identical to CE\\. On this diagram, when CE\\ is LOW, CE2\\ is LOW and CE2 is HIGH. When CE\\ is HIGH, CE2\\ is HIGH and CE2 is LOW. 3. Timing is shown assuming that the device was not enabled before entering into this sequence. 4. Outputs are disabled t KQHZ after deselect. CLK ADSP\\ ADSC\\ ADDRESS BWE\\, GW\\, BWa\\ - BWd\\ CE\\ (Note 2) ADV\\ OE\\ tADSH tAS tAH tKQLZ tOEHZ SINGLE READ BURST READ Q t AAS tAAH t Q(A2) Q(A2+2) Q(A2+3) Q(A2) Q(A2+1) Q(A2+2) Q(A1) Q(A2+1) tKC tKL tKH tOEQ tOELZ t KQ Deselect Cycle (note 4) ADSS tADSH t ADSS A2A1 t WS t WH t CEH t CES ADV\\ suspends burst. High-Z t KQ tKQX tKQHZ Burst wraps around to its initial state (Note 1) Don’t Care Undefi ned
Rev. 4.4 10/13 Micross Components reserves the right to change products or specifi cations without notice. NOTE: 1. D(A2) refers to output from address A2. D(A2+1) refers to output from the next internal burst address following A2. 2. CE2\\ and CE2 have timing identical to CE\\. On this diagram, when CE\\ is LOW, CE2\\ is LOW and CE2 is HIGH. When CE\\ is HI GH, CE2\\ is HIGH and CE2 is LOW. 3. OE\\ must be HIGH before the input data setup and held HIGH throughout the data hold time. This prevents input/output data contention for the time period prior to the byte write enable inputs being sampled. 4. ADV\\ must be HIGH to permit a WRITE to the loaded address. 5. Full-width WRITE can be initiated by GW\\ LOW; or GW\\ HIGH and BEW\\, BWa\\ - BWd\\ LOW. WRITE TIMING CLK ADSP\\ ADSS ADSC\\ ADDRESS BWE\\ BWa\\ - BWd\\ CE\\ (See Note) ADV\\ OE\\ tADSH tAS tAH tDS Single WRITE BURST WRITE GW\\ D Extended BURST WRITE t D(A2) D(A2+1) D(A2+2) D(A2+3) D(A3) D(A3+1) D(A3+2) D(A1) D(A2+1) tKC tKL tKH Q High-Z ADSS tADSH t A1 A2 BYTE WRITE signals are ignored when ADSP\\ is LOW. ADSS tADSH t BURST READ ADSC\\ extends burst. WS tWH t WS tWH t (Note 5) CES tCEH t (Note 4) AAS tAAH t ADV\\ suspends burst. (Note 3) tDH tOEHZ (Note 1) Don’t Care Undefi ned
Rev. 4.4 10/13 Micross Components reserves the right to change products or specifi cations without notice. READ/WRITE TIMING3 NOTE: 1. Q(A4) refers to output from address A. Q(A4+1) refers to output from the next internal burst address following A4. 2. CE2\\ and CE2 have timing identical to CE\\. On this diagram, when CE\\ is LOW, CE2\\ is LOW and CE2 is HIGH. When CE\\ is HI GH, CE2\\ is HIGH and CE2 is LOW. 3. The data bus (Q) remains in High-A following a WRITE cycle unless an ADSP\\, ADSC\\ or ADV\\ cycle is performed. 4. GW\\ is HIGH. 5. Back-to-back READs may be controlled by either ADSP\\ or ADSC\\. CLK ADSP\\ ADSS ADSC\\ ADDRESS WEH\\, WEL\\, BWE\\, GW\\ CE\\ (See Note) ADV\\ OE\\ tADSH tAS tAH Back-to-Back READs (Note 5) BURST READ D Back-to-Back WRITEs t Q(A4) Q(A4+1) Q(A4+2) Q(A4+3) D(A5) D(A6) Q(A1) D(A3) A1 A4 Q(A2) SINGLE WRITE Q tKC tKL tKH A3A2 tWS tWH tCES tCEH tDS tDH tOEHZ High-Z tKQ tOELZ (Note 1) Don’t Care Undefi ned
Rev. 4.4 10/13 Micross Components reserves the right to change products or specifi cations without notice. 100-Pin TQFP (Package Designator DQ) MECHANICAL DEFINITION
Rev. 4.4 10/13 Micross Components reserves the right to change products or specifi cations without notice.
ORDERING INFORMATION
EXAMPLE: AS5SS256K36DQ-10/IT Device Number Package Type Speed ns Process AS5SS256K36 DQ -8.5 /* AS5SS256K36 DQ -10 /* *AVAILABLE PROCESSES IT = Industrial Temperature Range -40 oC to +85oC ET = Enhanced Temperature Range -40 oC to +105oC XT = Military Temperature Range -55 oC to +125oC
Rev. 4.4 10/13 Micross Components reserves the right to change products or specifi cations without notice. DOCUMENT TITLE 256K x 36 SSRAM Flow-Through, Synchronous Burst SRAM
REVISION HISTORY
Rev # History Release Date Status
4.0 Removed “A” Version November 2009 Release
4.1 Updated Micross Information January 2010 Release
4.2 Added copper lead frame and RoHS May 2011 Release
compliant options. Added -7.5 speed option and enhanced temp range. Updated thermal resistance: From To ΘJA 40 29.41 oC/W ΘJC 9 6.31 oC/W Updated input/output capacitance and AC test conditions, C I from 4pF to 6pF and C O from 5pF to 8pF. Updated I SB2Z from 10mA to 80mA, and tZZ, tKC and t ZZZ from tKC to 2tKC. Increased min/max Input and output leakage to ± 5 μA. Changed: From To t KQXmin 3.0ns 2.5ns t KQLZmin 3.0ns 2.5ns t OEQ & tOEHZmax 5.0ns 4.4ns I DDmax (-8.5) 325mA 225mA (-10) 250mA 200mA I DD1max (-8.5) 85mA 150mA (-10) 65mA 140mA I SB2max 15mA 90mA I SB3max 30mA 130mA Deleted I SB4 Specifi cation
4.3 Added DQC package on the Thermal September 2011 Release
Resistance table, page 7.